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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib_helper/] [SinglePulseGenerator.vhd] - Blame information for rev 5

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1 3 Andrewski
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-- Entity: SinglePulseGenerator
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-- Date:2011-11-10  
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-- Author: Administrator     
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--
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.utilPkg.all;
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entity SinglePulseGenerator is
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        generic (
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                WIDTH : integer := 3
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        );
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        port (
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                reset : in std_logic;
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                clk : in std_logic;
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                t_in: in std_logic;
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                t_out : out std_logic;
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                pulse : out std_logic
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        );
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end SinglePulseGenerator;
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architecture arch of SinglePulseGenerator is
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        signal rcount : integer range 0 to WIDTH;
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        signal i_t_out : std_logic;
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begin
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        pulse <= to_stdl(t_in /= i_t_out);
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        t_out <= i_t_out;
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        -- buffer reset generator
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        process (reset, clk, t_in) begin
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                if reset = '1' then
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                        i_t_out <= t_in;
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                        rcount <= 0;
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                elsif rising_edge(clk) then
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                        if t_in /= i_t_out then
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                                rcount <= rcount + 1;
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                                if rcount = WIDTH then
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                                        rcount <= 0;
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                                        i_t_out <= t_in;
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                                end if;
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                        end if;
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                end if;
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        end process;
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end arch;
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