OpenCores
URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [wrapper/] [SettingsReg0.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2 13 Andrewski
--This file is part of fpga_gpib_controller.
3
--
4
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation, either version 3 of the License, or
7
-- (at your option) any later version.
8
--
9
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
 
14
-- You should have received a copy of the GNU General Public License
15
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
16
--------------------------------------------------------------------------------
17 3 Andrewski
-- Entity: SettingsReg0
18
-- Date:2011-11-09  
19 13 Andrewski
-- Author: Andrzej Paluch
20 3 Andrewski
--
21
-- Description ${cursor}
22
--------------------------------------------------------------------------------
23
library ieee;
24
use ieee.std_logic_1164.all;
25
use ieee.std_logic_unsigned.all;
26
 
27
 
28
library ieee;
29
use ieee.std_logic_1164.all;
30
use ieee.std_logic_unsigned.all;
31
 
32
entity SettingsReg0 is
33
        port (
34
                reset : in std_logic;
35
                strobe : in std_logic;
36
                data_in : in std_logic_vector (15 downto 0);
37
                data_out : out std_logic_vector (15 downto 0);
38
                ------------- gpib -----------------------------
39
                isLE_TE : out std_logic;
40
                lpeUsed : out std_logic;
41
                fixedPpLine : out std_logic_vector (2 downto 0);
42
                eosUsed : out std_logic;
43
                eosMark : out std_logic_vector (7 downto 0);
44
                lon : out std_logic;
45
                ton : out std_logic
46
        );
47
end SettingsReg0;
48
 
49
architecture arch of SettingsReg0 is
50
 
51
        signal inner_buf : std_logic_vector (15 downto 0);
52
 
53
begin
54
 
55
        data_out <= inner_buf;
56
 
57
        isLE_TE <= inner_buf(0);
58
        lpeUsed <= inner_buf(1);
59
        fixedPpLine <= inner_buf(4 downto 2);
60
        eosUsed <= inner_buf(5);
61
        eosMark <= inner_buf(13 downto 6);
62
        lon <= inner_buf(14);
63
        ton <= inner_buf(15);
64
 
65
        process (reset, strobe) begin
66
                if reset = '1' then
67
                        inner_buf <= "0000000000000000";
68
                elsif rising_edge(strobe) then
69
                        inner_buf <= data_in;
70
                end if;
71
        end process;
72
 
73
end arch;
74
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.