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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [wrapper/] [WriterControlReg1.vhd] - Blame information for rev 6

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Line No. Rev Author Line
1 3 Andrewski
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-- Entity: WriterControlReg1
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-- Date:2011-11-10  
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-- Author: Administrator     
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--
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity WriterControlReg1 is
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        port (
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                reset : in std_logic;
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                strobe : in std_logic;
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                data_in : in std_logic_vector (15 downto 0);
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                data_out : out std_logic_vector (15 downto 0);
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                ------------------ gpib --------------------
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                -- num of bytes available in fifo
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                bytes_available_in_fifo : in std_logic_vector (10 downto 0)
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        );
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end WriterControlReg1;
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architecture arch of WriterControlReg1 is
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begin
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        data_out(10 downto 0) <= bytes_available_in_fifo(10 downto 0);
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        data_out(15 downto 11) <= "00000";
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end arch;
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