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[/] [gpib_controller/] [trunk/] [vhdl/] [test/] [Fifo8b_Test.vhd] - Blame information for rev 11

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Line No. Rev Author Line
1 3 Andrewski 
 
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--------------------------------------------------------------------------------
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-- Fifo8b test
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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use ieee.std_logic_arith.all;
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use work.helperComponents.all;
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ENTITY Fifo8b_Test_vhd IS
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END Fifo8b_Test_vhd;
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ARCHITECTURE behavior OF Fifo8b_Test_vhd IS
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        constant clk_period : time := 1us;
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        SIGNAL reset :  std_logic := '0';
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        SIGNAL clk :  std_logic := '0';
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        -------------- fifo --------------------
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        SIGNAL bytesAvailable : std_logic;
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        SIGNAL availableBytesCount : std_logic_vector(10 downto 0);
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        SIGNAL bufferFull : std_logic;
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        SIGNAL resetFifo : std_logic := '0';
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        ----------------------------------------
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        SIGNAL data_in : std_logic_vector(7 downto 0) := (others => '0');
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        SIGNAL ready_to_write : std_logic;
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        SIGNAL strobe_write : std_logic := '0';
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                ----------------------------------------
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        SIGNAL data_out : std_logic_vector(7 downto 0);
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        SIGNAL ready_to_read : std_logic;
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        SIGNAL strobe_read : std_logic := '0';
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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        fifo: Fifo8b port map (
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                reset => reset,
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                clk => clk,
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                -------------- fifo --------------------
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                bytesAvailable => bytesAvailable,
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                availableBytesCount => availableBytesCount,
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                bufferFull => bufferFull,
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                resetFifo => resetFifo,
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                ----------------------------------------
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                data_in => data_in,
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                ready_to_write => ready_to_write,
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                strobe_write => strobe_write,
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                ----------------------------------------
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                data_out => data_out,
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                ready_to_read => ready_to_read,
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                strobe_read => strobe_read
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        );
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        -- Clock process definitions
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        clk_process :process
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        begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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        end process;
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        stim_proc: PROCESS
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        BEGIN
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                reset <= '1';
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                wait for clk_period*4;
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                reset <= '0';
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                wait for clk_period*4;
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                data_in <= "00000010";
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                wait for clk_period;
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                strobe_write <= '1';
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                wait for clk_period;
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                strobe_write <= '0';
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                wait for clk_period*4;
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                data_in <= "00000011";
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                wait for clk_period;
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                strobe_write <= '1';
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                wait for clk_period;
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                strobe_write <= '0';
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                wait for clk_period*4;
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                strobe_read <= '1';
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                wait for clk_period;
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                strobe_read <= '0';
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                wait for clk_period*4;
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                strobe_read <= '1';
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                wait for clk_period;
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                strobe_read <= '0';
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                wait for clk_period*4;
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                data_in <= "00000100";
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                wait for clk_period;
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                strobe_write <= '1';
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                wait for clk_period;
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                strobe_write <= '0';
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                wait for clk_period*4;
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                strobe_read <= '1';
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                wait for clk_period;
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                strobe_read <= '0';
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--              for i in 0 to 2**11-1 loop
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--                      data_in <= conv_std_logic_vector(i, 8);
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--                      wait for clk_period;
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--                      strobe_write <= '1';
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--                      wait until ready_to_write = '0';
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--                      strobe_write <= '0';
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--                      if i < 2**11-1 then
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--                              wait until ready_to_write = '1';
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--                      end if;
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--              end loop;
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--
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--              wait for clk_period;
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--
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--              strobe_read <= '1';
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--              wait for clk_period;
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--              strobe_read <= '0';
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--
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--              wait for clk_period*3;
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--
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--              for i in 0 to 1 loop
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--                      data_in <= conv_std_logic_vector(i, 8);
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--                      wait for clk_period;
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--                      strobe_write <= '1';
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--                      wait until ready_to_write = '0';
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--                      strobe_write <= '0';
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--                      wait until ready_to_write = '1';
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--              end loop;
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                wait; -- will wait forever
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        END PROCESS;
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END;

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