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[/] [gpib_controller/] [trunk/] [vhdl/] [test/] [RegsGpibFasade_communication_test.vhd] - Blame information for rev 3

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--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:22:23 02/04/2012
-- Design Name:   
-- Module Name:   /home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/test/RegsGpibFasade_test.vhd
-- Project Name:  proto1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RegsGpibFasade
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
use work.wrapperComponents.ALL;
 
ENTITY RegsGpibFasade_communication_test IS
END RegsGpibFasade_communication_test;
 
ARCHITECTURE behavior OF RegsGpibFasade_communication_test IS
 
        component gpibCableEmulator is port (
                -- interface signals
                DIO_1 : in std_logic_vector (7 downto 0);
                output_valid_1 : in std_logic;
                DIO_2 : in std_logic_vector (7 downto 0);
                output_valid_2 : in std_logic;
                DIO : out std_logic_vector (7 downto 0);
                -- attention
                ATN_1 : in std_logic;
                ATN_2 : in std_logic;
                ATN : out std_logic;
                -- data valid
                DAV_1 : in std_logic;
                DAV_2 : in std_logic;
                DAV : out std_logic;
                -- not ready for data
                NRFD_1 : in std_logic;
                NRFD_2 : in std_logic;
                NRFD : out std_logic;
                -- no data accepted
                NDAC_1 : in std_logic;
                NDAC_2 : in std_logic;
                NDAC : out std_logic;
                -- end or identify
                EOI_1 : in std_logic;
                EOI_2 : in std_logic;
                EOI : out std_logic;
                -- service request
                SRQ_1 : in std_logic;
                SRQ_2 : in std_logic;
                SRQ : out std_logic;
                -- interface clear
                IFC_1 : in std_logic;
                IFC_2 : in std_logic;
                IFC : out std_logic;
                -- remote enable
                REN_1 : in std_logic;
                REN_2 : in std_logic;
                REN : out std_logic
        );
        end component;
 
   --Inputs
   signal reset : std_logic := '0';
   signal clk : std_logic := '0';
   signal DI : std_logic_vector(7 downto 0) := (others => '0');
   signal ATN_in : std_logic := '0';
   signal DAV_in : std_logic := '0';
   signal NRFD_in : std_logic := '0';
   signal NDAC_in : std_logic := '0';
   signal EOI_in : std_logic := '0';
   signal SRQ_in : std_logic := '0';
   signal IFC_in : std_logic := '0';
   signal REN_in : std_logic := '0';
   signal data_in : std_logic_vector(15 downto 0) := (others => '0');
   signal reg_addr : std_logic_vector(14 downto 0) := (others => '0');
   signal strobe_read : std_logic := '0';
   signal strobe_write : std_logic := '0';
 
        --Outputs
   signal DO : std_logic_vector(7 downto 0);
   signal output_valid : std_logic;
   signal ATN_out : std_logic;
   signal DAV_out : std_logic;
   signal NRFD_out : std_logic;
   signal NDAC_out : std_logic;
   signal EOI_out : std_logic;
   signal SRQ_out : std_logic;
   signal IFC_out : std_logic;
   signal REN_out : std_logic;
   signal data_out : std_logic_vector(15 downto 0);
   signal interrupt_line : std_logic;
   signal debug1 : std_logic;
 
   --Inputs
   signal data_in_1 : std_logic_vector(15 downto 0) := (others => '0');
   signal reg_addr_1 : std_logic_vector(14 downto 0) := (others => '0');
   signal strobe_read_1 : std_logic := '0';
   signal strobe_write_1 : std_logic := '0';
 
        --Outputs
   signal DO_1 : std_logic_vector(7 downto 0);
   signal output_valid_1 : std_logic;
   signal ATN_out_1 : std_logic;
   signal DAV_out_1 : std_logic;
   signal NRFD_out_1 : std_logic;
   signal NDAC_out_1 : std_logic;
   signal EOI_out_1 : std_logic;
   signal SRQ_out_1 : std_logic;
   signal IFC_out_1 : std_logic;
   signal REN_out_1 : std_logic;
   signal data_out_1 : std_logic_vector(15 downto 0);
   signal interrupt_line_1 : std_logic;
 
 
        -- Clock period definitions
        constant clk_period : time := 10 ns;
 
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
        uut: RegsGpibFasade PORT MAP (
                reset => reset,
                clk => clk,
                DI => DI,
                DO => DO,
                output_valid => output_valid,
                ATN_in => ATN_in,
                ATN_out => ATN_out,
                DAV_in => DAV_in,
                DAV_out => DAV_out,
                NRFD_in => NRFD_in,
                NRFD_out => NRFD_out,
                NDAC_in => NDAC_in,
                NDAC_out => NDAC_out,
                EOI_in => EOI_in,
                EOI_out => EOI_out,
                SRQ_in => SRQ_in,
                SRQ_out => SRQ_out,
                IFC_in => IFC_in,
                IFC_out => IFC_out,
                REN_in => REN_in,
                REN_out => REN_out,
                data_in => data_in,
                data_out => data_out,
                reg_addr => reg_addr,
                strobe_read => strobe_read,
                strobe_write => strobe_write,
                interrupt_line => interrupt_line,
                debug1 => debug1
        );
 
        -- Instantiate the Unit Under Test (UUT)
        uut_1: RegsGpibFasade PORT MAP (
                reset => reset,
                clk => clk,
                DI => DI,
                DO => DO_1,
                output_valid => output_valid_1,
                ATN_in => ATN_in,
                ATN_out => ATN_out_1,
                DAV_in => DAV_in,
                DAV_out => DAV_out_1,
                NRFD_in => NRFD_in,
                NRFD_out => NRFD_out_1,
                NDAC_in => NDAC_in,
                NDAC_out => NDAC_out_1,
                EOI_in => EOI_in,
                EOI_out => EOI_out_1,
                SRQ_in => SRQ_in,
                SRQ_out => SRQ_out_1,
                IFC_in => IFC_in,
                IFC_out => IFC_out_1,
                REN_in => REN_in,
                REN_out => REN_out_1,
                data_in => data_in_1,
                data_out => data_out_1,
                reg_addr => reg_addr_1,
                strobe_read => strobe_read_1,
                strobe_write => strobe_write_1,
                interrupt_line => interrupt_line_1,
                debug1 => open
        );
 
        gce: gpibCableEmulator port map (
                -- interface signals
                DIO_1 => DO,
                output_valid_1 => output_valid,
                DIO_2 => DO_1,
                output_valid_2 => output_valid_1,
                DIO => DI,
                -- attention
                ATN_1 => ATN_out,
                ATN_2 => ATN_out_1,
                ATN => ATN_in,
                -- data valid
                DAV_1 => DAV_out,
                DAV_2 => DAV_out_1,
                DAV => DAV_in,
                -- not ready for data
                NRFD_1 => NRFD_out,
                NRFD_2 => NRFD_out_1,
                NRFD => NRFD_in,
                -- no data accepted
                NDAC_1 => NDAC_out,
                NDAC_2 => NDAC_out_1,
                NDAC => NDAC_in,
                -- end or identify
                EOI_1 => EOI_out,
                EOI_2 => EOI_out_1,
                EOI => EOI_in,
                -- service request
                SRQ_1 => SRQ_out,
                SRQ_2 => SRQ_out_1,
                SRQ => SRQ_in,
                -- interface clear
                IFC_1 => IFC_out,
                IFC_2 => IFC_out_1,
                IFC => IFC_in,
                -- remote enable
                REN_1 => REN_out,
                REN_2 => REN_out_1,
                REN => REN_in
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
        stim_proc: process begin
 
                -- hold reset state for 10 clock cycles
                reset <= '1';
                wait for clk_period*10;
                reset <= '0';
                wait for clk_period*10;
 
                -- set address of GPIB1
                reg_addr_1 <= "000000000000001";
                data_in_1 <= X"0002";
                wait for clk_period*2;
                strobe_write_1 <= '1';
                wait for clk_period*2;
                strobe_write_1 <= '0';
                wait for clk_period*2;
 
                -- set rsc
                reg_addr <= "000000000000111";
                data_in <= X"0040";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*20;
 
                -- set sic
                reg_addr <= "000000000000111";
                data_in <= X"00c0";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*20;
 
                -- reset sic
                reg_addr <= "000000000000111";
                data_in <= X"0040";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait until IFC_in = '0';
 
                -- address GPIB1 to listen
                reg_addr <= "000000000001101";
                data_in <= X"0022";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*5;
 
                -- address GPIB0 to talk
                reg_addr <= "000000000001101";
                data_in <= X"0041";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*5;
 
                -- go to standby
                reg_addr <= "000000000000111";
                data_in <= X"0240";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait until ATN_in = '0';
                reg_addr <= "000000000000111";
                data_in <= X"0040";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*5;
 
                -- set eof
                reg_addr <= "000000000001010";
                data_in <= X"0006";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*5;
 
                -- writes data to GPIB1
                reg_addr <= "000000000001101";
                data_in <= X"0007";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*15;
 
                -- take control
                reg_addr <= "000000000000111";
                data_in <= X"0840";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*150;
 
                -- reset buffer
                reg_addr <= "000000000001010";
                data_in <= X"000a";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*10;
 
                -- address GPIB0 to listen
                reg_addr <= "000000000001101";
                data_in <= X"0021";
                wait for clk_period*2;
                strobe_write <= '1';
                wait for clk_period*2;
                strobe_write <= '0';
                wait for clk_period*5;
 
                wait;
        end process;
 
END;

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [test/] [RegsGpibFasade_communication_test.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 16:22:23 02/04/2012`
6			`-- Design Name:`
7			`-- Module Name: /home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/test/RegsGpibFasade_test.vhd`
8			`-- Project Name: proto1`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- VHDL Test Bench Created by ISE for module: RegsGpibFasade`
14			`--`
15			`-- Dependencies:`
16			`--`
17			`-- Revision:`
18			`-- Revision 0.01 - File Created`
19			`-- Additional Comments:`
20			`--`
21			`-- Notes:`
22			`-- This testbench has been automatically generated using types std_logic and`
23			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
24			`-- that these types always be used for the top-level I/O of a design in order`
25			`-- to guarantee that the testbench will bind correctly to the post-implementation`
26			`-- simulation model.`
27			`--------------------------------------------------------------------------------`
28			`LIBRARY ieee;`
29			`USE ieee.std_logic_1164.ALL;`
30
31			`-- Uncomment the following library declaration if using`
32			`-- arithmetic functions with Signed or Unsigned values`
33			`--USE ieee.numeric_std.ALL;`
34
35			`use work.wrapperComponents.ALL;`
36
37			`ENTITY RegsGpibFasade_communication_test IS`
38			`END RegsGpibFasade_communication_test;`
39
40			`ARCHITECTURE behavior OF RegsGpibFasade_communication_test IS`
41
42			`component gpibCableEmulator is port (`
43			`-- interface signals`
44			`DIO_1 : in std_logic_vector (7 downto 0);`
45			`output_valid_1 : in std_logic;`
46			`DIO_2 : in std_logic_vector (7 downto 0);`
47			`output_valid_2 : in std_logic;`
48			`DIO : out std_logic_vector (7 downto 0);`
49			`-- attention`
50			`ATN_1 : in std_logic;`
51			`ATN_2 : in std_logic;`
52			`ATN : out std_logic;`
53			`-- data valid`
54			`DAV_1 : in std_logic;`
55			`DAV_2 : in std_logic;`
56			`DAV : out std_logic;`
57			`-- not ready for data`
58			`NRFD_1 : in std_logic;`
59			`NRFD_2 : in std_logic;`
60			`NRFD : out std_logic;`
61			`-- no data accepted`
62			`NDAC_1 : in std_logic;`
63			`NDAC_2 : in std_logic;`
64			`NDAC : out std_logic;`
65			`-- end or identify`
66			`EOI_1 : in std_logic;`
67			`EOI_2 : in std_logic;`
68			`EOI : out std_logic;`
69			`-- service request`
70			`SRQ_1 : in std_logic;`
71			`SRQ_2 : in std_logic;`
72			`SRQ : out std_logic;`
73			`-- interface clear`
74			`IFC_1 : in std_logic;`
75			`IFC_2 : in std_logic;`
76			`IFC : out std_logic;`
77			`-- remote enable`
78			`REN_1 : in std_logic;`
79			`REN_2 : in std_logic;`
80			`REN : out std_logic`
81			`);`
82			`end component;`
83
84			`--Inputs`
85			`signal reset : std_logic := '0';`
86			`signal clk : std_logic := '0';`
87			`signal DI : std_logic_vector(7 downto 0) := (others => '0');`
88			`signal ATN_in : std_logic := '0';`
89			`signal DAV_in : std_logic := '0';`
90			`signal NRFD_in : std_logic := '0';`
91			`signal NDAC_in : std_logic := '0';`
92			`signal EOI_in : std_logic := '0';`
93			`signal SRQ_in : std_logic := '0';`
94			`signal IFC_in : std_logic := '0';`
95			`signal REN_in : std_logic := '0';`
96			`signal data_in : std_logic_vector(15 downto 0) := (others => '0');`
97			`signal reg_addr : std_logic_vector(14 downto 0) := (others => '0');`
98			`signal strobe_read : std_logic := '0';`
99			`signal strobe_write : std_logic := '0';`
100
101			`--Outputs`
102			`signal DO : std_logic_vector(7 downto 0);`
103			`signal output_valid : std_logic;`
104			`signal ATN_out : std_logic;`
105			`signal DAV_out : std_logic;`
106			`signal NRFD_out : std_logic;`
107			`signal NDAC_out : std_logic;`
108			`signal EOI_out : std_logic;`
109			`signal SRQ_out : std_logic;`
110			`signal IFC_out : std_logic;`
111			`signal REN_out : std_logic;`
112			`signal data_out : std_logic_vector(15 downto 0);`
113			`signal interrupt_line : std_logic;`
114			`signal debug1 : std_logic;`
115
116			`--Inputs`
117			`signal data_in_1 : std_logic_vector(15 downto 0) := (others => '0');`
118			`signal reg_addr_1 : std_logic_vector(14 downto 0) := (others => '0');`
119			`signal strobe_read_1 : std_logic := '0';`
120			`signal strobe_write_1 : std_logic := '0';`
121
122			`--Outputs`
123			`signal DO_1 : std_logic_vector(7 downto 0);`
124			`signal output_valid_1 : std_logic;`
125			`signal ATN_out_1 : std_logic;`
126			`signal DAV_out_1 : std_logic;`
127			`signal NRFD_out_1 : std_logic;`
128			`signal NDAC_out_1 : std_logic;`
129			`signal EOI_out_1 : std_logic;`
130			`signal SRQ_out_1 : std_logic;`
131			`signal IFC_out_1 : std_logic;`
132			`signal REN_out_1 : std_logic;`
133			`signal data_out_1 : std_logic_vector(15 downto 0);`
134			`signal interrupt_line_1 : std_logic;`
135
136
137			`-- Clock period definitions`
138			`constant clk_period : time := 10 ns;`
139
140
141			`BEGIN`
142
143			`-- Instantiate the Unit Under Test (UUT)`
144			`uut: RegsGpibFasade PORT MAP (`
145			`reset => reset,`
146			`clk => clk,`
147			`DI => DI,`
148			`DO => DO,`
149			`output_valid => output_valid,`
150			`ATN_in => ATN_in,`
151			`ATN_out => ATN_out,`
152			`DAV_in => DAV_in,`
153			`DAV_out => DAV_out,`
154			`NRFD_in => NRFD_in,`
155			`NRFD_out => NRFD_out,`
156			`NDAC_in => NDAC_in,`
157			`NDAC_out => NDAC_out,`
158			`EOI_in => EOI_in,`
159			`EOI_out => EOI_out,`
160			`SRQ_in => SRQ_in,`
161			`SRQ_out => SRQ_out,`
162			`IFC_in => IFC_in,`
163			`IFC_out => IFC_out,`
164			`REN_in => REN_in,`
165			`REN_out => REN_out,`
166			`data_in => data_in,`
167			`data_out => data_out,`
168			`reg_addr => reg_addr,`
169			`strobe_read => strobe_read,`
170			`strobe_write => strobe_write,`
171			`interrupt_line => interrupt_line,`
172			`debug1 => debug1`
173			`);`
174
175			`-- Instantiate the Unit Under Test (UUT)`
176			`uut_1: RegsGpibFasade PORT MAP (`
177			`reset => reset,`
178			`clk => clk,`
179			`DI => DI,`
180			`DO => DO_1,`
181			`output_valid => output_valid_1,`
182			`ATN_in => ATN_in,`
183			`ATN_out => ATN_out_1,`
184			`DAV_in => DAV_in,`
185			`DAV_out => DAV_out_1,`
186			`NRFD_in => NRFD_in,`
187			`NRFD_out => NRFD_out_1,`
188			`NDAC_in => NDAC_in,`
189			`NDAC_out => NDAC_out_1,`
190			`EOI_in => EOI_in,`
191			`EOI_out => EOI_out_1,`
192			`SRQ_in => SRQ_in,`
193			`SRQ_out => SRQ_out_1,`
194			`IFC_in => IFC_in,`
195			`IFC_out => IFC_out_1,`
196			`REN_in => REN_in,`
197			`REN_out => REN_out_1,`
198			`data_in => data_in_1,`
199			`data_out => data_out_1,`
200			`reg_addr => reg_addr_1,`
201			`strobe_read => strobe_read_1,`
202			`strobe_write => strobe_write_1,`
203			`interrupt_line => interrupt_line_1,`
204			`debug1 => open`
205			`);`
206
207			`gce: gpibCableEmulator port map (`
208			`-- interface signals`
209			`DIO_1 => DO,`
210			`output_valid_1 => output_valid,`
211			`DIO_2 => DO_1,`
212			`output_valid_2 => output_valid_1,`
213			`DIO => DI,`
214			`-- attention`
215			`ATN_1 => ATN_out,`
216			`ATN_2 => ATN_out_1,`
217			`ATN => ATN_in,`
218			`-- data valid`
219			`DAV_1 => DAV_out,`
220			`DAV_2 => DAV_out_1,`
221			`DAV => DAV_in,`
222			`-- not ready for data`
223			`NRFD_1 => NRFD_out,`
224			`NRFD_2 => NRFD_out_1,`
225			`NRFD => NRFD_in,`
226			`-- no data accepted`
227			`NDAC_1 => NDAC_out,`
228			`NDAC_2 => NDAC_out_1,`
229			`NDAC => NDAC_in,`
230			`-- end or identify`
231			`EOI_1 => EOI_out,`
232			`EOI_2 => EOI_out_1,`
233			`EOI => EOI_in,`
234			`-- service request`
235			`SRQ_1 => SRQ_out,`
236			`SRQ_2 => SRQ_out_1,`
237			`SRQ => SRQ_in,`
238			`-- interface clear`
239			`IFC_1 => IFC_out,`
240			`IFC_2 => IFC_out_1,`
241			`IFC => IFC_in,`
242			`-- remote enable`
243			`REN_1 => REN_out,`
244			`REN_2 => REN_out_1,`
245			`REN => REN_in`
246			`);`
247
248			`-- Clock process definitions`
249			`clk_process :process`
250			`begin`
251			`clk <= '0';`
252			`wait for clk_period/2;`
253			`clk <= '1';`
254			`wait for clk_period/2;`
255			`end process;`
256
257
258			`-- Stimulus process`
259			`stim_proc: process begin`
260
261			`-- hold reset state for 10 clock cycles`
262			`reset <= '1';`
263			`wait for clk_period*10;`
264			`reset <= '0';`
265			`wait for clk_period*10;`
266
267			`-- set address of GPIB1`
268			`reg_addr_1 <= "000000000000001";`
269			`data_in_1 <= X"0002";`
270			`wait for clk_period*2;`
271			`strobe_write_1 <= '1';`
272			`wait for clk_period*2;`
273			`strobe_write_1 <= '0';`
274			`wait for clk_period*2;`
275
276			`-- set rsc`
277			`reg_addr <= "000000000000111";`
278			`data_in <= X"0040";`
279			`wait for clk_period*2;`
280			`strobe_write <= '1';`
281			`wait for clk_period*2;`
282			`strobe_write <= '0';`
283			`wait for clk_period*20;`
284
285			`-- set sic`
286			`reg_addr <= "000000000000111";`
287			`data_in <= X"00c0";`
288			`wait for clk_period*2;`
289			`strobe_write <= '1';`
290			`wait for clk_period*2;`
291			`strobe_write <= '0';`
292			`wait for clk_period*20;`
293
294			`-- reset sic`
295			`reg_addr <= "000000000000111";`
296			`data_in <= X"0040";`
297			`wait for clk_period*2;`
298			`strobe_write <= '1';`
299			`wait for clk_period*2;`
300			`strobe_write <= '0';`
301			`wait until IFC_in = '0';`
302
303			`-- address GPIB1 to listen`
304			`reg_addr <= "000000000001101";`
305			`data_in <= X"0022";`
306			`wait for clk_period*2;`
307			`strobe_write <= '1';`
308			`wait for clk_period*2;`
309			`strobe_write <= '0';`
310			`wait for clk_period*5;`
311
312			`-- address GPIB0 to talk`
313			`reg_addr <= "000000000001101";`
314			`data_in <= X"0041";`
315			`wait for clk_period*2;`
316			`strobe_write <= '1';`
317			`wait for clk_period*2;`
318			`strobe_write <= '0';`
319			`wait for clk_period*5;`
320
321			`-- go to standby`
322			`reg_addr <= "000000000000111";`
323			`data_in <= X"0240";`
324			`wait for clk_period*2;`
325			`strobe_write <= '1';`
326			`wait for clk_period*2;`
327			`strobe_write <= '0';`
328			`wait until ATN_in = '0';`
329			`reg_addr <= "000000000000111";`
330			`data_in <= X"0040";`
331			`wait for clk_period*2;`
332			`strobe_write <= '1';`
333			`wait for clk_period*2;`
334			`strobe_write <= '0';`
335			`wait for clk_period*5;`
336
337			`-- set eof`
338			`reg_addr <= "000000000001010";`
339			`data_in <= X"0006";`
340			`wait for clk_period*2;`
341			`strobe_write <= '1';`
342			`wait for clk_period*2;`
343			`strobe_write <= '0';`
344			`wait for clk_period*5;`
345
346			`-- writes data to GPIB1`
347			`reg_addr <= "000000000001101";`
348			`data_in <= X"0007";`
349			`wait for clk_period*2;`
350			`strobe_write <= '1';`
351			`wait for clk_period*2;`
352			`strobe_write <= '0';`
353			`wait for clk_period*15;`
354
355			`-- take control`
356			`reg_addr <= "000000000000111";`
357			`data_in <= X"0840";`
358			`wait for clk_period*2;`
359			`strobe_write <= '1';`
360			`wait for clk_period*2;`
361			`strobe_write <= '0';`
362			`wait for clk_period*150;`
363
364			`-- reset buffer`
365			`reg_addr <= "000000000001010";`
366			`data_in <= X"000a";`
367			`wait for clk_period*2;`
368			`strobe_write <= '1';`
369			`wait for clk_period*2;`
370			`strobe_write <= '0';`
371			`wait for clk_period*10;`
372
373			`-- address GPIB0 to listen`
374			`reg_addr <= "000000000001101";`
375			`data_in <= X"0021";`
376			`wait for clk_period*2;`
377			`strobe_write <= '1';`
378			`wait for clk_period*2;`
379			`strobe_write <= '0';`
380			`wait for clk_period*5;`
381
382			`wait;`
383			`end process;`
384
385			`END;`