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[/] [gpib_controller/] [trunk/] [vhdl/] [test/] [gpib_TE_LE_Test.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2 13 Andrewski
--This file is part of fpga_gpib_controller.
3 3 Andrewski
--
4 13 Andrewski
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation, either version 3 of the License, or
7
-- (at your option) any later version.
8
--
9
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
 
14
-- You should have received a copy of the GNU General Public License
15
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
16
--------------------------------------------------------------------------------
17
-- Author: Andrzej Paluch
18
--
19 3 Andrewski
-- Create Date:   23:21:05 10/21/2011
20
-- Design Name:   
21
-- Module Name:   /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
22
-- Project Name:  usbToHpib
23
-- Target Device:  
24
-- Tool versions:  
25
-- Description:   
26
-- 
27
-- VHDL Test Bench Created by ISE for module: gpibInterface
28
-- 
29
-- Dependencies:
30
-- 
31
-- Revision:
32
-- Revision 0.01 - File Created
33
-- Additional Comments:
34
--
35
-- Notes: 
36
-- This testbench has been automatically generated using types std_logic and
37
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
38
-- that these types always be used for the top-level I/O of a design in order
39
-- to guarantee that the testbench will bind correctly to the post-implementation 
40
-- simulation model.
41
--------------------------------------------------------------------------------
42
LIBRARY ieee;
43
USE ieee.std_logic_1164.ALL;
44
USE ieee.std_logic_unsigned.all;
45
USE ieee.numeric_std.ALL;
46
 
47
use work.gpibComponents.all;
48
use work.helperComponents.all;
49
 
50
 
51
ENTITY gpib_TE_LE_Test IS
52
END gpib_TE_LE_Test;
53
 
54
ARCHITECTURE behavior OF gpib_TE_LE_Test IS
55
 
56
        -- Component Declaration for the Unit Under Test (UUT)
57
 
58
        component gpibCableEmulator is port (
59
                -- interface signals
60
                DIO_1 : in std_logic_vector (7 downto 0);
61
                output_valid_1 : in std_logic;
62
                DIO_2 : in std_logic_vector (7 downto 0);
63
                output_valid_2 : in std_logic;
64
                DIO : out std_logic_vector (7 downto 0);
65
                -- attention
66
                ATN_1 : in std_logic;
67
                ATN_2 : in std_logic;
68
                ATN : out std_logic;
69
                -- data valid
70
                DAV_1 : in std_logic;
71
                DAV_2 : in std_logic;
72
                DAV : out std_logic;
73
                -- not ready for data
74
                NRFD_1 : in std_logic;
75
                NRFD_2 : in std_logic;
76
                NRFD : out std_logic;
77
                -- no data accepted
78
                NDAC_1 : in std_logic;
79
                NDAC_2 : in std_logic;
80
                NDAC : out std_logic;
81
                -- end or identify
82
                EOI_1 : in std_logic;
83
                EOI_2 : in std_logic;
84
                EOI : out std_logic;
85
                -- service request
86
                SRQ_1 : in std_logic;
87
                SRQ_2 : in std_logic;
88
                SRQ : out std_logic;
89
                -- interface clear
90
                IFC_1 : in std_logic;
91
                IFC_2 : in std_logic;
92
                IFC : out std_logic;
93
                -- remote enable
94
                REN_1 : in std_logic;
95
                REN_2 : in std_logic;
96
                REN : out std_logic
97
        );
98
        end component;
99
 
100
        -- inputs common
101
        signal clk : std_logic := '0';
102
        signal reset : std_logic := '0';
103
        signal T1 : std_logic_vector(7 downto 0) := "00000100";
104
 
105
        -- inputs 1
106
        signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
107
        signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
108
        signal rdy_1 : std_logic := '0';
109
        signal nba_1 : std_logic := '0';
110
        signal ltn_1 : std_logic := '0';
111
        signal lun_1 : std_logic := '0';
112
        signal lon_1 : std_logic := '0';
113
        signal ton_1 : std_logic := '0';
114
        signal endOf_1 : std_logic := '0';
115
        signal gts_1 : std_logic := '0';
116
        signal rpp_1 : std_logic := '0';
117
        signal tcs_1 : std_logic := '0';
118
        signal tca_1 : std_logic := '0';
119
        signal sic_1 : std_logic := '0';
120
        signal rsc_1 : std_logic := '0';
121
        signal sre_1 : std_logic := '0';
122
        signal rtl_1 : std_logic := '0';
123
        signal rsv_1 : std_logic := '0';
124
        signal ist_1 : std_logic := '0';
125
        signal lpe_1 : std_logic := '0';
126
 
127
        -- inputs 2
128
        signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
129
        signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
130
        signal rdy_2 : std_logic := '0';
131
        signal nba_2 : std_logic := '0';
132
        signal ltn_2 : std_logic := '0';
133
        signal lun_2 : std_logic := '0';
134
        signal lon_2 : std_logic := '0';
135
        signal ton_2 : std_logic := '0';
136
        signal endOf_2 : std_logic := '0';
137
        signal gts_2 : std_logic := '0';
138
        signal rpp_2 : std_logic := '0';
139
        signal tcs_2 : std_logic := '0';
140
        signal tca_2 : std_logic := '0';
141
        signal sic_2 : std_logic := '0';
142
        signal rsc_2 : std_logic := '0';
143
        signal sre_2 : std_logic := '0';
144
        signal rtl_2 : std_logic := '0';
145
        signal rsv_2 : std_logic := '0';
146
        signal ist_2 : std_logic := '0';
147
        signal lpe_2 : std_logic := '0';
148
 
149
        -- outputs 1
150
        signal dvd_1 : std_logic;
151
        signal wnc_1 : std_logic;
152
        signal tac_1 : std_logic;
153
        signal lac_1 : std_logic;
154
        signal cwrc_1 : std_logic;
155
        signal cwrd_1 : std_logic;
156
        signal clr_1 : std_logic;
157
        signal trg_1 : std_logic;
158
        signal atl_1 : std_logic;
159
        signal att_1 : std_logic;
160
        signal mla_1 : std_logic;
161
        signal lsb_1 : std_logic;
162
        signal spa_1 : std_logic;
163
        signal ppr_1 : std_logic;
164
        signal sreq_1 : std_logic;
165
        signal isLocal_1 : std_logic;
166
        signal currentSecAddr_1 : std_logic_vector (4 downto 0);
167
 
168
        -- outputs 2
169
        signal dvd_2 : std_logic;
170
        signal wnc_2 : std_logic;
171
        signal tac_2 : std_logic;
172
        signal lac_2 : std_logic;
173
        signal cwrc_2 : std_logic;
174
        signal cwrd_2 : std_logic;
175
        signal clr_2 : std_logic;
176
        signal trg_2 : std_logic;
177
        signal atl_2 : std_logic;
178
        signal att_2 : std_logic;
179
        signal mla_2 : std_logic;
180
        signal lsb_2 : std_logic;
181
        signal spa_2 : std_logic;
182
        signal ppr_2 : std_logic;
183
        signal sreq_2 : std_logic;
184
        signal isLocal_2 : std_logic;
185
        signal currentSecAddr_2 : std_logic_vector (4 downto 0);
186
 
187
        -- common
188
        signal DO : std_logic_vector (7 downto 0);
189
        signal DI_1 : std_logic_vector (7 downto 0);
190
        signal output_valid_1 : std_logic;
191
        signal DI_2 : std_logic_vector (7 downto 0);
192
        signal output_valid_2 : std_logic;
193
        signal ATN_1, ATN_2, ATN : std_logic;
194
        signal DAV_1, DAV_2, DAV : std_logic;
195
        signal NRFD_1, NRFD_2, NRFD : std_logic;
196
        signal NDAC_1, NDAC_2, NDAC : std_logic;
197
        signal EOI_1, EOI_2, EOI : std_logic;
198
        signal SRQ_1, SRQ_2, SRQ : std_logic;
199
        signal IFC_1, IFC_2, IFC : std_logic;
200
        signal REN_1, REN_2, REN : std_logic;
201
 
202
        -- gpib reader
203
        signal buf_interrupt : std_logic;
204
        signal data_available : std_logic;
205
        signal last_byte_addr : std_logic_vector (3 downto 0);
206
        signal end_of_stream : std_logic;
207
        signal byte_addr : std_logic_vector (3 downto 0);
208
        signal data_out : std_logic_vector (7 downto 0);
209
        signal reset_buffer : std_logic := '0';
210
        signal dataSecAddr : std_logic_vector (4 downto 0);
211
 
212
        -- gpib writer
213
        signal w_last_byte_addr : std_logic_vector (3 downto 0)
214
                := (others => '0');
215
        signal w_end_of_stream : std_logic := '0';
216
        signal w_data_available : std_logic := '0';
217
        signal w_buf_interrupt : std_logic;
218
        signal w_data_in : std_logic_vector (7 downto 0);
219
        signal w_byte_addr : std_logic_vector (3 downto 0);
220
        signal w_reset_buffer : std_logic := '0';
221
        signal w_dataSecAddr : std_logic_vector (4 downto 0);
222
        type WR_BUF_TYPE is
223
                array (0 to 15) of std_logic_vector (7 downto 0);
224
        signal w_write_buffer : WR_BUF_TYPE;
225
 
226
        -- Clock period definitions
227
        constant clk_period : time := 2ps;
228
 
229
BEGIN
230
 
231
        -- Instantiate the Unit Under Test (UUT)
232
        gpib1: gpibInterface PORT MAP (
233
                clk => clk,
234
                reset => reset,
235
                isLE => '1',
236
                isTE => '1',
237
                lpeUsed => '0',
238
                fixedPpLine => "000",
239
                eosUsed => '0',
240
                eosMark => "00000000",
241
                myListAddr => "00001",
242
                myTalkAddr => "00001",
243
                secAddrMask => "00000000000000000000000000000110",
244
                data => data_1,
245
                status_byte => status_byte_1,
246
                T1 => T1,
247
                rdy => rdy_1,
248
                nba => nba_1,
249
                ltn => ltn_1,
250
                lun => lun_1,
251
                lon => lon_1,
252
                ton => ton_1,
253
                endOf => endOf_1,
254
                gts => gts_1,
255
                rpp => rpp_1,
256
                tcs => tcs_1,
257
                tca => tca_1,
258
                sic => sic_1,
259
                rsc => rsc_1,
260
                sre => sre_1,
261
                rtl => rtl_1,
262
                rsv => rsv_1,
263
                ist => ist_1,
264
                lpe => lpe_1,
265
                dvd => dvd_1,
266
                wnc => wnc_1,
267
                tac => tac_1,
268
                lac => lac_1,
269
                cwrc => cwrc_1,
270
                cwrd => cwrd_1,
271
                clr => clr_1,
272
                trg => trg_1,
273
                atl => atl_1,
274
                att => att_1,
275
                mla => mla_1,
276
                lsb => lsb_1,
277
                spa => spa_1,
278
                ppr => ppr_1,
279
                sreq => sreq_1,
280
                isLocal => isLocal_1,
281
                currentSecAddr => currentSecAddr_1,
282
                DI => DO,
283
                DO => DI_1,
284
                output_valid => output_valid_1,
285
                ATN_in => ATN,
286
                ATN_out => ATN_1,
287
                DAV_in => DAV,
288
                DAV_out => DAV_1,
289
                NRFD_in => NRFD,
290
                NRFD_out => NRFD_1,
291
                NDAC_in => NDAC,
292
                NDAC_out => NDAC_1,
293
                EOI_in => EOI,
294
                EOI_out => EOI_1,
295
                SRQ_in => SRQ,
296
                SRQ_out => SRQ_1,
297
                IFC_in => IFC,
298
                IFC_out => IFC_1,
299
                REN_in => REN,
300
                REN_out => REN_1
301
                );
302
 
303
        -- Instantiate the Unit Under Test (UUT)
304
        gpib2: gpibInterface PORT MAP (
305
                clk => clk,
306
                reset => reset,
307
                isLE => '1',
308
                isTE => '1',
309
                lpeUsed => '0',
310
                fixedPpLine => "000",
311
                eosUsed => '0',
312
                eosMark => "00000000",
313
                myListAddr => "00010",
314
                myTalkAddr => "00010",
315
                secAddrMask => "00000000000000000000000000000110",
316
                data => data_2,
317
                status_byte => status_byte_2,
318
                T1 => T1,
319
                rdy => rdy_2,
320
                nba => nba_2,
321
                ltn => ltn_2,
322
                lun => lun_2,
323
                lon => lon_2,
324
                ton => ton_2,
325
                endOf => endOf_2,
326
                gts => gts_2,
327
                rpp => rpp_2,
328
                tcs => tcs_2,
329
                tca => tca_2,
330
                sic => sic_2,
331
                rsc => rsc_2,
332
                sre => sre_2,
333
                rtl => rtl_2,
334
                rsv => rsv_2,
335
                ist => ist_2,
336
                lpe => lpe_2,
337
                dvd => dvd_2,
338
                wnc => wnc_2,
339
                tac => tac_2,
340
                lac => lac_2,
341
                cwrc => cwrc_2,
342
                cwrd => cwrd_2,
343
                clr => clr_2,
344
                trg => trg_2,
345
                atl => atl_2,
346
                att => att_2,
347
                mla => mla_2,
348
                lsb => lsb_2,
349
                spa => spa_2,
350
                ppr => ppr_2,
351
                sreq => sreq_2,
352
                isLocal => isLocal_2,
353
                currentSecAddr => currentSecAddr_2,
354
                DI => DO,
355
                DO => DI_2,
356
                output_valid => output_valid_2,
357
                ATN_in => ATN,
358
                ATN_out => ATN_2,
359
                DAV_in => DAV,
360
                DAV_out => DAV_2,
361
                NRFD_in => NRFD,
362
                NRFD_out => NRFD_2,
363
                NDAC_in => NDAC,
364
                NDAC_out => NDAC_2,
365
                EOI_in => EOI,
366
                EOI_out => EOI_2,
367
                SRQ_in => SRQ,
368
                SRQ_out => SRQ_2,
369
                IFC_in => IFC,
370
                IFC_out => IFC_2,
371
                REN_in => REN,
372
                REN_out => REN_2
373
                );
374
 
375
        ce: gpibCableEmulator port map (
376
                -- interface signals
377
                DIO_1 => DI_1,
378
                output_valid_1 => output_valid_1,
379
                DIO_2 => DI_2,
380
                output_valid_2 => output_valid_2,
381
                DIO => DO,
382
                -- attention
383
                ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
384
                DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
385
                NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
386
                NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
387
                EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
388
                SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
389
                IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
390
                REN_1 => REN_1, REN_2 => REN_2, REN => REN
391
        );
392
 
393
        gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
394
                clk => clk, reset => reset,
395
                ------------------------------------------------------------------------
396
                ------ GPIB interface --------------------------------------------------
397
                ------------------------------------------------------------------------
398
                data_in => DO, dvd => dvd_2, lac => lac_2, lsb => lsb_2, rdy => rdy_2,
399
                ------------------------------------------------------------------------
400
                ------ external interface ----------------------------------------------
401
                ------------------------------------------------------------------------
402
                isLE => '1', secAddr => currentSecAddr_1, dataSecAddr => dataSecAddr,
403
                buf_interrupt => buf_interrupt, data_available => data_available,
404
                last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
405
                byte_addr => byte_addr, data_out => data_out,
406
                reset_buffer => reset_buffer
407
        );
408
 
409
        w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
410
 
411
        gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
412
                        clk => clk, reset => reset,
413
                        ------------------------------------------------------------------------
414
                        ------ GPIB interface --------------------------------------------------
415
                        ------------------------------------------------------------------------
416
                        data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
417
                        endOf => endOf_1, tac => tac_1, cwrc => cwrc_1,
418
                        ------------------------------------------------------------------------
419
                        ------ external interface ----------------------------------------------
420
                        ------------------------------------------------------------------------
421
                        isTE => '1', secAddr => currentSecAddr_1, dataSecAddr => w_dataSecAddr,
422
                        last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
423
                        data_available => w_data_available, buf_interrupt => w_buf_interrupt,
424
                        data_in => w_data_in, byte_addr => w_byte_addr,
425
                        reset_buffer => w_reset_buffer
426
                );
427
 
428
        -- Clock process definitions
429
        clk_process :process
430
        begin
431
                clk <= '0';
432
                wait for clk_period/2;
433
                clk <= '1';
434
                wait for clk_period/2;
435
        end process;
436
 
437
 
438
        -- Stimulus process
439
        stim_proc: process
440
        begin
441
                -- hold reset state for 10 clock periods.
442
                reset <= '1';
443
                wait for clk_period*10;
444
                reset <= '0';
445
                wait for clk_period*10;
446
 
447
                -- requests system control
448
                rsc_1 <= '1';
449
 
450
                -- interface clear
451
                sic_1 <= '1';
452
                wait until IFC_1 = '1';
453
                sic_1 <= '0';
454
                wait until IFC_1 = '0';
455
 
456
                -- gpib2 to listen
457
                w_write_buffer(0) <= "00100010";
458
                w_write_buffer(1) <= "01100010";
459
                -- gpib1 to talk
460
                w_write_buffer(2) <= "01000001";
461
                w_write_buffer(3) <= "01100010";
462
                w_last_byte_addr <= "0011";
463
                w_data_available <= '1';
464
 
465
                wait until w_buf_interrupt='1';
466
 
467
                gts_1 <= '1';
468
                wait until ATN='0';
469
 
470
                w_reset_buffer <= '1';
471
                wait for clk_period*2;
472
                w_reset_buffer <= '0';
473
 
474
                w_dataSecAddr <= "00010";
475
 
476
                wait for clk_period*1;
477
 
478
                w_write_buffer(0) <= "10101010";
479
                w_write_buffer(1) <= "01010101";
480
                w_write_buffer(2) <= "11111111";
481
                w_last_byte_addr <= "0010";
482
                w_end_of_stream <= '1';
483
                w_data_available <= '1';
484
 
485
                wait until buf_interrupt='1';
486
 
487
                byte_addr <= "0000";
488
                wait for clk_period*1;
489
                assert data_out = "10101010";
490
 
491
                byte_addr <= "0001";
492
                wait for clk_period*1;
493
                assert data_out = "01010101";
494
 
495
                byte_addr <= "0010";
496
                wait for clk_period*1;
497
                assert data_out = "11111111";
498
 
499
                report "$$$ END OF TEST - TE / LE $$$";
500
 
501
                wait;
502
        end process;
503
 
504
END;

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