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[/] [gpio/] [tags/] [asyst_3/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 65

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1 14 lampret 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  WISHBONE General-Purpose I/O                                ////
4 
////                                                              ////
5 
////  This file is part of the GPIO project                       ////
6 
////  http://www.opencores.org/cores/gpio/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Implementation of GPIO IP core according to                 ////
10 
////  GPIO IP core specification document.                        ////
11 
////                                                              ////
12 
////  To Do:                                                      ////
13 
////   Nothing                                                    ////
14 
////                                                              ////
15 
////  Author(s):                                                  ////
16 
////      - Damjan Lampret, lampret@opencores.org                 ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 56 gorand 
// Revision 1.15  2003/11/10 23:21:22  gorand
49 
// bug fixed. all tests passed.
50 
//
51 36 gorand 
// Revision 1.14  2003/11/06 13:59:07  gorand
52 
// added support for 8-bit access to registers.
53 
//
54 34 gorand 
// Revision 1.13  2002/11/18 22:35:18  lampret
55 
// Bug fix. Interrupts were also asserted when condition was not met.
56 
//
57 31 lampret 
// Revision 1.12  2002/11/11 21:36:28  lampret
58 
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
59 
//
60 29 lampret 
// Revision 1.11  2002/03/13 20:56:28  lampret
61 
// Removed zero padding as per Avi Shamli suggestion.
62 
//
63 26 lampret 
// Revision 1.10  2002/03/13 20:47:57  lampret
64 
// Ports changed per Ran Aviram suggestions.
65 
//
66 25 lampret 
// Revision 1.9  2002/03/09 03:43:27  lampret
67 
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
68 
//
69 24 lampret 
// Revision 1.8  2002/01/14 19:06:28  lampret
70 
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
71 
//
72 23 lampret 
// Revision 1.7  2001/12/25 17:21:21  lampret
73 
// Fixed two typos.
74 
//
75 22 lampret 
// Revision 1.6  2001/12/25 17:12:35  lampret
76 
// Added RGPIO_INTS.
77 
//
78 21 lampret 
// Revision 1.5  2001/12/12 20:35:53  lampret
79 
// Fixing style.
80 
//
81 20 lampret 
// Revision 1.4  2001/12/12 07:12:58  lampret
82 
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
83 
//
84 19 lampret 
// Revision 1.3  2001/11/15 02:24:37  lampret
85 
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
86 
//
87 17 lampret 
// Revision 1.2  2001/10/31 02:26:51  lampret
88 
// Fixed wb_err_o.
89 
//
90 15 lampret 
// Revision 1.1  2001/09/18 18:49:07  lampret
91 
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
92 
//
93 14 lampret 
// Revision 1.1  2001/08/21 21:39:28  lampret
94 
// Changed directory structure, port names and drfines.
95 
//
96 
// Revision 1.2  2001/07/14 20:39:26  lampret
97 
// Better configurability.
98 
//
99 
// Revision 1.1  2001/06/05 07:45:26  lampret
100 
// Added initial RTL and test benches. There are still some issues with these files.
101 
//
102 
//
103 
 
104 
// synopsys translate_off
105 
`include "timescale.v"
106 
// synopsys translate_on
107 
`include "gpio_defines.v"
108 
 
109 
module gpio_top(
110 
        // WISHBONE Interface
111 
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
112 
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
113 
 
114 
        // Auxiliary inputs interface
115 
        aux_i,
116 
 
117 
        // External GPIO Interface
118 25 lampret 
        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o
119 14 lampret 
);
120 
 
121 
parameter dw = 32;
122 
parameter aw = `GPIO_ADDRHH+1;
123 
parameter gw = `GPIO_IOS;
124 
//
125 
// WISHBONE Interface
126 
//
127 
input                   wb_clk_i;       // Clock
128 
input                   wb_rst_i;       // Reset
129 
input                   wb_cyc_i;       // cycle valid input
130 
input   [aw-1:0] wb_adr_i;       // address bus inputs
131 
input   [dw-1:0] wb_dat_i;       // input data bus
132 
input   [3:0]            wb_sel_i;       // byte select inputs
133 
input                   wb_we_i;        // indicates write transfer
134 
input                   wb_stb_i;       // strobe input
135 
output  [dw-1:0] wb_dat_o;       // output data bus
136 
output                  wb_ack_o;       // normal termination
137 
output                  wb_err_o;       // termination w/ error
138 
output                  wb_inta_o;      // Interrupt request output
139 
 
140 
// Auxiliary Inputs Interface
141 
input   [gw-1:0] aux_i;          // Auxiliary inputs
142 
 
143 
//
144 
// External GPIO Interface
145 
//
146 25 lampret 
input   [gw-1:0] ext_pad_i;      // GPIO Inputs
147 
input                   clk_pad_i;      // GPIO Eclk
148 
output  [gw-1:0] ext_pad_o;      // GPIO Outputs
149 
output  [gw-1:0] ext_padoen_o;   // GPIO output drivers enables
150 14 lampret 
 
151 
`ifdef GPIO_IMPLEMENTED
152 
 
153 
//
154 
// GPIO Input Register (or no register)
155 
//
156 
`ifdef GPIO_RGPIO_IN
157 
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
158 
`else
159 
wire    [gw-1:0] rgpio_in;       // No register
160 
`endif
161 
 
162 
//
163 
// GPIO Output Register (or no register)
164 
//
165 
`ifdef GPIO_RGPIO_OUT
166 
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
167 
`else
168 
wire    [gw-1:0] rgpio_out;      // No register
169 
`endif
170 
 
171 
//
172 
// GPIO Output Driver Enable Register (or no register)
173 
//
174 
`ifdef GPIO_RGPIO_OE
175 
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
176 
`else
177 
wire    [gw-1:0] rgpio_oe;       // No register
178 
`endif
179 
 
180 
//
181 
// GPIO Interrupt Enable Register (or no register)
182 
//
183 
`ifdef GPIO_RGPIO_INTE
184 
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
185 
`else
186 
wire    [gw-1:0] rgpio_inte;     // No register
187 
`endif
188 
 
189 
//
190 
// GPIO Positive edge Triggered Register (or no register)
191 
//
192 
`ifdef GPIO_RGPIO_PTRIG
193 
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
194 
`else
195 
wire    [gw-1:0] rgpio_ptrig;    // No register
196 
`endif
197 
 
198 
//
199 
// GPIO Auxiliary select Register (or no register)
200 
//
201 
`ifdef GPIO_RGPIO_AUX
202 
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
203 
`else
204 
wire    [gw-1:0] rgpio_aux;      // No register
205 
`endif
206 
 
207 
//
208 
// GPIO Control Register (or no register)
209 
//
210 
`ifdef GPIO_RGPIO_CTRL
211 56 gorand 
reg     [1:0]            rgpio_ctrl;     // RGPIO_CTRL register
212 14 lampret 
`else
213 56 gorand 
wire    [1:0]            rgpio_ctrl;     // No register
214 14 lampret 
`endif
215 
 
216 
//
217 21 lampret 
// GPIO Interrupt Status Register (or no register)
218 
//
219 
`ifdef GPIO_RGPIO_INTS
220 
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
221 
`else
222 
wire    [gw-1:0] rgpio_ints;     // No register
223 
`endif
224 
 
225 
//
226 56 gorand 
// GPIO Enable Clock  Register (or no register)
227 
//
228 
`ifdef GPIO_RGPIO_ECLK
229 
reg     [gw-1:0] rgpio_eclk;     // RGPIO_ECLK register
230 
`else
231 
wire    [gw-1:0] rgpio_eclk;     // No register
232 
`endif
233 
 
234 
//
235 
// GPIO Active Negative Edge  Register (or no register)
236 
//
237 
`ifdef GPIO_RGPIO_NEC
238 
reg     [gw-1:0] rgpio_nec;      // RGPIO_NEC register
239 
`else
240 
wire    [gw-1:0] rgpio_nec;      // No register
241 
`endif
242 
 
243 
//
244 14 lampret 
// Internal wires & regs
245 
//
246 56 gorand 
wire      rgpio_out_sel;  // RGPIO_OUT select
247 
wire      rgpio_oe_sel; // RGPIO_OE select
248 
wire      rgpio_inte_sel; // RGPIO_INTE select
249 
wire      rgpio_ptrig_sel;// RGPIO_PTRIG select
250 
wire      rgpio_aux_sel;  // RGPIO_AUX select
251 
wire      rgpio_ctrl_sel; // RGPIO_CTRL select
252 
wire      rgpio_ints_sel; // RGPIO_INTS select
253 
wire      rgpio_eclk_sel ;
254 
wire      rgpio_nec_sel ;
255 
wire      full_decoding;  // Full address decoding qualification
256 
wire  [gw-1:0]  in_muxed; // Muxed inputs
257 
wire      wb_ack;   // WB Acknowledge
258 
wire      wb_err;   // WB Error
259 
wire      wb_inta;  // WB Interrupt
260 
reg [dw-1:0]  wb_dat;   // WB Data out
261 17 lampret 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
262 56 gorand 
reg     wb_ack_o; // WB Acknowledge
263 
reg     wb_err_o; // WB Error
264 
reg     wb_inta_o;  // WB Interrupt
265 
reg [dw-1:0]  wb_dat_o; // WB Data out
266 17 lampret 
`endif
267 56 gorand 
wire  [gw-1:0]  out_pad;  // GPIO Outputs
268 17 lampret 
`ifdef GPIO_REGISTERED_IO_OUTPUTS
269 56 gorand 
reg [gw-1:0]  ext_pad_o;  // GPIO Outputs
270 17 lampret 
`endif
271 56 gorand 
wire  [gw-1:0]  extc_in;  // Muxed inputs sampled by external clock
272 
wire  [gw-1:0]  pext_clk; // External clock for posedge flops
273 
reg [gw-1:0]  pextc_sampled;  // Posedge external clock sampled inputs
274 17 lampret 
`ifdef GPIO_NO_NEGEDGE_FLOPS
275 
`else
276 56 gorand 
reg [gw-1:0]  nextc_sampled;  // Negedge external clock sampled inputs
277 17 lampret 
`endif
278 14 lampret 
 
279 56 gorand 
 
280 14 lampret 
//
281 
// All WISHBONE transfer terminations are successful except when:
282 
// a) full address decoding is enabled and address doesn't match
283 
//    any of the GPIO registers
284 
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
285 
//
286 17 lampret 
 
287 
//
288 
// WB Acknowledge
289 
//
290 
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
291 
 
292 
//
293 
// Optional registration of WB Ack
294 
//
295 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
296 
always @(posedge wb_clk_i or posedge wb_rst_i)
297 
        if (wb_rst_i)
298 
                wb_ack_o <= #1 1'b0;
299 
        else
300 34 gorand 
                wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
301 17 lampret 
`else
302 
assign wb_ack_o = wb_ack;
303 
`endif
304 
 
305 
//
306 
// WB Error
307 
//
308 14 lampret 
`ifdef GPIO_FULL_DECODE
309 
`ifdef GPIO_STRICT_32BIT_ACCESS
310 17 lampret 
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
311 14 lampret 
`else
312 17 lampret 
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
313 14 lampret 
`endif
314 
`else
315 
`ifdef GPIO_STRICT_32BIT_ACCESS
316 17 lampret 
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
317 14 lampret 
`else
318 17 lampret 
assign wb_err = 1'b0;
319 14 lampret 
`endif
320 
`endif
321 
 
322 
//
323 17 lampret 
// Optional registration of WB error
324 14 lampret 
//
325 17 lampret 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
326 
always @(posedge wb_clk_i or posedge wb_rst_i)
327 
        if (wb_rst_i)
328 
                wb_err_o <= #1 1'b0;
329 
        else
330 23 lampret 
                wb_err_o <= #1 wb_err & ~wb_err_o;
331 17 lampret 
`else
332 
assign wb_err_o = wb_err;
333 
`endif
334 14 lampret 
 
335 
//
336 
// Full address decoder
337 
//
338 
`ifdef GPIO_FULL_DECODE
339 
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
340 
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
341 
`else
342 
assign full_decoding = 1'b1;
343 
`endif
344 
 
345 
//
346 
// GPIO registers address decoder
347 
//
348 
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
349 
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
350 
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
351 
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
352 
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
353 
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
354 21 lampret 
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
355 14 lampret 
 
356 56 gorand 
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
357 
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
358 
 
359 
 
360 
 
361 14 lampret 
//
362 
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
363 
//
364 
`ifdef GPIO_RGPIO_CTRL
365 
always @(posedge wb_clk_i or posedge wb_rst_i)
366 
        if (wb_rst_i)
367 56 gorand 
                rgpio_ctrl <= #1 2'b0;
368 14 lampret 
        else if (rgpio_ctrl_sel && wb_we_i)
369 56 gorand 
                rgpio_ctrl <= #1 wb_dat_i[1:0];
370 14 lampret 
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
371 21 lampret 
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
372 14 lampret 
`else
373 56 gorand 
assign rgpio_ctrl = 2'h01;      // RGPIO_CTRL[EN] = 1
374 14 lampret 
`endif
375 
 
376 
//
377 
// Write to RGPIO_OUT
378 
//
379 
`ifdef GPIO_RGPIO_OUT
380 
always @(posedge wb_clk_i or posedge wb_rst_i)
381 
        if (wb_rst_i)
382 
                rgpio_out <= #1 {gw{1'b0}};
383 
        else if (rgpio_out_sel && wb_we_i)
384 34 gorand 
    begin
385 
`ifdef GPIO_STRICT_32BIT_ACCESS
386 14 lampret 
                rgpio_out <= #1 wb_dat_i[gw-1:0];
387 34 gorand 
`endif
388 
 
389 
`ifdef GPIO_WB_BYTES4
390 
     if ( wb_sel_i [3] == 1'b1 )
391 
       rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
392 
     if ( wb_sel_i [2] == 1'b1 )
393 
       rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
394 
     if ( wb_sel_i [1] == 1'b1 )
395 
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
396 
     if ( wb_sel_i [0] == 1'b1 )
397 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
398 
`endif
399 
`ifdef GPIO_WB_BYTES3
400 
     if ( wb_sel_i [2] == 1'b1 )
401 
       rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
402 
     if ( wb_sel_i [1] == 1'b1 )
403 
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
404 
     if ( wb_sel_i [0] == 1'b1 )
405 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
406 
`endif
407 
`ifdef GPIO_WB_BYTES2
408 
     if ( wb_sel_i [1] == 1'b1 )
409 
       rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
410 
     if ( wb_sel_i [0] == 1'b1 )
411 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
412 
`endif
413 
`ifdef GPIO_WB_BYTES1
414 
     if ( wb_sel_i [0] == 1'b1 )
415 
       rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
416 
`endif
417 
   end
418 
 
419 14 lampret 
`else
420 17 lampret 
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
421 14 lampret 
`endif
422 
 
423 
//
424 17 lampret 
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
425 14 lampret 
//
426 
`ifdef GPIO_RGPIO_OE
427 36 gorand 
always @(posedge wb_clk_i or posedge wb_rst_i)
428 
        if (wb_rst_i)
429 14 lampret 
                rgpio_oe <= #1 {gw{1'b0}};
430 36 gorand 
        else if (rgpio_oe_sel && wb_we_i)
431 34 gorand 
  begin
432 
`ifdef GPIO_STRICT_32BIT_ACCESS
433 17 lampret 
                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
434 34 gorand 
`endif
435 
 
436 
`ifdef GPIO_WB_BYTES4
437 36 gorand 
     if ( wb_sel_i [3] == 1'b1 )
438 34 gorand 
       rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;
439 36 gorand 
     if ( wb_sel_i [2] == 1'b1 )
440 34 gorand 
       rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;
441 36 gorand 
     if ( wb_sel_i [1] == 1'b1 )
442 34 gorand 
       rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
443 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
444 34 gorand 
       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
445 
`endif
446 
`ifdef GPIO_WB_BYTES3
447 36 gorand 
     if ( wb_sel_i [2] == 1'b1 )
448 34 gorand 
       rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;
449 36 gorand 
     if ( wb_sel_i [1] == 1'b1 )
450 34 gorand 
       rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
451 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
452 34 gorand 
       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
453 
`endif
454 
`ifdef GPIO_WB_BYTES2
455 36 gorand 
     if ( wb_sel_i [1] == 1'b1 )
456 34 gorand 
       rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;
457 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
458 34 gorand 
       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
459 
`endif
460 
`ifdef GPIO_WB_BYTES1
461 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
462 34 gorand 
       rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;
463 
`endif
464 
   end
465 
 
466 14 lampret 
`else
467 
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
468 
`endif
469 
 
470 
//
471 
// Write to RGPIO_INTE
472 
//
473 
`ifdef GPIO_RGPIO_INTE
474 
always @(posedge wb_clk_i or posedge wb_rst_i)
475 
        if (wb_rst_i)
476 
                rgpio_inte <= #1 {gw{1'b0}};
477 
        else if (rgpio_inte_sel && wb_we_i)
478 34 gorand 
  begin
479 
`ifdef GPIO_STRICT_32BIT_ACCESS
480 14 lampret 
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
481 34 gorand 
`endif
482 
 
483 
`ifdef GPIO_WB_BYTES4
484 
     if ( wb_sel_i [3] == 1'b1 )
485 
       rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
486 
     if ( wb_sel_i [2] == 1'b1 )
487 
       rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
488 
     if ( wb_sel_i [1] == 1'b1 )
489 
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
490 
     if ( wb_sel_i [0] == 1'b1 )
491 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
492 
`endif
493 
`ifdef GPIO_WB_BYTES3
494 
     if ( wb_sel_i [2] == 1'b1 )
495 
       rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
496 
     if ( wb_sel_i [1] == 1'b1 )
497 
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
498 
     if ( wb_sel_i [0] == 1'b1 )
499 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
500 
`endif
501 
`ifdef GPIO_WB_BYTES2
502 
     if ( wb_sel_i [1] == 1'b1 )
503 
       rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
504 
     if ( wb_sel_i [0] == 1'b1 )
505 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
506 
`endif
507 
`ifdef GPIO_WB_BYTES1
508 
     if ( wb_sel_i [0] == 1'b1 )
509 
       rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
510 
`endif
511 
   end
512 
 
513 
 
514 14 lampret 
`else
515 
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
516 
`endif
517 
 
518 
//
519 
// Write to RGPIO_PTRIG
520 
//
521 
`ifdef GPIO_RGPIO_PTRIG
522 
always @(posedge wb_clk_i or posedge wb_rst_i)
523 
        if (wb_rst_i)
524 
                rgpio_ptrig <= #1 {gw{1'b0}};
525 
        else if (rgpio_ptrig_sel && wb_we_i)
526 34 gorand 
  begin
527 
`ifdef GPIO_STRICT_32BIT_ACCESS
528 14 lampret 
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
529 34 gorand 
`endif
530 
 
531 
`ifdef GPIO_WB_BYTES4
532 
     if ( wb_sel_i [3] == 1'b1 )
533 
       rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
534 
     if ( wb_sel_i [2] == 1'b1 )
535 
       rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
536 
     if ( wb_sel_i [1] == 1'b1 )
537 
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
538 
     if ( wb_sel_i [0] == 1'b1 )
539 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
540 
`endif
541 
`ifdef GPIO_WB_BYTES3
542 
     if ( wb_sel_i [2] == 1'b1 )
543 
       rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
544 
     if ( wb_sel_i [1] == 1'b1 )
545 
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
546 
     if ( wb_sel_i [0] == 1'b1 )
547 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
548 
`endif
549 
`ifdef GPIO_WB_BYTES2
550 
     if ( wb_sel_i [1] == 1'b1 )
551 
       rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
552 
     if ( wb_sel_i [0] == 1'b1 )
553 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
554 
`endif
555 
`ifdef GPIO_WB_BYTES1
556 
     if ( wb_sel_i [0] == 1'b1 )
557 
       rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
558 
`endif
559 
   end
560 
 
561 14 lampret 
`else
562 
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
563 
`endif
564 
 
565 
//
566 
// Write to RGPIO_AUX
567 
//
568 
`ifdef GPIO_RGPIO_AUX
569 
always @(posedge wb_clk_i or posedge wb_rst_i)
570 
        if (wb_rst_i)
571 
                rgpio_aux <= #1 {gw{1'b0}};
572 
        else if (rgpio_aux_sel && wb_we_i)
573 34 gorand 
  begin
574 
`ifdef GPIO_STRICT_32BIT_ACCESS
575 14 lampret 
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
576 34 gorand 
`endif
577 
 
578 
`ifdef GPIO_WB_BYTES4
579 
     if ( wb_sel_i [3] == 1'b1 )
580 
       rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
581 
     if ( wb_sel_i [2] == 1'b1 )
582 
       rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
583 
     if ( wb_sel_i [1] == 1'b1 )
584 
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
585 
     if ( wb_sel_i [0] == 1'b1 )
586 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
587 
`endif
588 
`ifdef GPIO_WB_BYTES3
589 
     if ( wb_sel_i [2] == 1'b1 )
590 
       rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
591 
     if ( wb_sel_i [1] == 1'b1 )
592 
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
593 
     if ( wb_sel_i [0] == 1'b1 )
594 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
595 
`endif
596 
`ifdef GPIO_WB_BYTES2
597 
     if ( wb_sel_i [1] == 1'b1 )
598 
       rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
599 
     if ( wb_sel_i [0] == 1'b1 )
600 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
601 
`endif
602 
`ifdef GPIO_WB_BYTES1
603 
     if ( wb_sel_i [0] == 1'b1 )
604 
       rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
605 
`endif
606 
   end
607 
 
608 14 lampret 
`else
609 
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
610 
`endif
611 
 
612 56 gorand 
 
613 14 lampret 
//
614 56 gorand 
// Write to RGPIO_ECLK
615 
//
616 
`ifdef GPIO_RGPIO_ECLK
617 
always @(posedge wb_clk_i or posedge wb_rst_i)
618 
        if (wb_rst_i)
619 
                rgpio_eclk <= #1 {gw{1'b0}};
620 
        else if (rgpio_eclk_sel && wb_we_i)
621 
  begin
622 
`ifdef GPIO_STRICT_32BIT_ACCESS
623 
                rgpio_eclk <= #1 wb_dat_i[gw-1:0];
624 
`endif
625 
 
626 
`ifdef GPIO_WB_BYTES4
627 
     if ( wb_sel_i [3] == 1'b1 )
628 
       rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
629 
     if ( wb_sel_i [2] == 1'b1 )
630 
       rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ;
631 
     if ( wb_sel_i [1] == 1'b1 )
632 
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
633 
     if ( wb_sel_i [0] == 1'b1 )
634 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
635 
`endif
636 
`ifdef GPIO_WB_BYTES3
637 
     if ( wb_sel_i [2] == 1'b1 )
638 
       rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
639 
     if ( wb_sel_i [1] == 1'b1 )
640 
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
641 
     if ( wb_sel_i [0] == 1'b1 )
642 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
643 
`endif
644 
`ifdef GPIO_WB_BYTES2
645 
     if ( wb_sel_i [1] == 1'b1 )
646 
       rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
647 
     if ( wb_sel_i [0] == 1'b1 )
648 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
649 
`endif
650 
`ifdef GPIO_WB_BYTES1
651 
     if ( wb_sel_i [0] == 1'b1 )
652 
       rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
653 
`endif
654 
   end
655 
 
656 
 
657 
`else
658 
assign rgpio_eclk = `GPIO_DEF_RPGIO_ECLK;       // RGPIO_ECLK = 0x0
659 
`endif
660 
 
661 
 
662 
 
663 
//
664 
// Write to RGPIO_NEC
665 
//
666 
`ifdef GPIO_RGPIO_NEC
667 
always @(posedge wb_clk_i or posedge wb_rst_i)
668 
        if (wb_rst_i)
669 
                rgpio_nec <= #1 {gw{1'b0}};
670 
        else if (rgpio_nec_sel && wb_we_i)
671 
  begin
672 
`ifdef GPIO_STRICT_32BIT_ACCESS
673 
                rgpio_nec <= #1 wb_dat_i[gw-1:0];
674 
`endif
675 
 
676 
`ifdef GPIO_WB_BYTES4
677 
     if ( wb_sel_i [3] == 1'b1 )
678 
       rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
679 
     if ( wb_sel_i [2] == 1'b1 )
680 
       rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ;
681 
     if ( wb_sel_i [1] == 1'b1 )
682 
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
683 
     if ( wb_sel_i [0] == 1'b1 )
684 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
685 
`endif
686 
`ifdef GPIO_WB_BYTES3
687 
     if ( wb_sel_i [2] == 1'b1 )
688 
       rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
689 
     if ( wb_sel_i [1] == 1'b1 )
690 
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
691 
     if ( wb_sel_i [0] == 1'b1 )
692 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
693 
`endif
694 
`ifdef GPIO_WB_BYTES2
695 
     if ( wb_sel_i [1] == 1'b1 )
696 
       rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
697 
     if ( wb_sel_i [0] == 1'b1 )
698 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
699 
`endif
700 
`ifdef GPIO_WB_BYTES1
701 
     if ( wb_sel_i [0] == 1'b1 )
702 
       rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
703 
`endif
704 
   end
705 
 
706 
 
707 
`else
708 
assign rgpio_nec = `GPIO_DEF_RPGIO_NEC; // RGPIO_NEC = 0x0
709 
`endif
710 
 
711 
 
712 
//
713 14 lampret 
// Latch into RGPIO_IN
714 
//
715 
`ifdef GPIO_RGPIO_IN
716 17 lampret 
always @(posedge wb_clk_i or posedge wb_rst_i)
717 14 lampret 
        if (wb_rst_i)
718 
                rgpio_in <= #1 {gw{1'b0}};
719 
        else
720 17 lampret 
                rgpio_in <= #1 in_muxed;
721 14 lampret 
`else
722 17 lampret 
assign rgpio_in = in_muxed;
723 14 lampret 
`endif
724 
 
725 
//
726 17 lampret 
// Mux inputs directly from input pads with inputs sampled by external clock
727 14 lampret 
//
728 56 gorand 
//assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
729 17 lampret 
 
730 56 gorand 
 
731 
`ifdef GPIO_LINES32
732 
assign  in_muxed [31] = rgpio_eclk [31] ? extc_in[31] : ext_pad_i[31] ;
733 
`endif
734 
 
735 
`ifdef GPIO_LINES31
736 
assign  in_muxed [30] = rgpio_eclk [30] ? extc_in[30] : ext_pad_i[30] ;
737 
`endif
738 
 
739 
`ifdef GPIO_LINES30
740 
assign  in_muxed [29] = rgpio_eclk [29] ? extc_in[29] : ext_pad_i[29] ;
741 
`endif
742 
 
743 
`ifdef GPIO_LINES29
744 
assign  in_muxed [28] = rgpio_eclk [28] ? extc_in[28] : ext_pad_i[28] ;
745 
`endif
746 
 
747 
`ifdef GPIO_LINES28
748 
assign  in_muxed [27] = rgpio_eclk [27] ? extc_in[27] : ext_pad_i[27] ;
749 
`endif
750 
 
751 
`ifdef GPIO_LINES27
752 
assign  in_muxed [26] = rgpio_eclk [26] ? extc_in[26] : ext_pad_i[26] ;
753 
`endif
754 
 
755 
`ifdef GPIO_LINES26
756 
assign  in_muxed [25] = rgpio_eclk [25] ? extc_in[25] : ext_pad_i[25] ;
757 
`endif
758 
 
759 
`ifdef GPIO_LINES25
760 
assign  in_muxed [24] = rgpio_eclk [24] ? extc_in[24] : ext_pad_i[24] ;
761 
`endif
762 
 
763 
`ifdef GPIO_LINES24
764 
assign  in_muxed [23] = rgpio_eclk [23] ? extc_in[23] : ext_pad_i[23] ;
765 
`endif
766 
 
767 
`ifdef GPIO_LINES23
768 
assign  in_muxed [22] = rgpio_eclk [22] ? extc_in[22] : ext_pad_i[22] ;
769 
`endif
770 
 
771 
`ifdef GPIO_LINES22
772 
assign  in_muxed [21] = rgpio_eclk [21] ? extc_in[21] : ext_pad_i[21] ;
773 
`endif
774 
 
775 
`ifdef GPIO_LINES21
776 
assign  in_muxed [20] = rgpio_eclk [20] ? extc_in[20] : ext_pad_i[20] ;
777 
`endif
778 
 
779 
`ifdef GPIO_LINES20
780 
assign  in_muxed [19] = rgpio_eclk [19] ? extc_in[19] : ext_pad_i[19] ;
781 
`endif
782 
 
783 
`ifdef GPIO_LINES19
784 
assign  in_muxed [18] = rgpio_eclk [18] ? extc_in[18] : ext_pad_i[18] ;
785 
`endif
786 
 
787 
`ifdef GPIO_LINES18
788 
assign  in_muxed [17] = rgpio_eclk [17] ? extc_in[17] : ext_pad_i[17] ;
789 
`endif
790 
 
791 
`ifdef GPIO_LINES17
792 
assign  in_muxed [16] = rgpio_eclk [16] ? extc_in[16] : ext_pad_i[16] ;
793 
`endif
794 
 
795 
`ifdef GPIO_LINES16
796 
assign  in_muxed [15] = rgpio_eclk [15] ? extc_in[15] : ext_pad_i[15] ;
797 
`endif
798 
 
799 
`ifdef GPIO_LINES15
800 
assign  in_muxed [14] = rgpio_eclk [14] ? extc_in[14] : ext_pad_i[14] ;
801 
`endif
802 
 
803 
`ifdef GPIO_LINES14
804 
assign  in_muxed [13] = rgpio_eclk [13] ? extc_in[13] : ext_pad_i[13] ;
805 
`endif
806 
 
807 
`ifdef GPIO_LINES13
808 
assign  in_muxed [12] = rgpio_eclk [12] ? extc_in[12] : ext_pad_i[12] ;
809 
`endif
810 
 
811 
`ifdef GPIO_LINES12
812 
assign  in_muxed [11] = rgpio_eclk [11] ? extc_in[11] : ext_pad_i[11] ;
813 
`endif
814 
 
815 
`ifdef GPIO_LINES11
816 
assign  in_muxed [10] = rgpio_eclk [10] ? extc_in[10] : ext_pad_i[10] ;
817 
`endif
818 
 
819 
`ifdef GPIO_LINES10
820 
assign  in_muxed [9] = rgpio_eclk [9] ? extc_in[9] : ext_pad_i[9] ;
821 
`endif
822 
 
823 
`ifdef GPIO_LINES9
824 
assign  in_muxed [8] = rgpio_eclk [8] ? extc_in[8] : ext_pad_i[8] ;
825 
`endif
826 
 
827 
`ifdef GPIO_LINES8
828 
assign  in_muxed [7] = rgpio_eclk [7] ? extc_in[7] : ext_pad_i[7] ;
829 
`endif
830 
 
831 
`ifdef GPIO_LINES7
832 
assign  in_muxed [6] = rgpio_eclk [6] ? extc_in[6] : ext_pad_i[6] ;
833 
`endif
834 
 
835 
`ifdef GPIO_LINES6
836 
assign  in_muxed [5] = rgpio_eclk [5] ? extc_in[5] : ext_pad_i[5] ;
837 
`endif
838 
 
839 
`ifdef GPIO_LINES5
840 
assign  in_muxed [4] = rgpio_eclk [4] ? extc_in[4] : ext_pad_i[4] ;
841 
`endif
842 
 
843 
`ifdef GPIO_LINES4
844 
assign  in_muxed [3] = rgpio_eclk [3] ? extc_in[3] : ext_pad_i[3] ;
845 
`endif
846 
 
847 
`ifdef GPIO_LINES3
848 
assign  in_muxed [2] = rgpio_eclk [2] ? extc_in[2] : ext_pad_i[2] ;
849 
`endif
850 
 
851 
`ifdef GPIO_LINES2
852 
assign  in_muxed [1] = rgpio_eclk [1] ? extc_in[1] : ext_pad_i[1] ;
853 
`endif
854 
 
855 
`ifdef GPIO_LINES1
856 
assign  in_muxed [0] = rgpio_eclk [0] ? extc_in[0] : ext_pad_i[0] ;
857 
`endif
858 
 
859 
 
860 17 lampret 
//
861 
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
862 
// If negedge flops are allowed, pext_clk only clocks posedge flops.
863 
//
864 
`ifdef GPIO_NO_NEGEDGE_FLOPS
865 29 lampret 
`ifdef GPIO_NO_CLKPAD_LOGIC
866 56 gorand 
assign pext_clk = {gw{clk_pad_i}};
867 29 lampret 
`else
868 56 gorand 
 
869 
//assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
870 
 
871 
 
872 
`ifdef GPIO_LINES32
873 
assign  pext_clk [31] = rgpio_nec [31] ? ~clk_pad_i : clk_pad_i ;
874 29 lampret 
`endif
875 56 gorand 
 
876 
`ifdef GPIO_LINES31
877 
assign  pext_clk [30] = rgpio_nec [30] ? ~clk_pad_i : clk_pad_i ;
878 
`endif
879 
 
880 
`ifdef GPIO_LINES30
881 
assign  pext_clk [29] = rgpio_nec [29] ? ~clk_pad_i : clk_pad_i ;
882 
`endif
883 
 
884 
`ifdef GPIO_LINES29
885 
assign  pext_clk [28] = rgpio_nec [28] ? ~clk_pad_i : clk_pad_i ;
886 
`endif
887 
 
888 
`ifdef GPIO_LINES28
889 
assign  pext_clk [27] = rgpio_nec [27] ? ~clk_pad_i : clk_pad_i ;
890 
`endif
891 
 
892 
`ifdef GPIO_LINES27
893 
assign  pext_clk [26] = rgpio_nec [26] ? ~clk_pad_i : clk_pad_i ;
894 
`endif
895 
 
896 
`ifdef GPIO_LINES26
897 
assign  pext_clk [25] = rgpio_nec [25] ? ~clk_pad_i : clk_pad_i ;
898 
`endif
899 
 
900 
`ifdef GPIO_LINES25
901 
assign  pext_clk [24] = rgpio_nec [24] ? ~clk_pad_i : clk_pad_i ;
902 
`endif
903 
 
904 
`ifdef GPIO_LINES24
905 
assign  pext_clk [23] = rgpio_nec [23] ? ~clk_pad_i : clk_pad_i ;
906 
`endif
907 
 
908 
`ifdef GPIO_LINES23
909 
assign  pext_clk [22] = rgpio_nec [22] ? ~clk_pad_i : clk_pad_i ;
910 
`endif
911 
 
912 
`ifdef GPIO_LINES22
913 
assign  pext_clk [21] = rgpio_nec [21] ? ~clk_pad_i : clk_pad_i ;
914 
`endif
915 
 
916 
`ifdef GPIO_LINES21
917 
assign  pext_clk [20] = rgpio_nec [20] ? ~clk_pad_i : clk_pad_i ;
918 
`endif
919 
 
920 
`ifdef GPIO_LINES20
921 
assign  pext_clk [19] = rgpio_nec [19] ? ~clk_pad_i : clk_pad_i ;
922 
`endif
923 
 
924 
`ifdef GPIO_LINES19
925 
assign  pext_clk [18] = rgpio_nec [18] ? ~clk_pad_i : clk_pad_i ;
926 
`endif
927 
 
928 
`ifdef GPIO_LINES18
929 
assign  pext_clk [17] = rgpio_nec [17] ? ~clk_pad_i : clk_pad_i ;
930 
`endif
931 
 
932 
`ifdef GPIO_LINES17
933 
assign  pext_clk [16] = rgpio_nec [16] ? ~clk_pad_i : clk_pad_i ;
934 
`endif
935 
 
936 
`ifdef GPIO_LINES16
937 
assign  pext_clk [15] = rgpio_nec [15] ? ~clk_pad_i : clk_pad_i ;
938 
`endif
939 
 
940 
`ifdef GPIO_LINES15
941 
assign  pext_clk [14] = rgpio_nec [14] ? ~clk_pad_i : clk_pad_i ;
942 
`endif
943 
 
944 
`ifdef GPIO_LINES14
945 
assign  pext_clk [13] = rgpio_nec [13] ? ~clk_pad_i : clk_pad_i ;
946 
`endif
947 
 
948 
`ifdef GPIO_LINES13
949 
assign  pext_clk [12] = rgpio_nec [12] ? ~clk_pad_i : clk_pad_i ;
950 
`endif
951 
 
952 
`ifdef GPIO_LINES12
953 
assign  pext_clk [11] = rgpio_nec [11] ? ~clk_pad_i : clk_pad_i ;
954 
`endif
955 
 
956 
`ifdef GPIO_LINES11
957 
assign  pext_clk [10] = rgpio_nec [10] ? ~clk_pad_i : clk_pad_i ;
958 
`endif
959 
 
960 
`ifdef GPIO_LINES10
961 
assign  pext_clk [9] = rgpio_nec [9] ? ~clk_pad_i : clk_pad_i ;
962 
`endif
963 
 
964 
`ifdef GPIO_LINES9
965 
assign  pext_clk [8] = rgpio_nec [8] ? ~clk_pad_i : clk_pad_i ;
966 
`endif
967 
 
968 
`ifdef GPIO_LINES8
969 
assign  pext_clk [7] = rgpio_nec [7] ? ~clk_pad_i : clk_pad_i ;
970 
`endif
971 
 
972 
`ifdef GPIO_LINES7
973 
assign  pext_clk [6] = rgpio_nec [6] ? ~clk_pad_i : clk_pad_i ;
974 
`endif
975 
 
976 
`ifdef GPIO_LINES6
977 
assign  pext_clk [5] = rgpio_nec [5] ? ~clk_pad_i : clk_pad_i ;
978 
`endif
979 
 
980 
`ifdef GPIO_LINES5
981 
assign  pext_clk [4] = rgpio_nec [4] ? ~clk_pad_i : clk_pad_i ;
982 
`endif
983 
 
984 
`ifdef GPIO_LINES4
985 
assign  pext_clk [3] = rgpio_nec [3] ? ~clk_pad_i : clk_pad_i ;
986 
`endif
987 
 
988 
`ifdef GPIO_LINES3
989 
assign  pext_clk [2] = rgpio_nec [2] ? ~clk_pad_i : clk_pad_i ;
990 
`endif
991 
 
992 
`ifdef GPIO_LINES2
993 
assign  pext_clk [1] = rgpio_nec [1] ? ~clk_pad_i : clk_pad_i ;
994 
`endif
995 
 
996 
`ifdef GPIO_LINES1
997 
assign  pext_clk [0] = rgpio_nec [0] ? ~clk_pad_i : clk_pad_i ;
998 
`endif
999 
 
1000 
`endif
1001 17 lampret 
`else
1002 56 gorand 
assign pext_clk = {gw{clk_pad_i}};
1003 17 lampret 
`endif
1004 
 
1005 56 gorand 
 
1006 17 lampret 
//
1007 
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
1008 
//
1009 
`ifdef GPIO_NO_NEGEDGE_FLOPS
1010 
assign extc_in = pextc_sampled;
1011 
`else
1012 56 gorand 
//assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
1013 
 
1014 
 
1015 
`ifdef GPIO_LINES32
1016 
assign  extc_in [31] = rgpio_nec [31] ? nextc_sampled[31] : pextc_sampled[31] ;
1017 17 lampret 
`endif
1018 
 
1019 56 gorand 
`ifdef GPIO_LINES31
1020 
assign  extc_in [30] = rgpio_nec [30] ? nextc_sampled[30] : pextc_sampled[30] ;
1021 
`endif
1022 
 
1023 
`ifdef GPIO_LINES30
1024 
assign  extc_in [29] = rgpio_nec [29] ? nextc_sampled[29] : pextc_sampled[29] ;
1025 
`endif
1026 
 
1027 
`ifdef GPIO_LINES29
1028 
assign  extc_in [28] = rgpio_nec [28] ? nextc_sampled[28] : pextc_sampled[28] ;
1029 
`endif
1030 
 
1031 
`ifdef GPIO_LINES28
1032 
assign  extc_in [27] = rgpio_nec [27] ? nextc_sampled[27] : pextc_sampled[27] ;
1033 
`endif
1034 
 
1035 
`ifdef GPIO_LINES27
1036 
assign  extc_in [26] = rgpio_nec [26] ? nextc_sampled[26] : pextc_sampled[26] ;
1037 
`endif
1038 
 
1039 
`ifdef GPIO_LINES26
1040 
assign  extc_in [25] = rgpio_nec [25] ? nextc_sampled[25] : pextc_sampled[25] ;
1041 
`endif
1042 
 
1043 
`ifdef GPIO_LINES25
1044 
assign  extc_in [24] = rgpio_nec [24] ? nextc_sampled[24] : pextc_sampled[24] ;
1045 
`endif
1046 
 
1047 
`ifdef GPIO_LINES24
1048 
assign  extc_in [23] = rgpio_nec [23] ? nextc_sampled[23] : pextc_sampled[23] ;
1049 
`endif
1050 
 
1051 
`ifdef GPIO_LINES23
1052 
assign  extc_in [22] = rgpio_nec [22] ? nextc_sampled[22] : pextc_sampled[22] ;
1053 
`endif
1054 
 
1055 
`ifdef GPIO_LINES22
1056 
assign  extc_in [21] = rgpio_nec [21] ? nextc_sampled[21] : pextc_sampled[21] ;
1057 
`endif
1058 
 
1059 
`ifdef GPIO_LINES21
1060 
assign  extc_in [20] = rgpio_nec [20] ? nextc_sampled[20] : pextc_sampled[20] ;
1061 
`endif
1062 
 
1063 
`ifdef GPIO_LINES20
1064 
assign  extc_in [19] = rgpio_nec [19] ? nextc_sampled[19] : pextc_sampled[19] ;
1065 
`endif
1066 
 
1067 
`ifdef GPIO_LINES19
1068 
assign  extc_in [18] = rgpio_nec [18] ? nextc_sampled[18] : pextc_sampled[18] ;
1069 
`endif
1070 
 
1071 
`ifdef GPIO_LINES18
1072 
assign  extc_in [17] = rgpio_nec [17] ? nextc_sampled[17] : pextc_sampled[17] ;
1073 
`endif
1074 
 
1075 
`ifdef GPIO_LINES17
1076 
assign  extc_in [16] = rgpio_nec [16] ? nextc_sampled[16] : pextc_sampled[16] ;
1077 
`endif
1078 
 
1079 
`ifdef GPIO_LINES16
1080 
assign  extc_in [15] = rgpio_nec [15] ? nextc_sampled[15] : pextc_sampled[15] ;
1081 
`endif
1082 
 
1083 
`ifdef GPIO_LINES15
1084 
assign  extc_in [14] = rgpio_nec [14] ? nextc_sampled[14] : pextc_sampled[14] ;
1085 
`endif
1086 
 
1087 
`ifdef GPIO_LINES14
1088 
assign  extc_in [13] = rgpio_nec [13] ? nextc_sampled[13] : pextc_sampled[13] ;
1089 
`endif
1090 
 
1091 
`ifdef GPIO_LINES13
1092 
assign  extc_in [12] = rgpio_nec [12] ? nextc_sampled[12] : pextc_sampled[12] ;
1093 
`endif
1094 
 
1095 
`ifdef GPIO_LINES12
1096 
assign  extc_in [11] = rgpio_nec [11] ? nextc_sampled[11] : pextc_sampled[11] ;
1097 
`endif
1098 
 
1099 
`ifdef GPIO_LINES11
1100 
assign  extc_in [10] = rgpio_nec [10] ? nextc_sampled[10] : pextc_sampled[10] ;
1101 
`endif
1102 
 
1103 
`ifdef GPIO_LINES10
1104 
assign  extc_in [9] = rgpio_nec [9] ? nextc_sampled[9] : pextc_sampled[9] ;
1105 
`endif
1106 
 
1107 
`ifdef GPIO_LINES9
1108 
assign  extc_in [8] = rgpio_nec [8] ? nextc_sampled[8] : pextc_sampled[8] ;
1109 
`endif
1110 
 
1111 
`ifdef GPIO_LINES8
1112 
assign  extc_in [7] = rgpio_nec [7] ? nextc_sampled[7] : pextc_sampled[7] ;
1113 
`endif
1114 
 
1115 
`ifdef GPIO_LINES7
1116 
assign  extc_in [6] = rgpio_nec [6] ? nextc_sampled[6] : pextc_sampled[6] ;
1117 
`endif
1118 
 
1119 
`ifdef GPIO_LINES6
1120 
assign  extc_in [5] = rgpio_nec [5] ? nextc_sampled[5] : pextc_sampled[5] ;
1121 
`endif
1122 
 
1123 
`ifdef GPIO_LINES5
1124 
assign  extc_in [4] = rgpio_nec [4] ? nextc_sampled[4] : pextc_sampled[4] ;
1125 
`endif
1126 
 
1127 
`ifdef GPIO_LINES4
1128 
assign  extc_in [3] = rgpio_nec [3] ? nextc_sampled[3] : pextc_sampled[3] ;
1129 
`endif
1130 
 
1131 
`ifdef GPIO_LINES3
1132 
assign  extc_in [2] = rgpio_nec [2] ? nextc_sampled[2] : pextc_sampled[2] ;
1133 
`endif
1134 
 
1135 
`ifdef GPIO_LINES2
1136 
assign  extc_in [1] = rgpio_nec [1] ? nextc_sampled[1] : pextc_sampled[1] ;
1137 
`endif
1138 
 
1139 
`ifdef GPIO_LINES1
1140 
assign  extc_in [0] = rgpio_nec [0] ? nextc_sampled[0] : pextc_sampled[0] ;
1141 
`endif
1142 
 
1143 
`endif
1144 
 
1145 17 lampret 
//
1146 
// Latch using posedge external clock
1147 
//
1148 56 gorand 
 
1149 
`ifdef GPIO_LINES32
1150 
always @(posedge pext_clk[31] or posedge wb_rst_i)
1151 17 lampret 
        if (wb_rst_i)
1152 56 gorand 
                pextc_sampled[31] <= #1 1'b0;
1153 17 lampret 
        else
1154 56 gorand 
                pextc_sampled[31] <= #1 ext_pad_i[31];
1155 
`endif
1156 17 lampret 
 
1157 56 gorand 
`ifdef GPIO_LINES31
1158 
always @(posedge pext_clk[30] or posedge wb_rst_i)
1159 
  if (wb_rst_i)
1160 
    pextc_sampled[30] <= #1 1'b0;
1161 
  else
1162 
    pextc_sampled[30] <= #1 ext_pad_i[30];
1163 
`endif
1164 
 
1165 
`ifdef GPIO_LINES30
1166 
always @(posedge pext_clk[29] or posedge wb_rst_i)
1167 
  if (wb_rst_i)
1168 
    pextc_sampled[29] <= #1 1'b0;
1169 
  else
1170 
    pextc_sampled[29] <= #1 ext_pad_i[29];
1171 
`endif
1172 
 
1173 
`ifdef GPIO_LINES29
1174 
always @(posedge pext_clk[28] or posedge wb_rst_i)
1175 
  if (wb_rst_i)
1176 
    pextc_sampled[28] <= #1 1'b0;
1177 
  else
1178 
    pextc_sampled[28] <= #1 ext_pad_i[28];
1179 
`endif
1180 
 
1181 
`ifdef GPIO_LINES28
1182 
always @(posedge pext_clk[27] or posedge wb_rst_i)
1183 
  if (wb_rst_i)
1184 
    pextc_sampled[27] <= #1 1'b0;
1185 
  else
1186 
    pextc_sampled[27] <= #1 ext_pad_i[27];
1187 
`endif
1188 
 
1189 
`ifdef GPIO_LINES27
1190 
always @(posedge pext_clk[26] or posedge wb_rst_i)
1191 
  if (wb_rst_i)
1192 
    pextc_sampled[26] <= #1 1'b0;
1193 
  else
1194 
    pextc_sampled[26] <= #1 ext_pad_i[26];
1195 
`endif
1196 
 
1197 
`ifdef GPIO_LINES26
1198 
always @(posedge pext_clk[25] or posedge wb_rst_i)
1199 
  if (wb_rst_i)
1200 
    pextc_sampled[25] <= #1 1'b0;
1201 
  else
1202 
    pextc_sampled[25] <= #1 ext_pad_i[25];
1203 
`endif
1204 
 
1205 
`ifdef GPIO_LINES25
1206 
always @(posedge pext_clk[24] or posedge wb_rst_i)
1207 
  if (wb_rst_i)
1208 
    pextc_sampled[24] <= #1 1'b0;
1209 
  else
1210 
    pextc_sampled[24] <= #1 ext_pad_i[24];
1211 
`endif
1212 
 
1213 
`ifdef GPIO_LINES24
1214 
always @(posedge pext_clk[23] or posedge wb_rst_i)
1215 
  if (wb_rst_i)
1216 
    pextc_sampled[23] <= #1 1'b0;
1217 
  else
1218 
    pextc_sampled[23] <= #1 ext_pad_i[23];
1219 
`endif
1220 
 
1221 
`ifdef GPIO_LINES23
1222 
always @(posedge pext_clk[22] or posedge wb_rst_i)
1223 
  if (wb_rst_i)
1224 
    pextc_sampled[22] <= #1 1'b0;
1225 
  else
1226 
    pextc_sampled[22] <= #1 ext_pad_i[22];
1227 
`endif
1228 
 
1229 
`ifdef GPIO_LINES22
1230 
always @(posedge pext_clk[21] or posedge wb_rst_i)
1231 
  if (wb_rst_i)
1232 
    pextc_sampled[21] <= #1 1'b0;
1233 
  else
1234 
    pextc_sampled[21] <= #1 ext_pad_i[21];
1235 
`endif
1236 
 
1237 
`ifdef GPIO_LINES21
1238 
always @(posedge pext_clk[20] or posedge wb_rst_i)
1239 
  if (wb_rst_i)
1240 
    pextc_sampled[20] <= #1 1'b0;
1241 
  else
1242 
    pextc_sampled[20] <= #1 ext_pad_i[20];
1243 
`endif
1244 
 
1245 
`ifdef GPIO_LINES20
1246 
always @(posedge pext_clk[19] or posedge wb_rst_i)
1247 
  if (wb_rst_i)
1248 
    pextc_sampled[19] <= #1 1'b0;
1249 
  else
1250 
    pextc_sampled[19] <= #1 ext_pad_i[19];
1251 
`endif
1252 
 
1253 
`ifdef GPIO_LINES19
1254 
always @(posedge pext_clk[18] or posedge wb_rst_i)
1255 
  if (wb_rst_i)
1256 
    pextc_sampled[18] <= #1 1'b0;
1257 
  else
1258 
    pextc_sampled[18] <= #1 ext_pad_i[18];
1259 
`endif
1260 
 
1261 
`ifdef GPIO_LINES18
1262 
always @(posedge pext_clk[17] or posedge wb_rst_i)
1263 
  if (wb_rst_i)
1264 
    pextc_sampled[17] <= #1 1'b0;
1265 
  else
1266 
    pextc_sampled[17] <= #1 ext_pad_i[17];
1267 
`endif
1268 
 
1269 
`ifdef GPIO_LINES17
1270 
always @(posedge pext_clk[16] or posedge wb_rst_i)
1271 
  if (wb_rst_i)
1272 
    pextc_sampled[16] <= #1 1'b0;
1273 
  else
1274 
    pextc_sampled[16] <= #1 ext_pad_i[16];
1275 
`endif
1276 
 
1277 
`ifdef GPIO_LINES16
1278 
always @(posedge pext_clk[15] or posedge wb_rst_i)
1279 
  if (wb_rst_i)
1280 
    pextc_sampled[15] <= #1 1'b0;
1281 
  else
1282 
    pextc_sampled[15] <= #1 ext_pad_i[15];
1283 
`endif
1284 
 
1285 
`ifdef GPIO_LINES15
1286 
always @(posedge pext_clk[14] or posedge wb_rst_i)
1287 
  if (wb_rst_i)
1288 
    pextc_sampled[14] <= #1 1'b0;
1289 
  else
1290 
    pextc_sampled[14] <= #1 ext_pad_i[14];
1291 
`endif
1292 
 
1293 
`ifdef GPIO_LINES14
1294 
always @(posedge pext_clk[13] or posedge wb_rst_i)
1295 
  if (wb_rst_i)
1296 
    pextc_sampled[13] <= #1 1'b0;
1297 
  else
1298 
    pextc_sampled[13] <= #1 ext_pad_i[13];
1299 
`endif
1300 
 
1301 
`ifdef GPIO_LINES13
1302 
always @(posedge pext_clk[12] or posedge wb_rst_i)
1303 
  if (wb_rst_i)
1304 
    pextc_sampled[12] <= #1 1'b0;
1305 
  else
1306 
    pextc_sampled[12] <= #1 ext_pad_i[12];
1307 
`endif
1308 
 
1309 
`ifdef GPIO_LINES12
1310 
always @(posedge pext_clk[11] or posedge wb_rst_i)
1311 
  if (wb_rst_i)
1312 
    pextc_sampled[11] <= #1 1'b0;
1313 
  else
1314 
    pextc_sampled[11] <= #1 ext_pad_i[11];
1315 
`endif
1316 
 
1317 
`ifdef GPIO_LINES11
1318 
always @(posedge pext_clk[10] or posedge wb_rst_i)
1319 
  if (wb_rst_i)
1320 
    pextc_sampled[10] <= #1 1'b0;
1321 
  else
1322 
    pextc_sampled[10] <= #1 ext_pad_i[10];
1323 
`endif
1324 
 
1325 
`ifdef GPIO_LINES10
1326 
always @(posedge pext_clk[9] or posedge wb_rst_i)
1327 
  if (wb_rst_i)
1328 
    pextc_sampled[9] <= #1 1'b0;
1329 
  else
1330 
    pextc_sampled[9] <= #1 ext_pad_i[9];
1331 
`endif
1332 
 
1333 
`ifdef GPIO_LINES9
1334 
always @(posedge pext_clk[8] or posedge wb_rst_i)
1335 
  if (wb_rst_i)
1336 
    pextc_sampled[8] <= #1 1'b0;
1337 
  else
1338 
    pextc_sampled[8] <= #1 ext_pad_i[8];
1339 
`endif
1340 
 
1341 
`ifdef GPIO_LINES8
1342 
always @(posedge pext_clk[7] or posedge wb_rst_i)
1343 
  if (wb_rst_i)
1344 
    pextc_sampled[7] <= #1 1'b0;
1345 
  else
1346 
    pextc_sampled[7] <= #1 ext_pad_i[7];
1347 
`endif
1348 
 
1349 
`ifdef GPIO_LINES7
1350 
always @(posedge pext_clk[6] or posedge wb_rst_i)
1351 
  if (wb_rst_i)
1352 
    pextc_sampled[6] <= #1 1'b0;
1353 
  else
1354 
    pextc_sampled[6] <= #1 ext_pad_i[6];
1355 
`endif
1356 
 
1357 
`ifdef GPIO_LINES6
1358 
always @(posedge pext_clk[5] or posedge wb_rst_i)
1359 
  if (wb_rst_i)
1360 
    pextc_sampled[5] <= #1 1'b0;
1361 
  else
1362 
    pextc_sampled[5] <= #1 ext_pad_i[5];
1363 
`endif
1364 
 
1365 
`ifdef GPIO_LINES5
1366 
always @(posedge pext_clk[4] or posedge wb_rst_i)
1367 
  if (wb_rst_i)
1368 
    pextc_sampled[4] <= #1 1'b0;
1369 
  else
1370 
    pextc_sampled[4] <= #1 ext_pad_i[4];
1371 
`endif
1372 
 
1373 
`ifdef GPIO_LINES4
1374 
always @(posedge pext_clk[3] or posedge wb_rst_i)
1375 
  if (wb_rst_i)
1376 
    pextc_sampled[3] <= #1 1'b0;
1377 
  else
1378 
    pextc_sampled[3] <= #1 ext_pad_i[3];
1379 
`endif
1380 
 
1381 
`ifdef GPIO_LINES3
1382 
always @(posedge pext_clk[2] or posedge wb_rst_i)
1383 
  if (wb_rst_i)
1384 
    pextc_sampled[2] <= #1 1'b0;
1385 
  else
1386 
    pextc_sampled[2] <= #1 ext_pad_i[2];
1387 
`endif
1388 
 
1389 
`ifdef GPIO_LINES2
1390 
always @(posedge pext_clk[1] or posedge wb_rst_i)
1391 
  if (wb_rst_i)
1392 
    pextc_sampled[1] <= #1 1'b0;
1393 
  else
1394 
    pextc_sampled[1] <= #1 ext_pad_i[1];
1395 
`endif
1396 
 
1397 
`ifdef GPIO_LINES1
1398 
always @(posedge pext_clk[0] or posedge wb_rst_i)
1399 
  if (wb_rst_i)
1400 
    pextc_sampled[0] <= #1 1'b0;
1401 
  else
1402 
    pextc_sampled[0] <= #1 ext_pad_i[0];
1403 
`endif
1404 
 
1405 17 lampret 
//
1406 
// Latch using negedge external clock
1407 
//
1408 
`ifdef GPIO_NO_NEGEDGE_FLOPS
1409 
`else
1410 25 lampret 
always @(negedge clk_pad_i or posedge wb_rst_i)
1411 17 lampret 
        if (wb_rst_i)
1412 
                nextc_sampled <= #1 {gw{1'b0}};
1413 
        else
1414 25 lampret 
                nextc_sampled <= #1 ext_pad_i;
1415 17 lampret 
`endif
1416 
 
1417 
//
1418 
// Mux all registers when doing a read of GPIO registers
1419 
//
1420 14 lampret 
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
1421 56 gorand 
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
1422 14 lampret 
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
1423 
`ifdef GPIO_READREGS
1424 
                `GPIO_RGPIO_OUT: begin
1425 26 lampret 
                        wb_dat[dw-1:0] = rgpio_out;
1426 14 lampret 
                end
1427 
                `GPIO_RGPIO_OE: begin
1428 26 lampret 
                        wb_dat[dw-1:0] = ~rgpio_oe;
1429 14 lampret 
                end
1430 
                `GPIO_RGPIO_INTE: begin
1431 26 lampret 
                        wb_dat[dw-1:0] = rgpio_inte;
1432 14 lampret 
                end
1433 
                `GPIO_RGPIO_PTRIG: begin
1434 26 lampret 
                        wb_dat[dw-1:0] = rgpio_ptrig;
1435 14 lampret 
                end
1436 56 gorand 
                `GPIO_RGPIO_NEC: begin
1437 
                        wb_dat[dw-1:0] = rgpio_nec;
1438 
                end
1439 
                `GPIO_RGPIO_ECLK: begin
1440 
                        wb_dat[dw-1:0] = rgpio_eclk;
1441 
                end
1442 14 lampret 
                `GPIO_RGPIO_AUX: begin
1443 26 lampret 
                        wb_dat[dw-1:0] = rgpio_aux;
1444 14 lampret 
                end
1445 
                `GPIO_RGPIO_CTRL: begin
1446 56 gorand 
                        wb_dat[1:0] = rgpio_ctrl;
1447 
                        wb_dat[dw-1:2] = {dw-2{1'b0}};
1448 14 lampret 
                end
1449 
`endif
1450 21 lampret 
                `GPIO_RGPIO_INTS: begin
1451 26 lampret 
                        wb_dat[dw-1:0] = rgpio_ints;
1452 21 lampret 
                end
1453 14 lampret 
                default: begin
1454 26 lampret 
                        wb_dat[dw-1:0] = rgpio_in;
1455 14 lampret 
                end
1456 
        endcase
1457 
 
1458 
//
1459 17 lampret 
// WB data output
1460 
//
1461 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1462 
always @(posedge wb_clk_i or posedge wb_rst_i)
1463 
        if (wb_rst_i)
1464 
                wb_dat_o <= #1 {dw{1'b0}};
1465 
        else
1466 
                wb_dat_o <= #1 wb_dat;
1467 
`else
1468 
assign wb_dat_o = wb_dat;
1469 
`endif
1470 
 
1471 
//
1472 21 lampret 
// RGPIO_INTS
1473 
//
1474 
`ifdef GPIO_RGPIO_INTS
1475 
always @(posedge wb_clk_i or posedge wb_rst_i)
1476 
        if (wb_rst_i)
1477 
                rgpio_ints <= #1 {gw{1'b0}};
1478 
        else if (rgpio_ints_sel && wb_we_i)
1479 
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
1480 31 lampret 
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
1481 
                rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
1482 21 lampret 
`else
1483 31 lampret 
assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
1484 21 lampret 
`endif
1485 
 
1486 
//
1487 14 lampret 
// Generate interrupt request
1488 
//
1489 21 lampret 
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
1490 14 lampret 
 
1491 
//
1492 17 lampret 
// Optional registration of WB interrupt
1493 14 lampret 
//
1494 17 lampret 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1495 
always @(posedge wb_clk_i or posedge wb_rst_i)
1496 
        if (wb_rst_i)
1497 19 lampret 
                wb_inta_o <= #1 1'b0;
1498 17 lampret 
        else
1499 
                wb_inta_o <= #1 wb_inta;
1500 
`else
1501 
assign wb_inta_o = wb_inta;
1502 
`endif
1503 14 lampret 
 
1504 
//
1505 17 lampret 
// Output enables are RGPIO_OE bits
1506 14 lampret 
//
1507 25 lampret 
assign ext_padoen_o = rgpio_oe;
1508 14 lampret 
 
1509 17 lampret 
//
1510 
// Generate GPIO outputs
1511 
//
1512 
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
1513 
 
1514 
//
1515 
// Optional registration of GPIO outputs
1516 
//
1517 
`ifdef GPIO_REGISTERED_IO_OUTPUTS
1518 
always @(posedge wb_clk_i or posedge wb_rst_i)
1519 
        if (wb_rst_i)
1520 25 lampret 
                ext_pad_o <= #1 {gw{1'b0}};
1521 17 lampret 
        else
1522 25 lampret 
                ext_pad_o <= #1 out_pad;
1523 14 lampret 
`else
1524 25 lampret 
assign ext_pad_o = out_pad;
1525 17 lampret 
`endif
1526 14 lampret 
 
1527 17 lampret 
`else
1528 
 
1529 14 lampret 
//
1530 
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
1531 
// is cleared and WISHBONE transfers complete with errors
1532 
//
1533 
assign wb_inta_o = 1'b0;
1534 
assign wb_ack_o = 1'b0;
1535 
assign wb_err_o = wb_cyc_i & wb_stb_i;
1536 25 lampret 
assign ext_padoen_o = {gw{1'b1}};
1537 
assign ext_pad_o = {gw{1'b0}};
1538 14 lampret 
 
1539 
//
1540 
// Read GPIO registers
1541 
//
1542 
assign wb_dat_o = {dw{1'b0}};
1543 
 
1544 
`endif
1545 
 
1546 
endmodule
1547 56 gorand 
 

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