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[/] [gpio/] [tags/] [rel_14/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 67

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1 14 lampret 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  WISHBONE General-Purpose I/O                                ////
4 
////                                                              ////
5 
////  This file is part of the GPIO project                       ////
6 
////  http://www.opencores.org/cores/gpio/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Implementation of GPIO IP core according to                 ////
10 
////  GPIO IP core specification document.                        ////
11 
////                                                              ////
12 
////  To Do:                                                      ////
13 
////   Nothing                                                    ////
14 
////                                                              ////
15 
////  Author(s):                                                  ////
16 
////      - Damjan Lampret, lampret@opencores.org                 ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 60 andreje 
// Revision 1.16  2003/12/17 13:00:52  gorand
49 
// added ECLK and NEC registers, all tests passed.
50 
//
51 56 gorand 
// Revision 1.15  2003/11/10 23:21:22  gorand
52 
// bug fixed. all tests passed.
53 
//
54 36 gorand 
// Revision 1.14  2003/11/06 13:59:07  gorand
55 
// added support for 8-bit access to registers.
56 
//
57 34 gorand 
// Revision 1.13  2002/11/18 22:35:18  lampret
58 
// Bug fix. Interrupts were also asserted when condition was not met.
59 
//
60 31 lampret 
// Revision 1.12  2002/11/11 21:36:28  lampret
61 
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
62 
//
63 29 lampret 
// Revision 1.11  2002/03/13 20:56:28  lampret
64 
// Removed zero padding as per Avi Shamli suggestion.
65 
//
66 26 lampret 
// Revision 1.10  2002/03/13 20:47:57  lampret
67 
// Ports changed per Ran Aviram suggestions.
68 
//
69 25 lampret 
// Revision 1.9  2002/03/09 03:43:27  lampret
70 
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
71 
//
72 24 lampret 
// Revision 1.8  2002/01/14 19:06:28  lampret
73 
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
74 
//
75 23 lampret 
// Revision 1.7  2001/12/25 17:21:21  lampret
76 
// Fixed two typos.
77 
//
78 22 lampret 
// Revision 1.6  2001/12/25 17:12:35  lampret
79 
// Added RGPIO_INTS.
80 
//
81 21 lampret 
// Revision 1.5  2001/12/12 20:35:53  lampret
82 
// Fixing style.
83 
//
84 20 lampret 
// Revision 1.4  2001/12/12 07:12:58  lampret
85 
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
86 
//
87 19 lampret 
// Revision 1.3  2001/11/15 02:24:37  lampret
88 
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
89 
//
90 17 lampret 
// Revision 1.2  2001/10/31 02:26:51  lampret
91 
// Fixed wb_err_o.
92 
//
93 15 lampret 
// Revision 1.1  2001/09/18 18:49:07  lampret
94 
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
95 
//
96 14 lampret 
// Revision 1.1  2001/08/21 21:39:28  lampret
97 
// Changed directory structure, port names and drfines.
98 
//
99 
// Revision 1.2  2001/07/14 20:39:26  lampret
100 
// Better configurability.
101 
//
102 
// Revision 1.1  2001/06/05 07:45:26  lampret
103 
// Added initial RTL and test benches. There are still some issues with these files.
104 
//
105 
//
106 
 
107 
// synopsys translate_off
108 
`include "timescale.v"
109 
// synopsys translate_on
110 
`include "gpio_defines.v"
111 
 
112 
module gpio_top(
113 
        // WISHBONE Interface
114 
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
115 
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
116 
 
117 
        // Auxiliary inputs interface
118 
        aux_i,
119 
 
120 
        // External GPIO Interface
121 60 andreje 
        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoe_o
122 14 lampret 
);
123 
 
124 
parameter dw = 32;
125 
parameter aw = `GPIO_ADDRHH+1;
126 
parameter gw = `GPIO_IOS;
127 
//
128 
// WISHBONE Interface
129 
//
130 
input                   wb_clk_i;       // Clock
131 
input                   wb_rst_i;       // Reset
132 
input                   wb_cyc_i;       // cycle valid input
133 
input   [aw-1:0] wb_adr_i;       // address bus inputs
134 
input   [dw-1:0] wb_dat_i;       // input data bus
135 
input   [3:0]            wb_sel_i;       // byte select inputs
136 
input                   wb_we_i;        // indicates write transfer
137 
input                   wb_stb_i;       // strobe input
138 
output  [dw-1:0] wb_dat_o;       // output data bus
139 
output                  wb_ack_o;       // normal termination
140 
output                  wb_err_o;       // termination w/ error
141 
output                  wb_inta_o;      // Interrupt request output
142 
 
143 
// Auxiliary Inputs Interface
144 
input   [gw-1:0] aux_i;          // Auxiliary inputs
145 
 
146 
//
147 
// External GPIO Interface
148 
//
149 25 lampret 
input   [gw-1:0] ext_pad_i;      // GPIO Inputs
150 
input                   clk_pad_i;      // GPIO Eclk
151 
output  [gw-1:0] ext_pad_o;      // GPIO Outputs
152 60 andreje 
output  [gw-1:0] ext_padoe_o;    // GPIO output drivers enables
153 14 lampret 
 
154 
`ifdef GPIO_IMPLEMENTED
155 
 
156 
//
157 
// GPIO Input Register (or no register)
158 
//
159 
`ifdef GPIO_RGPIO_IN
160 
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
161 
`else
162 
wire    [gw-1:0] rgpio_in;       // No register
163 
`endif
164 
 
165 
//
166 
// GPIO Output Register (or no register)
167 
//
168 
`ifdef GPIO_RGPIO_OUT
169 
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
170 
`else
171 
wire    [gw-1:0] rgpio_out;      // No register
172 
`endif
173 
 
174 
//
175 
// GPIO Output Driver Enable Register (or no register)
176 
//
177 
`ifdef GPIO_RGPIO_OE
178 
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
179 
`else
180 
wire    [gw-1:0] rgpio_oe;       // No register
181 
`endif
182 
 
183 
//
184 
// GPIO Interrupt Enable Register (or no register)
185 
//
186 
`ifdef GPIO_RGPIO_INTE
187 
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
188 
`else
189 
wire    [gw-1:0] rgpio_inte;     // No register
190 
`endif
191 
 
192 
//
193 
// GPIO Positive edge Triggered Register (or no register)
194 
//
195 
`ifdef GPIO_RGPIO_PTRIG
196 
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
197 
`else
198 
wire    [gw-1:0] rgpio_ptrig;    // No register
199 
`endif
200 
 
201 
//
202 
// GPIO Auxiliary select Register (or no register)
203 
//
204 
`ifdef GPIO_RGPIO_AUX
205 
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
206 
`else
207 
wire    [gw-1:0] rgpio_aux;      // No register
208 
`endif
209 
 
210 
//
211 
// GPIO Control Register (or no register)
212 
//
213 
`ifdef GPIO_RGPIO_CTRL
214 56 gorand 
reg     [1:0]            rgpio_ctrl;     // RGPIO_CTRL register
215 14 lampret 
`else
216 56 gorand 
wire    [1:0]            rgpio_ctrl;     // No register
217 14 lampret 
`endif
218 
 
219 
//
220 21 lampret 
// GPIO Interrupt Status Register (or no register)
221 
//
222 
`ifdef GPIO_RGPIO_INTS
223 
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
224 
`else
225 
wire    [gw-1:0] rgpio_ints;     // No register
226 
`endif
227 
 
228 
//
229 56 gorand 
// GPIO Enable Clock  Register (or no register)
230 
//
231 
`ifdef GPIO_RGPIO_ECLK
232 
reg     [gw-1:0] rgpio_eclk;     // RGPIO_ECLK register
233 
`else
234 
wire    [gw-1:0] rgpio_eclk;     // No register
235 
`endif
236 
 
237 
//
238 
// GPIO Active Negative Edge  Register (or no register)
239 
//
240 
`ifdef GPIO_RGPIO_NEC
241 
reg     [gw-1:0] rgpio_nec;      // RGPIO_NEC register
242 
`else
243 
wire    [gw-1:0] rgpio_nec;      // No register
244 
`endif
245 
 
246 
//
247 14 lampret 
// Internal wires & regs
248 
//
249 56 gorand 
wire      rgpio_out_sel;  // RGPIO_OUT select
250 
wire      rgpio_oe_sel; // RGPIO_OE select
251 
wire      rgpio_inte_sel; // RGPIO_INTE select
252 
wire      rgpio_ptrig_sel;// RGPIO_PTRIG select
253 
wire      rgpio_aux_sel;  // RGPIO_AUX select
254 
wire      rgpio_ctrl_sel; // RGPIO_CTRL select
255 
wire      rgpio_ints_sel; // RGPIO_INTS select
256 
wire      rgpio_eclk_sel ;
257 
wire      rgpio_nec_sel ;
258 
wire      full_decoding;  // Full address decoding qualification
259 
wire  [gw-1:0]  in_muxed; // Muxed inputs
260 
wire      wb_ack;   // WB Acknowledge
261 
wire      wb_err;   // WB Error
262 
wire      wb_inta;  // WB Interrupt
263 
reg [dw-1:0]  wb_dat;   // WB Data out
264 17 lampret 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
265 56 gorand 
reg     wb_ack_o; // WB Acknowledge
266 
reg     wb_err_o; // WB Error
267 
reg     wb_inta_o;  // WB Interrupt
268 
reg [dw-1:0]  wb_dat_o; // WB Data out
269 17 lampret 
`endif
270 56 gorand 
wire  [gw-1:0]  out_pad;  // GPIO Outputs
271 17 lampret 
`ifdef GPIO_REGISTERED_IO_OUTPUTS
272 56 gorand 
reg [gw-1:0]  ext_pad_o;  // GPIO Outputs
273 17 lampret 
`endif
274 56 gorand 
wire  [gw-1:0]  extc_in;  // Muxed inputs sampled by external clock
275 
wire  [gw-1:0]  pext_clk; // External clock for posedge flops
276 
reg [gw-1:0]  pextc_sampled;  // Posedge external clock sampled inputs
277 17 lampret 
`ifdef GPIO_NO_NEGEDGE_FLOPS
278 
`else
279 56 gorand 
reg [gw-1:0]  nextc_sampled;  // Negedge external clock sampled inputs
280 17 lampret 
`endif
281 14 lampret 
 
282 56 gorand 
 
283 14 lampret 
//
284 
// All WISHBONE transfer terminations are successful except when:
285 
// a) full address decoding is enabled and address doesn't match
286 
//    any of the GPIO registers
287 
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
288 
//
289 17 lampret 
 
290 
//
291 
// WB Acknowledge
292 
//
293 
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
294 
 
295 
//
296 
// Optional registration of WB Ack
297 
//
298 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
299 
always @(posedge wb_clk_i or posedge wb_rst_i)
300 
        if (wb_rst_i)
301 
                wb_ack_o <= #1 1'b0;
302 
        else
303 34 gorand 
                wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
304 17 lampret 
`else
305 
assign wb_ack_o = wb_ack;
306 
`endif
307 
 
308 
//
309 
// WB Error
310 
//
311 14 lampret 
`ifdef GPIO_FULL_DECODE
312 
`ifdef GPIO_STRICT_32BIT_ACCESS
313 17 lampret 
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
314 14 lampret 
`else
315 17 lampret 
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
316 14 lampret 
`endif
317 
`else
318 
`ifdef GPIO_STRICT_32BIT_ACCESS
319 17 lampret 
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
320 14 lampret 
`else
321 17 lampret 
assign wb_err = 1'b0;
322 14 lampret 
`endif
323 
`endif
324 
 
325 
//
326 17 lampret 
// Optional registration of WB error
327 14 lampret 
//
328 17 lampret 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
329 
always @(posedge wb_clk_i or posedge wb_rst_i)
330 
        if (wb_rst_i)
331 
                wb_err_o <= #1 1'b0;
332 
        else
333 23 lampret 
                wb_err_o <= #1 wb_err & ~wb_err_o;
334 17 lampret 
`else
335 
assign wb_err_o = wb_err;
336 
`endif
337 14 lampret 
 
338 
//
339 
// Full address decoder
340 
//
341 
`ifdef GPIO_FULL_DECODE
342 
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
343 
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
344 
`else
345 
assign full_decoding = 1'b1;
346 
`endif
347 
 
348 
//
349 
// GPIO registers address decoder
350 
//
351 60 andreje 
`ifdef GPIO_RGPIO_OUT
352 14 lampret 
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
353 60 andreje 
`endif
354 
`ifdef GPIO_RGPIO_OE
355 14 lampret 
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
356 60 andreje 
`endif
357 
`ifdef GPIO_RGPIO_INTE
358 14 lampret 
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
359 60 andreje 
`endif
360 
`ifdef GPIO_RGPIO_PTRIG
361 14 lampret 
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
362 60 andreje 
`endif
363 
`ifdef GPIO_RGPIO_AUX
364 14 lampret 
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
365 60 andreje 
`endif
366 
`ifdef GPIO_RGPIO_CTRL
367 14 lampret 
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
368 60 andreje 
`endif
369 
`ifdef GPIO_RGPIO_INTS
370 21 lampret 
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
371 60 andreje 
`endif
372 
`ifdef GPIO_RGPIO_ECLK
373 56 gorand 
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
374 60 andreje 
`endif
375 
`ifdef GPIO_RGPIO_NEC
376 56 gorand 
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
377 60 andreje 
`endif
378 56 gorand 
 
379 
 
380 14 lampret 
//
381 
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
382 
//
383 
`ifdef GPIO_RGPIO_CTRL
384 
always @(posedge wb_clk_i or posedge wb_rst_i)
385 
        if (wb_rst_i)
386 56 gorand 
                rgpio_ctrl <= #1 2'b0;
387 14 lampret 
        else if (rgpio_ctrl_sel && wb_we_i)
388 56 gorand 
                rgpio_ctrl <= #1 wb_dat_i[1:0];
389 14 lampret 
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
390 21 lampret 
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
391 14 lampret 
`else
392 56 gorand 
assign rgpio_ctrl = 2'h01;      // RGPIO_CTRL[EN] = 1
393 14 lampret 
`endif
394 
 
395 
//
396 
// Write to RGPIO_OUT
397 
//
398 
`ifdef GPIO_RGPIO_OUT
399 
always @(posedge wb_clk_i or posedge wb_rst_i)
400 
        if (wb_rst_i)
401 
                rgpio_out <= #1 {gw{1'b0}};
402 
        else if (rgpio_out_sel && wb_we_i)
403 34 gorand 
    begin
404 
`ifdef GPIO_STRICT_32BIT_ACCESS
405 14 lampret 
                rgpio_out <= #1 wb_dat_i[gw-1:0];
406 34 gorand 
`endif
407 
 
408 
`ifdef GPIO_WB_BYTES4
409 
     if ( wb_sel_i [3] == 1'b1 )
410 
       rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
411 
     if ( wb_sel_i [2] == 1'b1 )
412 
       rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
413 
     if ( wb_sel_i [1] == 1'b1 )
414 
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
415 
     if ( wb_sel_i [0] == 1'b1 )
416 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
417 
`endif
418 
`ifdef GPIO_WB_BYTES3
419 
     if ( wb_sel_i [2] == 1'b1 )
420 
       rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
421 
     if ( wb_sel_i [1] == 1'b1 )
422 
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
423 
     if ( wb_sel_i [0] == 1'b1 )
424 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
425 
`endif
426 
`ifdef GPIO_WB_BYTES2
427 
     if ( wb_sel_i [1] == 1'b1 )
428 
       rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
429 
     if ( wb_sel_i [0] == 1'b1 )
430 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
431 
`endif
432 
`ifdef GPIO_WB_BYTES1
433 
     if ( wb_sel_i [0] == 1'b1 )
434 
       rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
435 
`endif
436 
   end
437 
 
438 14 lampret 
`else
439 17 lampret 
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
440 14 lampret 
`endif
441 
 
442 
//
443 60 andreje 
// Write to RGPIO_OE.
444 14 lampret 
//
445 
`ifdef GPIO_RGPIO_OE
446 36 gorand 
always @(posedge wb_clk_i or posedge wb_rst_i)
447 
        if (wb_rst_i)
448 14 lampret 
                rgpio_oe <= #1 {gw{1'b0}};
449 36 gorand 
        else if (rgpio_oe_sel && wb_we_i)
450 34 gorand 
  begin
451 
`ifdef GPIO_STRICT_32BIT_ACCESS
452 60 andreje 
                rgpio_oe <= #1 wb_dat_i[gw-1:0];
453 34 gorand 
`endif
454 
 
455 
`ifdef GPIO_WB_BYTES4
456 36 gorand 
     if ( wb_sel_i [3] == 1'b1 )
457 60 andreje 
       rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
458 36 gorand 
     if ( wb_sel_i [2] == 1'b1 )
459 60 andreje 
       rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ;
460 36 gorand 
     if ( wb_sel_i [1] == 1'b1 )
461 60 andreje 
       rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
462 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
463 60 andreje 
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
464 34 gorand 
`endif
465 
`ifdef GPIO_WB_BYTES3
466 36 gorand 
     if ( wb_sel_i [2] == 1'b1 )
467 60 andreje 
       rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
468 36 gorand 
     if ( wb_sel_i [1] == 1'b1 )
469 60 andreje 
       rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
470 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
471 60 andreje 
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
472 34 gorand 
`endif
473 
`ifdef GPIO_WB_BYTES2
474 36 gorand 
     if ( wb_sel_i [1] == 1'b1 )
475 60 andreje 
       rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
476 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
477 60 andreje 
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
478 34 gorand 
`endif
479 
`ifdef GPIO_WB_BYTES1
480 36 gorand 
     if ( wb_sel_i [0] == 1'b1 )
481 60 andreje 
       rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
482 34 gorand 
`endif
483 
   end
484 
 
485 14 lampret 
`else
486 60 andreje 
assign rgpio_oe = `GPIO_DEF_RGPIO_OE;   // RGPIO_OE = 0x0
487 14 lampret 
`endif
488 
 
489 
//
490 
// Write to RGPIO_INTE
491 
//
492 
`ifdef GPIO_RGPIO_INTE
493 
always @(posedge wb_clk_i or posedge wb_rst_i)
494 
        if (wb_rst_i)
495 
                rgpio_inte <= #1 {gw{1'b0}};
496 
        else if (rgpio_inte_sel && wb_we_i)
497 34 gorand 
  begin
498 
`ifdef GPIO_STRICT_32BIT_ACCESS
499 14 lampret 
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
500 34 gorand 
`endif
501 
 
502 
`ifdef GPIO_WB_BYTES4
503 
     if ( wb_sel_i [3] == 1'b1 )
504 
       rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
505 
     if ( wb_sel_i [2] == 1'b1 )
506 
       rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
507 
     if ( wb_sel_i [1] == 1'b1 )
508 
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
509 
     if ( wb_sel_i [0] == 1'b1 )
510 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
511 
`endif
512 
`ifdef GPIO_WB_BYTES3
513 
     if ( wb_sel_i [2] == 1'b1 )
514 
       rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
515 
     if ( wb_sel_i [1] == 1'b1 )
516 
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
517 
     if ( wb_sel_i [0] == 1'b1 )
518 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
519 
`endif
520 
`ifdef GPIO_WB_BYTES2
521 
     if ( wb_sel_i [1] == 1'b1 )
522 
       rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
523 
     if ( wb_sel_i [0] == 1'b1 )
524 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
525 
`endif
526 
`ifdef GPIO_WB_BYTES1
527 
     if ( wb_sel_i [0] == 1'b1 )
528 
       rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
529 
`endif
530 
   end
531 
 
532 
 
533 14 lampret 
`else
534 60 andreje 
assign rgpio_inte = `GPIO_DEF_RGPIO_INTE;       // RGPIO_INTE = 0x0
535 14 lampret 
`endif
536 
 
537 
//
538 
// Write to RGPIO_PTRIG
539 
//
540 
`ifdef GPIO_RGPIO_PTRIG
541 
always @(posedge wb_clk_i or posedge wb_rst_i)
542 
        if (wb_rst_i)
543 
                rgpio_ptrig <= #1 {gw{1'b0}};
544 
        else if (rgpio_ptrig_sel && wb_we_i)
545 34 gorand 
  begin
546 
`ifdef GPIO_STRICT_32BIT_ACCESS
547 14 lampret 
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
548 34 gorand 
`endif
549 
 
550 
`ifdef GPIO_WB_BYTES4
551 
     if ( wb_sel_i [3] == 1'b1 )
552 
       rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
553 
     if ( wb_sel_i [2] == 1'b1 )
554 
       rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
555 
     if ( wb_sel_i [1] == 1'b1 )
556 
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
557 
     if ( wb_sel_i [0] == 1'b1 )
558 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
559 
`endif
560 
`ifdef GPIO_WB_BYTES3
561 
     if ( wb_sel_i [2] == 1'b1 )
562 
       rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
563 
     if ( wb_sel_i [1] == 1'b1 )
564 
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
565 
     if ( wb_sel_i [0] == 1'b1 )
566 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
567 
`endif
568 
`ifdef GPIO_WB_BYTES2
569 
     if ( wb_sel_i [1] == 1'b1 )
570 
       rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
571 
     if ( wb_sel_i [0] == 1'b1 )
572 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
573 
`endif
574 
`ifdef GPIO_WB_BYTES1
575 
     if ( wb_sel_i [0] == 1'b1 )
576 
       rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
577 
`endif
578 
   end
579 
 
580 14 lampret 
`else
581 60 andreje 
assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG;     // RGPIO_PTRIG = 0x0
582 14 lampret 
`endif
583 
 
584 
//
585 
// Write to RGPIO_AUX
586 
//
587 
`ifdef GPIO_RGPIO_AUX
588 
always @(posedge wb_clk_i or posedge wb_rst_i)
589 
        if (wb_rst_i)
590 
                rgpio_aux <= #1 {gw{1'b0}};
591 
        else if (rgpio_aux_sel && wb_we_i)
592 34 gorand 
  begin
593 
`ifdef GPIO_STRICT_32BIT_ACCESS
594 14 lampret 
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
595 34 gorand 
`endif
596 
 
597 
`ifdef GPIO_WB_BYTES4
598 
     if ( wb_sel_i [3] == 1'b1 )
599 
       rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
600 
     if ( wb_sel_i [2] == 1'b1 )
601 
       rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
602 
     if ( wb_sel_i [1] == 1'b1 )
603 
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
604 
     if ( wb_sel_i [0] == 1'b1 )
605 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
606 
`endif
607 
`ifdef GPIO_WB_BYTES3
608 
     if ( wb_sel_i [2] == 1'b1 )
609 
       rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
610 
     if ( wb_sel_i [1] == 1'b1 )
611 
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
612 
     if ( wb_sel_i [0] == 1'b1 )
613 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
614 
`endif
615 
`ifdef GPIO_WB_BYTES2
616 
     if ( wb_sel_i [1] == 1'b1 )
617 
       rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
618 
     if ( wb_sel_i [0] == 1'b1 )
619 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
620 
`endif
621 
`ifdef GPIO_WB_BYTES1
622 
     if ( wb_sel_i [0] == 1'b1 )
623 
       rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
624 
`endif
625 
   end
626 
 
627 14 lampret 
`else
628 60 andreje 
assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0
629 14 lampret 
`endif
630 
 
631 56 gorand 
 
632 14 lampret 
//
633 56 gorand 
// Write to RGPIO_ECLK
634 
//
635 
`ifdef GPIO_RGPIO_ECLK
636 
always @(posedge wb_clk_i or posedge wb_rst_i)
637 
        if (wb_rst_i)
638 
                rgpio_eclk <= #1 {gw{1'b0}};
639 
        else if (rgpio_eclk_sel && wb_we_i)
640 
  begin
641 
`ifdef GPIO_STRICT_32BIT_ACCESS
642 
                rgpio_eclk <= #1 wb_dat_i[gw-1:0];
643 
`endif
644 
 
645 
`ifdef GPIO_WB_BYTES4
646 
     if ( wb_sel_i [3] == 1'b1 )
647 
       rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
648 
     if ( wb_sel_i [2] == 1'b1 )
649 
       rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ;
650 
     if ( wb_sel_i [1] == 1'b1 )
651 
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
652 
     if ( wb_sel_i [0] == 1'b1 )
653 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
654 
`endif
655 
`ifdef GPIO_WB_BYTES3
656 
     if ( wb_sel_i [2] == 1'b1 )
657 
       rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
658 
     if ( wb_sel_i [1] == 1'b1 )
659 
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
660 
     if ( wb_sel_i [0] == 1'b1 )
661 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
662 
`endif
663 
`ifdef GPIO_WB_BYTES2
664 
     if ( wb_sel_i [1] == 1'b1 )
665 
       rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
666 
     if ( wb_sel_i [0] == 1'b1 )
667 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
668 
`endif
669 
`ifdef GPIO_WB_BYTES1
670 
     if ( wb_sel_i [0] == 1'b1 )
671 
       rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
672 
`endif
673 
   end
674 
 
675 
 
676 
`else
677 60 andreje 
assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK;       // RGPIO_ECLK = 0x0
678 56 gorand 
`endif
679 
 
680 
 
681 
 
682 
//
683 
// Write to RGPIO_NEC
684 
//
685 
`ifdef GPIO_RGPIO_NEC
686 
always @(posedge wb_clk_i or posedge wb_rst_i)
687 
        if (wb_rst_i)
688 
                rgpio_nec <= #1 {gw{1'b0}};
689 
        else if (rgpio_nec_sel && wb_we_i)
690 
  begin
691 
`ifdef GPIO_STRICT_32BIT_ACCESS
692 
                rgpio_nec <= #1 wb_dat_i[gw-1:0];
693 
`endif
694 
 
695 
`ifdef GPIO_WB_BYTES4
696 
     if ( wb_sel_i [3] == 1'b1 )
697 
       rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
698 
     if ( wb_sel_i [2] == 1'b1 )
699 
       rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ;
700 
     if ( wb_sel_i [1] == 1'b1 )
701 
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
702 
     if ( wb_sel_i [0] == 1'b1 )
703 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
704 
`endif
705 
`ifdef GPIO_WB_BYTES3
706 
     if ( wb_sel_i [2] == 1'b1 )
707 
       rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
708 
     if ( wb_sel_i [1] == 1'b1 )
709 
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
710 
     if ( wb_sel_i [0] == 1'b1 )
711 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
712 
`endif
713 
`ifdef GPIO_WB_BYTES2
714 
     if ( wb_sel_i [1] == 1'b1 )
715 
       rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
716 
     if ( wb_sel_i [0] == 1'b1 )
717 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
718 
`endif
719 
`ifdef GPIO_WB_BYTES1
720 
     if ( wb_sel_i [0] == 1'b1 )
721 
       rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
722 
`endif
723 
   end
724 
 
725 
 
726 
`else
727 60 andreje 
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
728 56 gorand 
`endif
729 
 
730 
 
731 
//
732 14 lampret 
// Latch into RGPIO_IN
733 
//
734 
`ifdef GPIO_RGPIO_IN
735 17 lampret 
always @(posedge wb_clk_i or posedge wb_rst_i)
736 14 lampret 
        if (wb_rst_i)
737 
                rgpio_in <= #1 {gw{1'b0}};
738 
        else
739 17 lampret 
                rgpio_in <= #1 in_muxed;
740 14 lampret 
`else
741 17 lampret 
assign rgpio_in = in_muxed;
742 14 lampret 
`endif
743 
 
744 
//
745 17 lampret 
// Mux inputs directly from input pads with inputs sampled by external clock
746 14 lampret 
//
747 56 gorand 
//assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
748 17 lampret 
 
749 56 gorand 
 
750 
`ifdef GPIO_LINES32
751 
assign  in_muxed [31] = rgpio_eclk [31] ? extc_in[31] : ext_pad_i[31] ;
752 
`endif
753 
 
754 
`ifdef GPIO_LINES31
755 
assign  in_muxed [30] = rgpio_eclk [30] ? extc_in[30] : ext_pad_i[30] ;
756 
`endif
757 
 
758 
`ifdef GPIO_LINES30
759 
assign  in_muxed [29] = rgpio_eclk [29] ? extc_in[29] : ext_pad_i[29] ;
760 
`endif
761 
 
762 
`ifdef GPIO_LINES29
763 
assign  in_muxed [28] = rgpio_eclk [28] ? extc_in[28] : ext_pad_i[28] ;
764 
`endif
765 
 
766 
`ifdef GPIO_LINES28
767 
assign  in_muxed [27] = rgpio_eclk [27] ? extc_in[27] : ext_pad_i[27] ;
768 
`endif
769 
 
770 
`ifdef GPIO_LINES27
771 
assign  in_muxed [26] = rgpio_eclk [26] ? extc_in[26] : ext_pad_i[26] ;
772 
`endif
773 
 
774 
`ifdef GPIO_LINES26
775 
assign  in_muxed [25] = rgpio_eclk [25] ? extc_in[25] : ext_pad_i[25] ;
776 
`endif
777 
 
778 
`ifdef GPIO_LINES25
779 
assign  in_muxed [24] = rgpio_eclk [24] ? extc_in[24] : ext_pad_i[24] ;
780 
`endif
781 
 
782 
`ifdef GPIO_LINES24
783 
assign  in_muxed [23] = rgpio_eclk [23] ? extc_in[23] : ext_pad_i[23] ;
784 
`endif
785 
 
786 
`ifdef GPIO_LINES23
787 
assign  in_muxed [22] = rgpio_eclk [22] ? extc_in[22] : ext_pad_i[22] ;
788 
`endif
789 
 
790 
`ifdef GPIO_LINES22
791 
assign  in_muxed [21] = rgpio_eclk [21] ? extc_in[21] : ext_pad_i[21] ;
792 
`endif
793 
 
794 
`ifdef GPIO_LINES21
795 
assign  in_muxed [20] = rgpio_eclk [20] ? extc_in[20] : ext_pad_i[20] ;
796 
`endif
797 
 
798 
`ifdef GPIO_LINES20
799 
assign  in_muxed [19] = rgpio_eclk [19] ? extc_in[19] : ext_pad_i[19] ;
800 
`endif
801 
 
802 
`ifdef GPIO_LINES19
803 
assign  in_muxed [18] = rgpio_eclk [18] ? extc_in[18] : ext_pad_i[18] ;
804 
`endif
805 
 
806 
`ifdef GPIO_LINES18
807 
assign  in_muxed [17] = rgpio_eclk [17] ? extc_in[17] : ext_pad_i[17] ;
808 
`endif
809 
 
810 
`ifdef GPIO_LINES17
811 
assign  in_muxed [16] = rgpio_eclk [16] ? extc_in[16] : ext_pad_i[16] ;
812 
`endif
813 
 
814 
`ifdef GPIO_LINES16
815 
assign  in_muxed [15] = rgpio_eclk [15] ? extc_in[15] : ext_pad_i[15] ;
816 
`endif
817 
 
818 
`ifdef GPIO_LINES15
819 
assign  in_muxed [14] = rgpio_eclk [14] ? extc_in[14] : ext_pad_i[14] ;
820 
`endif
821 
 
822 
`ifdef GPIO_LINES14
823 
assign  in_muxed [13] = rgpio_eclk [13] ? extc_in[13] : ext_pad_i[13] ;
824 
`endif
825 
 
826 
`ifdef GPIO_LINES13
827 
assign  in_muxed [12] = rgpio_eclk [12] ? extc_in[12] : ext_pad_i[12] ;
828 
`endif
829 
 
830 
`ifdef GPIO_LINES12
831 
assign  in_muxed [11] = rgpio_eclk [11] ? extc_in[11] : ext_pad_i[11] ;
832 
`endif
833 
 
834 
`ifdef GPIO_LINES11
835 
assign  in_muxed [10] = rgpio_eclk [10] ? extc_in[10] : ext_pad_i[10] ;
836 
`endif
837 
 
838 
`ifdef GPIO_LINES10
839 
assign  in_muxed [9] = rgpio_eclk [9] ? extc_in[9] : ext_pad_i[9] ;
840 
`endif
841 
 
842 
`ifdef GPIO_LINES9
843 
assign  in_muxed [8] = rgpio_eclk [8] ? extc_in[8] : ext_pad_i[8] ;
844 
`endif
845 
 
846 
`ifdef GPIO_LINES8
847 
assign  in_muxed [7] = rgpio_eclk [7] ? extc_in[7] : ext_pad_i[7] ;
848 
`endif
849 
 
850 
`ifdef GPIO_LINES7
851 
assign  in_muxed [6] = rgpio_eclk [6] ? extc_in[6] : ext_pad_i[6] ;
852 
`endif
853 
 
854 
`ifdef GPIO_LINES6
855 
assign  in_muxed [5] = rgpio_eclk [5] ? extc_in[5] : ext_pad_i[5] ;
856 
`endif
857 
 
858 
`ifdef GPIO_LINES5
859 
assign  in_muxed [4] = rgpio_eclk [4] ? extc_in[4] : ext_pad_i[4] ;
860 
`endif
861 
 
862 
`ifdef GPIO_LINES4
863 
assign  in_muxed [3] = rgpio_eclk [3] ? extc_in[3] : ext_pad_i[3] ;
864 
`endif
865 
 
866 
`ifdef GPIO_LINES3
867 
assign  in_muxed [2] = rgpio_eclk [2] ? extc_in[2] : ext_pad_i[2] ;
868 
`endif
869 
 
870 
`ifdef GPIO_LINES2
871 
assign  in_muxed [1] = rgpio_eclk [1] ? extc_in[1] : ext_pad_i[1] ;
872 
`endif
873 
 
874 
`ifdef GPIO_LINES1
875 
assign  in_muxed [0] = rgpio_eclk [0] ? extc_in[0] : ext_pad_i[0] ;
876 
`endif
877 
 
878 
 
879 17 lampret 
//
880 
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
881 
// If negedge flops are allowed, pext_clk only clocks posedge flops.
882 
//
883 
`ifdef GPIO_NO_NEGEDGE_FLOPS
884 29 lampret 
`ifdef GPIO_NO_CLKPAD_LOGIC
885 56 gorand 
assign pext_clk = {gw{clk_pad_i}};
886 29 lampret 
`else
887 56 gorand 
 
888 
//assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
889 
 
890 
 
891 
`ifdef GPIO_LINES32
892 
assign  pext_clk [31] = rgpio_nec [31] ? ~clk_pad_i : clk_pad_i ;
893 29 lampret 
`endif
894 56 gorand 
 
895 
`ifdef GPIO_LINES31
896 
assign  pext_clk [30] = rgpio_nec [30] ? ~clk_pad_i : clk_pad_i ;
897 
`endif
898 
 
899 
`ifdef GPIO_LINES30
900 
assign  pext_clk [29] = rgpio_nec [29] ? ~clk_pad_i : clk_pad_i ;
901 
`endif
902 
 
903 
`ifdef GPIO_LINES29
904 
assign  pext_clk [28] = rgpio_nec [28] ? ~clk_pad_i : clk_pad_i ;
905 
`endif
906 
 
907 
`ifdef GPIO_LINES28
908 
assign  pext_clk [27] = rgpio_nec [27] ? ~clk_pad_i : clk_pad_i ;
909 
`endif
910 
 
911 
`ifdef GPIO_LINES27
912 
assign  pext_clk [26] = rgpio_nec [26] ? ~clk_pad_i : clk_pad_i ;
913 
`endif
914 
 
915 
`ifdef GPIO_LINES26
916 
assign  pext_clk [25] = rgpio_nec [25] ? ~clk_pad_i : clk_pad_i ;
917 
`endif
918 
 
919 
`ifdef GPIO_LINES25
920 
assign  pext_clk [24] = rgpio_nec [24] ? ~clk_pad_i : clk_pad_i ;
921 
`endif
922 
 
923 
`ifdef GPIO_LINES24
924 
assign  pext_clk [23] = rgpio_nec [23] ? ~clk_pad_i : clk_pad_i ;
925 
`endif
926 
 
927 
`ifdef GPIO_LINES23
928 
assign  pext_clk [22] = rgpio_nec [22] ? ~clk_pad_i : clk_pad_i ;
929 
`endif
930 
 
931 
`ifdef GPIO_LINES22
932 
assign  pext_clk [21] = rgpio_nec [21] ? ~clk_pad_i : clk_pad_i ;
933 
`endif
934 
 
935 
`ifdef GPIO_LINES21
936 
assign  pext_clk [20] = rgpio_nec [20] ? ~clk_pad_i : clk_pad_i ;
937 
`endif
938 
 
939 
`ifdef GPIO_LINES20
940 
assign  pext_clk [19] = rgpio_nec [19] ? ~clk_pad_i : clk_pad_i ;
941 
`endif
942 
 
943 
`ifdef GPIO_LINES19
944 
assign  pext_clk [18] = rgpio_nec [18] ? ~clk_pad_i : clk_pad_i ;
945 
`endif
946 
 
947 
`ifdef GPIO_LINES18
948 
assign  pext_clk [17] = rgpio_nec [17] ? ~clk_pad_i : clk_pad_i ;
949 
`endif
950 
 
951 
`ifdef GPIO_LINES17
952 
assign  pext_clk [16] = rgpio_nec [16] ? ~clk_pad_i : clk_pad_i ;
953 
`endif
954 
 
955 
`ifdef GPIO_LINES16
956 
assign  pext_clk [15] = rgpio_nec [15] ? ~clk_pad_i : clk_pad_i ;
957 
`endif
958 
 
959 
`ifdef GPIO_LINES15
960 
assign  pext_clk [14] = rgpio_nec [14] ? ~clk_pad_i : clk_pad_i ;
961 
`endif
962 
 
963 
`ifdef GPIO_LINES14
964 
assign  pext_clk [13] = rgpio_nec [13] ? ~clk_pad_i : clk_pad_i ;
965 
`endif
966 
 
967 
`ifdef GPIO_LINES13
968 
assign  pext_clk [12] = rgpio_nec [12] ? ~clk_pad_i : clk_pad_i ;
969 
`endif
970 
 
971 
`ifdef GPIO_LINES12
972 
assign  pext_clk [11] = rgpio_nec [11] ? ~clk_pad_i : clk_pad_i ;
973 
`endif
974 
 
975 
`ifdef GPIO_LINES11
976 
assign  pext_clk [10] = rgpio_nec [10] ? ~clk_pad_i : clk_pad_i ;
977 
`endif
978 
 
979 
`ifdef GPIO_LINES10
980 
assign  pext_clk [9] = rgpio_nec [9] ? ~clk_pad_i : clk_pad_i ;
981 
`endif
982 
 
983 
`ifdef GPIO_LINES9
984 
assign  pext_clk [8] = rgpio_nec [8] ? ~clk_pad_i : clk_pad_i ;
985 
`endif
986 
 
987 
`ifdef GPIO_LINES8
988 
assign  pext_clk [7] = rgpio_nec [7] ? ~clk_pad_i : clk_pad_i ;
989 
`endif
990 
 
991 
`ifdef GPIO_LINES7
992 
assign  pext_clk [6] = rgpio_nec [6] ? ~clk_pad_i : clk_pad_i ;
993 
`endif
994 
 
995 
`ifdef GPIO_LINES6
996 
assign  pext_clk [5] = rgpio_nec [5] ? ~clk_pad_i : clk_pad_i ;
997 
`endif
998 
 
999 
`ifdef GPIO_LINES5
1000 
assign  pext_clk [4] = rgpio_nec [4] ? ~clk_pad_i : clk_pad_i ;
1001 
`endif
1002 
 
1003 
`ifdef GPIO_LINES4
1004 
assign  pext_clk [3] = rgpio_nec [3] ? ~clk_pad_i : clk_pad_i ;
1005 
`endif
1006 
 
1007 
`ifdef GPIO_LINES3
1008 
assign  pext_clk [2] = rgpio_nec [2] ? ~clk_pad_i : clk_pad_i ;
1009 
`endif
1010 
 
1011 
`ifdef GPIO_LINES2
1012 
assign  pext_clk [1] = rgpio_nec [1] ? ~clk_pad_i : clk_pad_i ;
1013 
`endif
1014 
 
1015 
`ifdef GPIO_LINES1
1016 
assign  pext_clk [0] = rgpio_nec [0] ? ~clk_pad_i : clk_pad_i ;
1017 
`endif
1018 
 
1019 
`endif
1020 17 lampret 
`else
1021 56 gorand 
assign pext_clk = {gw{clk_pad_i}};
1022 17 lampret 
`endif
1023 
 
1024 56 gorand 
 
1025 17 lampret 
//
1026 
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
1027 
//
1028 
`ifdef GPIO_NO_NEGEDGE_FLOPS
1029 
assign extc_in = pextc_sampled;
1030 
`else
1031 56 gorand 
//assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
1032 
 
1033 
 
1034 
`ifdef GPIO_LINES32
1035 
assign  extc_in [31] = rgpio_nec [31] ? nextc_sampled[31] : pextc_sampled[31] ;
1036 17 lampret 
`endif
1037 
 
1038 56 gorand 
`ifdef GPIO_LINES31
1039 
assign  extc_in [30] = rgpio_nec [30] ? nextc_sampled[30] : pextc_sampled[30] ;
1040 
`endif
1041 
 
1042 
`ifdef GPIO_LINES30
1043 
assign  extc_in [29] = rgpio_nec [29] ? nextc_sampled[29] : pextc_sampled[29] ;
1044 
`endif
1045 
 
1046 
`ifdef GPIO_LINES29
1047 
assign  extc_in [28] = rgpio_nec [28] ? nextc_sampled[28] : pextc_sampled[28] ;
1048 
`endif
1049 
 
1050 
`ifdef GPIO_LINES28
1051 
assign  extc_in [27] = rgpio_nec [27] ? nextc_sampled[27] : pextc_sampled[27] ;
1052 
`endif
1053 
 
1054 
`ifdef GPIO_LINES27
1055 
assign  extc_in [26] = rgpio_nec [26] ? nextc_sampled[26] : pextc_sampled[26] ;
1056 
`endif
1057 
 
1058 
`ifdef GPIO_LINES26
1059 
assign  extc_in [25] = rgpio_nec [25] ? nextc_sampled[25] : pextc_sampled[25] ;
1060 
`endif
1061 
 
1062 
`ifdef GPIO_LINES25
1063 
assign  extc_in [24] = rgpio_nec [24] ? nextc_sampled[24] : pextc_sampled[24] ;
1064 
`endif
1065 
 
1066 
`ifdef GPIO_LINES24
1067 
assign  extc_in [23] = rgpio_nec [23] ? nextc_sampled[23] : pextc_sampled[23] ;
1068 
`endif
1069 
 
1070 
`ifdef GPIO_LINES23
1071 
assign  extc_in [22] = rgpio_nec [22] ? nextc_sampled[22] : pextc_sampled[22] ;
1072 
`endif
1073 
 
1074 
`ifdef GPIO_LINES22
1075 
assign  extc_in [21] = rgpio_nec [21] ? nextc_sampled[21] : pextc_sampled[21] ;
1076 
`endif
1077 
 
1078 
`ifdef GPIO_LINES21
1079 
assign  extc_in [20] = rgpio_nec [20] ? nextc_sampled[20] : pextc_sampled[20] ;
1080 
`endif
1081 
 
1082 
`ifdef GPIO_LINES20
1083 
assign  extc_in [19] = rgpio_nec [19] ? nextc_sampled[19] : pextc_sampled[19] ;
1084 
`endif
1085 
 
1086 
`ifdef GPIO_LINES19
1087 
assign  extc_in [18] = rgpio_nec [18] ? nextc_sampled[18] : pextc_sampled[18] ;
1088 
`endif
1089 
 
1090 
`ifdef GPIO_LINES18
1091 
assign  extc_in [17] = rgpio_nec [17] ? nextc_sampled[17] : pextc_sampled[17] ;
1092 
`endif
1093 
 
1094 
`ifdef GPIO_LINES17
1095 
assign  extc_in [16] = rgpio_nec [16] ? nextc_sampled[16] : pextc_sampled[16] ;
1096 
`endif
1097 
 
1098 
`ifdef GPIO_LINES16
1099 
assign  extc_in [15] = rgpio_nec [15] ? nextc_sampled[15] : pextc_sampled[15] ;
1100 
`endif
1101 
 
1102 
`ifdef GPIO_LINES15
1103 
assign  extc_in [14] = rgpio_nec [14] ? nextc_sampled[14] : pextc_sampled[14] ;
1104 
`endif
1105 
 
1106 
`ifdef GPIO_LINES14
1107 
assign  extc_in [13] = rgpio_nec [13] ? nextc_sampled[13] : pextc_sampled[13] ;
1108 
`endif
1109 
 
1110 
`ifdef GPIO_LINES13
1111 
assign  extc_in [12] = rgpio_nec [12] ? nextc_sampled[12] : pextc_sampled[12] ;
1112 
`endif
1113 
 
1114 
`ifdef GPIO_LINES12
1115 
assign  extc_in [11] = rgpio_nec [11] ? nextc_sampled[11] : pextc_sampled[11] ;
1116 
`endif
1117 
 
1118 
`ifdef GPIO_LINES11
1119 
assign  extc_in [10] = rgpio_nec [10] ? nextc_sampled[10] : pextc_sampled[10] ;
1120 
`endif
1121 
 
1122 
`ifdef GPIO_LINES10
1123 
assign  extc_in [9] = rgpio_nec [9] ? nextc_sampled[9] : pextc_sampled[9] ;
1124 
`endif
1125 
 
1126 
`ifdef GPIO_LINES9
1127 
assign  extc_in [8] = rgpio_nec [8] ? nextc_sampled[8] : pextc_sampled[8] ;
1128 
`endif
1129 
 
1130 
`ifdef GPIO_LINES8
1131 
assign  extc_in [7] = rgpio_nec [7] ? nextc_sampled[7] : pextc_sampled[7] ;
1132 
`endif
1133 
 
1134 
`ifdef GPIO_LINES7
1135 
assign  extc_in [6] = rgpio_nec [6] ? nextc_sampled[6] : pextc_sampled[6] ;
1136 
`endif
1137 
 
1138 
`ifdef GPIO_LINES6
1139 
assign  extc_in [5] = rgpio_nec [5] ? nextc_sampled[5] : pextc_sampled[5] ;
1140 
`endif
1141 
 
1142 
`ifdef GPIO_LINES5
1143 
assign  extc_in [4] = rgpio_nec [4] ? nextc_sampled[4] : pextc_sampled[4] ;
1144 
`endif
1145 
 
1146 
`ifdef GPIO_LINES4
1147 
assign  extc_in [3] = rgpio_nec [3] ? nextc_sampled[3] : pextc_sampled[3] ;
1148 
`endif
1149 
 
1150 
`ifdef GPIO_LINES3
1151 
assign  extc_in [2] = rgpio_nec [2] ? nextc_sampled[2] : pextc_sampled[2] ;
1152 
`endif
1153 
 
1154 
`ifdef GPIO_LINES2
1155 
assign  extc_in [1] = rgpio_nec [1] ? nextc_sampled[1] : pextc_sampled[1] ;
1156 
`endif
1157 
 
1158 
`ifdef GPIO_LINES1
1159 
assign  extc_in [0] = rgpio_nec [0] ? nextc_sampled[0] : pextc_sampled[0] ;
1160 
`endif
1161 
 
1162 
`endif
1163 
 
1164 17 lampret 
//
1165 
// Latch using posedge external clock
1166 
//
1167 56 gorand 
 
1168 
`ifdef GPIO_LINES32
1169 
always @(posedge pext_clk[31] or posedge wb_rst_i)
1170 17 lampret 
        if (wb_rst_i)
1171 56 gorand 
                pextc_sampled[31] <= #1 1'b0;
1172 17 lampret 
        else
1173 56 gorand 
                pextc_sampled[31] <= #1 ext_pad_i[31];
1174 
`endif
1175 17 lampret 
 
1176 56 gorand 
`ifdef GPIO_LINES31
1177 
always @(posedge pext_clk[30] or posedge wb_rst_i)
1178 
  if (wb_rst_i)
1179 
    pextc_sampled[30] <= #1 1'b0;
1180 
  else
1181 
    pextc_sampled[30] <= #1 ext_pad_i[30];
1182 
`endif
1183 
 
1184 
`ifdef GPIO_LINES30
1185 
always @(posedge pext_clk[29] or posedge wb_rst_i)
1186 
  if (wb_rst_i)
1187 
    pextc_sampled[29] <= #1 1'b0;
1188 
  else
1189 
    pextc_sampled[29] <= #1 ext_pad_i[29];
1190 
`endif
1191 
 
1192 
`ifdef GPIO_LINES29
1193 
always @(posedge pext_clk[28] or posedge wb_rst_i)
1194 
  if (wb_rst_i)
1195 
    pextc_sampled[28] <= #1 1'b0;
1196 
  else
1197 
    pextc_sampled[28] <= #1 ext_pad_i[28];
1198 
`endif
1199 
 
1200 
`ifdef GPIO_LINES28
1201 
always @(posedge pext_clk[27] or posedge wb_rst_i)
1202 
  if (wb_rst_i)
1203 
    pextc_sampled[27] <= #1 1'b0;
1204 
  else
1205 
    pextc_sampled[27] <= #1 ext_pad_i[27];
1206 
`endif
1207 
 
1208 
`ifdef GPIO_LINES27
1209 
always @(posedge pext_clk[26] or posedge wb_rst_i)
1210 
  if (wb_rst_i)
1211 
    pextc_sampled[26] <= #1 1'b0;
1212 
  else
1213 
    pextc_sampled[26] <= #1 ext_pad_i[26];
1214 
`endif
1215 
 
1216 
`ifdef GPIO_LINES26
1217 
always @(posedge pext_clk[25] or posedge wb_rst_i)
1218 
  if (wb_rst_i)
1219 
    pextc_sampled[25] <= #1 1'b0;
1220 
  else
1221 
    pextc_sampled[25] <= #1 ext_pad_i[25];
1222 
`endif
1223 
 
1224 
`ifdef GPIO_LINES25
1225 
always @(posedge pext_clk[24] or posedge wb_rst_i)
1226 
  if (wb_rst_i)
1227 
    pextc_sampled[24] <= #1 1'b0;
1228 
  else
1229 
    pextc_sampled[24] <= #1 ext_pad_i[24];
1230 
`endif
1231 
 
1232 
`ifdef GPIO_LINES24
1233 
always @(posedge pext_clk[23] or posedge wb_rst_i)
1234 
  if (wb_rst_i)
1235 
    pextc_sampled[23] <= #1 1'b0;
1236 
  else
1237 
    pextc_sampled[23] <= #1 ext_pad_i[23];
1238 
`endif
1239 
 
1240 
`ifdef GPIO_LINES23
1241 
always @(posedge pext_clk[22] or posedge wb_rst_i)
1242 
  if (wb_rst_i)
1243 
    pextc_sampled[22] <= #1 1'b0;
1244 
  else
1245 
    pextc_sampled[22] <= #1 ext_pad_i[22];
1246 
`endif
1247 
 
1248 
`ifdef GPIO_LINES22
1249 
always @(posedge pext_clk[21] or posedge wb_rst_i)
1250 
  if (wb_rst_i)
1251 
    pextc_sampled[21] <= #1 1'b0;
1252 
  else
1253 
    pextc_sampled[21] <= #1 ext_pad_i[21];
1254 
`endif
1255 
 
1256 
`ifdef GPIO_LINES21
1257 
always @(posedge pext_clk[20] or posedge wb_rst_i)
1258 
  if (wb_rst_i)
1259 
    pextc_sampled[20] <= #1 1'b0;
1260 
  else
1261 
    pextc_sampled[20] <= #1 ext_pad_i[20];
1262 
`endif
1263 
 
1264 
`ifdef GPIO_LINES20
1265 
always @(posedge pext_clk[19] or posedge wb_rst_i)
1266 
  if (wb_rst_i)
1267 
    pextc_sampled[19] <= #1 1'b0;
1268 
  else
1269 
    pextc_sampled[19] <= #1 ext_pad_i[19];
1270 
`endif
1271 
 
1272 
`ifdef GPIO_LINES19
1273 
always @(posedge pext_clk[18] or posedge wb_rst_i)
1274 
  if (wb_rst_i)
1275 
    pextc_sampled[18] <= #1 1'b0;
1276 
  else
1277 
    pextc_sampled[18] <= #1 ext_pad_i[18];
1278 
`endif
1279 
 
1280 
`ifdef GPIO_LINES18
1281 
always @(posedge pext_clk[17] or posedge wb_rst_i)
1282 
  if (wb_rst_i)
1283 
    pextc_sampled[17] <= #1 1'b0;
1284 
  else
1285 
    pextc_sampled[17] <= #1 ext_pad_i[17];
1286 
`endif
1287 
 
1288 
`ifdef GPIO_LINES17
1289 
always @(posedge pext_clk[16] or posedge wb_rst_i)
1290 
  if (wb_rst_i)
1291 
    pextc_sampled[16] <= #1 1'b0;
1292 
  else
1293 
    pextc_sampled[16] <= #1 ext_pad_i[16];
1294 
`endif
1295 
 
1296 
`ifdef GPIO_LINES16
1297 
always @(posedge pext_clk[15] or posedge wb_rst_i)
1298 
  if (wb_rst_i)
1299 
    pextc_sampled[15] <= #1 1'b0;
1300 
  else
1301 
    pextc_sampled[15] <= #1 ext_pad_i[15];
1302 
`endif
1303 
 
1304 
`ifdef GPIO_LINES15
1305 
always @(posedge pext_clk[14] or posedge wb_rst_i)
1306 
  if (wb_rst_i)
1307 
    pextc_sampled[14] <= #1 1'b0;
1308 
  else
1309 
    pextc_sampled[14] <= #1 ext_pad_i[14];
1310 
`endif
1311 
 
1312 
`ifdef GPIO_LINES14
1313 
always @(posedge pext_clk[13] or posedge wb_rst_i)
1314 
  if (wb_rst_i)
1315 
    pextc_sampled[13] <= #1 1'b0;
1316 
  else
1317 
    pextc_sampled[13] <= #1 ext_pad_i[13];
1318 
`endif
1319 
 
1320 
`ifdef GPIO_LINES13
1321 
always @(posedge pext_clk[12] or posedge wb_rst_i)
1322 
  if (wb_rst_i)
1323 
    pextc_sampled[12] <= #1 1'b0;
1324 
  else
1325 
    pextc_sampled[12] <= #1 ext_pad_i[12];
1326 
`endif
1327 
 
1328 
`ifdef GPIO_LINES12
1329 
always @(posedge pext_clk[11] or posedge wb_rst_i)
1330 
  if (wb_rst_i)
1331 
    pextc_sampled[11] <= #1 1'b0;
1332 
  else
1333 
    pextc_sampled[11] <= #1 ext_pad_i[11];
1334 
`endif
1335 
 
1336 
`ifdef GPIO_LINES11
1337 
always @(posedge pext_clk[10] or posedge wb_rst_i)
1338 
  if (wb_rst_i)
1339 
    pextc_sampled[10] <= #1 1'b0;
1340 
  else
1341 
    pextc_sampled[10] <= #1 ext_pad_i[10];
1342 
`endif
1343 
 
1344 
`ifdef GPIO_LINES10
1345 
always @(posedge pext_clk[9] or posedge wb_rst_i)
1346 
  if (wb_rst_i)
1347 
    pextc_sampled[9] <= #1 1'b0;
1348 
  else
1349 
    pextc_sampled[9] <= #1 ext_pad_i[9];
1350 
`endif
1351 
 
1352 
`ifdef GPIO_LINES9
1353 
always @(posedge pext_clk[8] or posedge wb_rst_i)
1354 
  if (wb_rst_i)
1355 
    pextc_sampled[8] <= #1 1'b0;
1356 
  else
1357 
    pextc_sampled[8] <= #1 ext_pad_i[8];
1358 
`endif
1359 
 
1360 
`ifdef GPIO_LINES8
1361 
always @(posedge pext_clk[7] or posedge wb_rst_i)
1362 
  if (wb_rst_i)
1363 
    pextc_sampled[7] <= #1 1'b0;
1364 
  else
1365 
    pextc_sampled[7] <= #1 ext_pad_i[7];
1366 
`endif
1367 
 
1368 
`ifdef GPIO_LINES7
1369 
always @(posedge pext_clk[6] or posedge wb_rst_i)
1370 
  if (wb_rst_i)
1371 
    pextc_sampled[6] <= #1 1'b0;
1372 
  else
1373 
    pextc_sampled[6] <= #1 ext_pad_i[6];
1374 
`endif
1375 
 
1376 
`ifdef GPIO_LINES6
1377 
always @(posedge pext_clk[5] or posedge wb_rst_i)
1378 
  if (wb_rst_i)
1379 
    pextc_sampled[5] <= #1 1'b0;
1380 
  else
1381 
    pextc_sampled[5] <= #1 ext_pad_i[5];
1382 
`endif
1383 
 
1384 
`ifdef GPIO_LINES5
1385 
always @(posedge pext_clk[4] or posedge wb_rst_i)
1386 
  if (wb_rst_i)
1387 
    pextc_sampled[4] <= #1 1'b0;
1388 
  else
1389 
    pextc_sampled[4] <= #1 ext_pad_i[4];
1390 
`endif
1391 
 
1392 
`ifdef GPIO_LINES4
1393 
always @(posedge pext_clk[3] or posedge wb_rst_i)
1394 
  if (wb_rst_i)
1395 
    pextc_sampled[3] <= #1 1'b0;
1396 
  else
1397 
    pextc_sampled[3] <= #1 ext_pad_i[3];
1398 
`endif
1399 
 
1400 
`ifdef GPIO_LINES3
1401 
always @(posedge pext_clk[2] or posedge wb_rst_i)
1402 
  if (wb_rst_i)
1403 
    pextc_sampled[2] <= #1 1'b0;
1404 
  else
1405 
    pextc_sampled[2] <= #1 ext_pad_i[2];
1406 
`endif
1407 
 
1408 
`ifdef GPIO_LINES2
1409 
always @(posedge pext_clk[1] or posedge wb_rst_i)
1410 
  if (wb_rst_i)
1411 
    pextc_sampled[1] <= #1 1'b0;
1412 
  else
1413 
    pextc_sampled[1] <= #1 ext_pad_i[1];
1414 
`endif
1415 
 
1416 
`ifdef GPIO_LINES1
1417 
always @(posedge pext_clk[0] or posedge wb_rst_i)
1418 
  if (wb_rst_i)
1419 
    pextc_sampled[0] <= #1 1'b0;
1420 
  else
1421 
    pextc_sampled[0] <= #1 ext_pad_i[0];
1422 
`endif
1423 
 
1424 17 lampret 
//
1425 
// Latch using negedge external clock
1426 
//
1427 
`ifdef GPIO_NO_NEGEDGE_FLOPS
1428 
`else
1429 25 lampret 
always @(negedge clk_pad_i or posedge wb_rst_i)
1430 17 lampret 
        if (wb_rst_i)
1431 
                nextc_sampled <= #1 {gw{1'b0}};
1432 
        else
1433 25 lampret 
                nextc_sampled <= #1 ext_pad_i;
1434 17 lampret 
`endif
1435 
 
1436 
//
1437 
// Mux all registers when doing a read of GPIO registers
1438 
//
1439 14 lampret 
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
1440 56 gorand 
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
1441 14 lampret 
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
1442 
`ifdef GPIO_READREGS
1443 60 andreje 
  `ifdef GPIO_RGPIO_OUT
1444 
        `GPIO_RGPIO_OUT: begin
1445 26 lampret 
                        wb_dat[dw-1:0] = rgpio_out;
1446 14 lampret 
                end
1447 60 andreje 
  `endif
1448 
  `ifdef GPIO_RGPIO_OE
1449 14 lampret 
                `GPIO_RGPIO_OE: begin
1450 60 andreje 
                        wb_dat[dw-1:0] = rgpio_oe;
1451 14 lampret 
                end
1452 60 andreje 
  `endif
1453 
  `ifdef GPIO_RGPIO_INTE
1454 14 lampret 
                `GPIO_RGPIO_INTE: begin
1455 26 lampret 
                        wb_dat[dw-1:0] = rgpio_inte;
1456 14 lampret 
                end
1457 60 andreje 
  `endif
1458 
  `ifdef GPIO_RGPIO_PTRIG
1459 14 lampret 
                `GPIO_RGPIO_PTRIG: begin
1460 26 lampret 
                        wb_dat[dw-1:0] = rgpio_ptrig;
1461 14 lampret 
                end
1462 60 andreje 
  `endif
1463 
  `ifdef GPIO_RGPIO_NEC
1464 56 gorand 
                `GPIO_RGPIO_NEC: begin
1465 
                        wb_dat[dw-1:0] = rgpio_nec;
1466 
                end
1467 60 andreje 
  `endif
1468 
  `ifdef GPIO_RGPIO_ECLK
1469 56 gorand 
                `GPIO_RGPIO_ECLK: begin
1470 
                        wb_dat[dw-1:0] = rgpio_eclk;
1471 
                end
1472 60 andreje 
  `endif
1473 
  `ifdef GPIO_RGPIO_AUX
1474 14 lampret 
                `GPIO_RGPIO_AUX: begin
1475 26 lampret 
                        wb_dat[dw-1:0] = rgpio_aux;
1476 14 lampret 
                end
1477 60 andreje 
  `endif
1478 
  `ifdef GPIO_RGPIO_CTRL
1479 14 lampret 
                `GPIO_RGPIO_CTRL: begin
1480 56 gorand 
                        wb_dat[1:0] = rgpio_ctrl;
1481 
                        wb_dat[dw-1:2] = {dw-2{1'b0}};
1482 14 lampret 
                end
1483 60 andreje 
  `endif
1484 14 lampret 
`endif
1485 60 andreje 
  `ifdef GPIO_RGPIO_INTS
1486 21 lampret 
                `GPIO_RGPIO_INTS: begin
1487 26 lampret 
                        wb_dat[dw-1:0] = rgpio_ints;
1488 21 lampret 
                end
1489 60 andreje 
  `endif
1490 14 lampret 
                default: begin
1491 26 lampret 
                        wb_dat[dw-1:0] = rgpio_in;
1492 14 lampret 
                end
1493 
        endcase
1494 
 
1495 
//
1496 17 lampret 
// WB data output
1497 
//
1498 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1499 
always @(posedge wb_clk_i or posedge wb_rst_i)
1500 
        if (wb_rst_i)
1501 
                wb_dat_o <= #1 {dw{1'b0}};
1502 
        else
1503 
                wb_dat_o <= #1 wb_dat;
1504 
`else
1505 
assign wb_dat_o = wb_dat;
1506 
`endif
1507 
 
1508 
//
1509 21 lampret 
// RGPIO_INTS
1510 
//
1511 
`ifdef GPIO_RGPIO_INTS
1512 
always @(posedge wb_clk_i or posedge wb_rst_i)
1513 
        if (wb_rst_i)
1514 
                rgpio_ints <= #1 {gw{1'b0}};
1515 
        else if (rgpio_ints_sel && wb_we_i)
1516 
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
1517 31 lampret 
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
1518 
                rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
1519 21 lampret 
`else
1520 31 lampret 
assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
1521 21 lampret 
`endif
1522 
 
1523 
//
1524 14 lampret 
// Generate interrupt request
1525 
//
1526 21 lampret 
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
1527 14 lampret 
 
1528 
//
1529 17 lampret 
// Optional registration of WB interrupt
1530 14 lampret 
//
1531 17 lampret 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1532 
always @(posedge wb_clk_i or posedge wb_rst_i)
1533 
        if (wb_rst_i)
1534 19 lampret 
                wb_inta_o <= #1 1'b0;
1535 17 lampret 
        else
1536 
                wb_inta_o <= #1 wb_inta;
1537 
`else
1538 
assign wb_inta_o = wb_inta;
1539 
`endif
1540 14 lampret 
 
1541 
//
1542 17 lampret 
// Output enables are RGPIO_OE bits
1543 14 lampret 
//
1544 60 andreje 
assign ext_padoe_o = rgpio_oe;
1545 14 lampret 
 
1546 17 lampret 
//
1547 
// Generate GPIO outputs
1548 
//
1549 
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
1550 
 
1551 
//
1552 
// Optional registration of GPIO outputs
1553 
//
1554 
`ifdef GPIO_REGISTERED_IO_OUTPUTS
1555 
always @(posedge wb_clk_i or posedge wb_rst_i)
1556 
        if (wb_rst_i)
1557 25 lampret 
                ext_pad_o <= #1 {gw{1'b0}};
1558 17 lampret 
        else
1559 25 lampret 
                ext_pad_o <= #1 out_pad;
1560 14 lampret 
`else
1561 25 lampret 
assign ext_pad_o = out_pad;
1562 17 lampret 
`endif
1563 14 lampret 
 
1564 17 lampret 
`else
1565 
 
1566 14 lampret 
//
1567 
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
1568 
// is cleared and WISHBONE transfers complete with errors
1569 
//
1570 
assign wb_inta_o = 1'b0;
1571 
assign wb_ack_o = 1'b0;
1572 
assign wb_err_o = wb_cyc_i & wb_stb_i;
1573 60 andreje 
assign ext_padoe_o = {gw{1'b1}};
1574 25 lampret 
assign ext_pad_o = {gw{1'b0}};
1575 14 lampret 
 
1576 
//
1577 
// Read GPIO registers
1578 
//
1579 
assign wb_dat_o = {dw{1'b0}};
1580 
 
1581 
`endif
1582 
 
1583 
endmodule
1584 56 gorand 
 

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