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[/] [gpio/] [tags/] [rel_15/] [rtl/] [verilog/] [gpio_defines.v] - Blame information for rev 52

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE GPIO Definitions                                   ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  GPIO IP Definitions.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2003/11/06 13:59:07  gorand
// added support for 8-bit access to registers.
//
// Revision 1.2  2003/10/02 18:54:35  simons
// GPIO signals muxed with other peripherals, higland_board fixed.
//
// Revision 1.1.1.1  2003/06/24 09:09:23  simons
// This files were moved here from toplevel folder.
//
// Revision 1.1.1.1  2003/06/11 18:51:13  simons
// Initial import.
//
// Revision 1.5  2002/11/11 21:36:28  lampret
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
//
// Revision 1.4  2002/05/06 18:25:31  lampret
// negedge flops are enabled by default.
//
// Revision 1.3  2001/12/25 17:12:35  lampret
// Added RGPIO_INTS.
//
// Revision 1.2  2001/11/15 02:24:37  lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.3  2001/07/15 00:21:10  lampret
// Registers can be omitted and will have certain default values
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
//
// Number of GPIO I/O signals
//
// This is the most important parameter of the GPIO IP core. It defines how many
// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are
// required, use several instances of GPIO IP core.
//
// Default is 16.
//
`define GPIO_IOS 31
 
 
//
// Undefine this one if you don't want to remove GPIO block from your design
// but you also don't need it. When it is undefined, all GPIO ports still
// remain valid and the core can be synthesized however internally there is
// no GPIO funationality.
//
// Defined by default (duhh !).
//
`define GPIO_IMPLEMENTED
 
//
// Define to register all WISHBONE outputs.
//
// Register outputs if you are using GPIO core as a block and synthesizing
// and place&routing it separately from the rest of the system.
//
// If you do not need registered outputs, you can save some area by not defining
// this macro. By default it is defined.
//
`define GPIO_REGISTERED_WB_OUTPUTS
 
//
// Define to register all GPIO pad outputs.
//
// Register outputs if you are using GPIO core as a block and synthesizing
// and place&routing it separately from the rest of the system.
//
// If you do not need registered outputs, you can save some area by not defining
// this macro. By default it is defined.
//
`define GPIO_REGISTERED_IO_OUTPUTS
 
//
// Define to avoid using negative edge clock flip-flops for external clock
// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with
// positive edge clock flip-flops will be used.
//
// By default it is not defined.
//
//`define GPIO_NO_NEGEDGE_FLOPS
 
//
// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
// clock signal, enable the following define.
//
// By default it is not defined.
//
//`define GPIO_NO_CLKPAD_LOGIC
 
// 
// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
// is usually useful if you want really small area (for example when implemented in
// FPGA).
//
// To follow GPIO IP core specification document this one must be defined. Also to
// successfully run the test bench it must be defined. By default it is defined.
//
`define GPIO_READREGS
 
//
// Full WISHBONE address decoding
//
// It is is undefined, partial WISHBONE address decoding is performed.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define GPIO_FULL_DECODE
 
//
// Strict 32-bit WISHBONE access
//
// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
// not defined, err_o is asserted whenever 8- or 16-bit access is made.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
//`define GPIO_STRICT_32BIT_ACCESS
//
`ifdef GPIO_STRICT_32BIT_ACCESS
`else
// added by gorand :
// if GPIO_STRICT_32BIT_ACCESS is not defined,
// depending on number of gpio I/O lines, the following are defined :
// if the number of I/O lines is in range 1-8,   GPIO_WB_BYTES1 is defined,
// if the number of I/O lines is in range 9-16,  GPIO_WB_BYTES2 is defined,
// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
 
`define GPIO_WB_BYTES4
`endif
 
//
// WISHBONE address bits used for full decoding of GPIO registers.
//
`define GPIO_ADDRHH 6
`define GPIO_ADDRHL 5
`define GPIO_ADDRLH 1
`define GPIO_ADDRLL 0
 
//
// Bits of WISHBONE address used for partial decoding of GPIO registers.
//
// Default 4:2.
//
`define GPIO_OFS_BITS   `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
 
//
// Addresses of GPIO registers
//
// To comply with GPIO IP core specification document they must go from
// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,
// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL
//
// If particular register is not needed, it's address definition can be omitted
// and the register will not be implemented. Instead a fixed default value will
// be used.
//
`define GPIO_RGPIO_IN           3'h0    // Address 0x00
`define GPIO_RGPIO_OUT          3'h1    // Address 0x04
`define GPIO_RGPIO_OE           3'h2    // Address 0x08
`define GPIO_RGPIO_INTE         3'h3    // Address 0x0c
`define GPIO_RGPIO_PTRIG        3'h4    // Address 0x10
`define GPIO_RGPIO_AUX          3'h5    // Address 0x14
`define GPIO_RGPIO_CTRL         3'h6    // Address 0x18
`define GPIO_RGPIO_INTS         3'h7    // Address 0x1c
 
//
// Default values for unimplemented GPIO registers
//
`define GPIO_DEF_RGPIO_IN       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_OUT      `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_OE       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_INTE     `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_PTRIG    `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_AUX      `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_CTRL     `GPIO_IOS'h0
 
//
// RGPIO_CTRL bits
//
// To comply with the GPIO IP core specification document they must go from
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
//
`define GPIO_RGPIO_CTRL_ECLK            0
`define GPIO_RGPIO_CTRL_NEC             1
`define GPIO_RGPIO_CTRL_INTE            2
`define GPIO_RGPIO_CTRL_INTS            3

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE GPIO Definitions ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// GPIO IP Definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	52	simons	`// Revision 1.6 2003/11/06 13:59:07 gorand`
48			`// added support for 8-bit access to registers.`
49			`//`
50	34	gorand	`// Revision 1.2 2003/10/02 18:54:35 simons`
51			`// GPIO signals muxed with other peripherals, higland_board fixed.`
52			`//`
53			`// Revision 1.1.1.1 2003/06/24 09:09:23 simons`
54			`// This files were moved here from toplevel folder.`
55			`//`
56			`// Revision 1.1.1.1 2003/06/11 18:51:13 simons`
57			`// Initial import.`
58			`//`
59			`// Revision 1.5 2002/11/11 21:36:28 lampret`
60			`// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].`
61			`//`
62	29	lampret	`// Revision 1.4 2002/05/06 18:25:31 lampret`
63			`// negedge flops are enabled by default.`
64			`//`
65	27	lampret	`// Revision 1.3 2001/12/25 17:12:35 lampret`
66			`// Added RGPIO_INTS.`
67			`//`
68	21	lampret	`// Revision 1.2 2001/11/15 02:24:37 lampret`
69			`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
70			`//`
71	17	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
72			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
73			`//`
74	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
75			`// Changed directory structure, port names and drfines.`
76			`//`
77			`// Revision 1.3 2001/07/15 00:21:10 lampret`
78			`// Registers can be omitted and will have certain default values`
79			`//`
80			`// Revision 1.2 2001/07/14 20:39:26 lampret`
81			`// Better configurability.`
82			`//`
83			`// Revision 1.1 2001/06/05 07:45:26 lampret`
84			`// Added initial RTL and test benches. There are still some issues with these files.`
85			`//`
86			`//`
87
88			`//`
89			`// Number of GPIO I/O signals`
90			`//`
91			`// This is the most important parameter of the GPIO IP core. It defines how many`
92			`// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are`
93			`// required, use several instances of GPIO IP core.`
94			`//`
95			`// Default is 16.`
96			`//`
97	34	gorand	`define GPIO_IOS 31
98	14	lampret
99	34	gorand
100	14	lampret	`//`
101			`// Undefine this one if you don't want to remove GPIO block from your design`
102			`// but you also don't need it. When it is undefined, all GPIO ports still`
103			`// remain valid and the core can be synthesized however internally there is`
104			`// no GPIO funationality.`
105			`//`
106			`// Defined by default (duhh !).`
107			`//`
108			`define GPIO_IMPLEMENTED
109
110	17	lampret	`//`
111			`// Define to register all WISHBONE outputs.`
112			`//`
113			`// Register outputs if you are using GPIO core as a block and synthesizing`
114			`// and place&routing it separately from the rest of the system.`
115			`//`
116			`// If you do not need registered outputs, you can save some area by not defining`
117			`// this macro. By default it is defined.`
118			`//`
119			`define GPIO_REGISTERED_WB_OUTPUTS
120
121			`//`
122			`// Define to register all GPIO pad outputs.`
123			`//`
124			`// Register outputs if you are using GPIO core as a block and synthesizing`
125			`// and place&routing it separately from the rest of the system.`
126			`//`
127			`// If you do not need registered outputs, you can save some area by not defining`
128			`// this macro. By default it is defined.`
129			`//`
130			`define GPIO_REGISTERED_IO_OUTPUTS
131
132			`//`
133			`// Define to avoid using negative edge clock flip-flops for external clock`
134			`// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with`
135			`// positive edge clock flip-flops will be used.`
136			`//`
137	27	lampret	`// By default it is not defined.`
138	17	lampret	`//`
139	27	lampret	//`define GPIO_NO_NEGEDGE_FLOPS
140	17	lampret
141	29	lampret	`//`
142			`// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock`
143			`// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on`
144			`// clock signal, enable the following define.`
145			`//`
146			`// By default it is not defined.`
147			`//`
148			//`define GPIO_NO_CLKPAD_LOGIC
149
150	14	lampret	`//`
151			`// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.`
152			`// When it is undefined all reads of GPIO registers return RGPIO_IN register. This`
153			`// is usually useful if you want really small area (for example when implemented in`
154			`// FPGA).`
155			`//`
156			`// To follow GPIO IP core specification document this one must be defined. Also to`
157			`// successfully run the test bench it must be defined. By default it is defined.`
158			`//`
159			`define GPIO_READREGS
160
161			`//`
162			`// Full WISHBONE address decoding`
163			`//`
164			`// It is is undefined, partial WISHBONE address decoding is performed.`
165			`// Undefine it if you need to save some area.`
166			`//`
167			`// By default it is defined.`
168			`//`
169			`define GPIO_FULL_DECODE
170
171			`//`
172			`// Strict 32-bit WISHBONE access`
173			`//`
174			`// If this one is defined, all WISHBONE accesses must be 32-bit. If it is`
175			`// not defined, err_o is asserted whenever 8- or 16-bit access is made.`
176			`// Undefine it if you need to save some area.`
177			`//`
178			`// By default it is defined.`
179			`//`
180	34	gorand	//`define GPIO_STRICT_32BIT_ACCESS
181			`//`
182	52	simons	`ifdef GPIO_STRICT_32BIT_ACCESS
183			`else
184	34	gorand	`// added by gorand :`
185			`// if GPIO_STRICT_32BIT_ACCESS is not defined,`
186			`// depending on number of gpio I/O lines, the following are defined :`
187			`// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined,`
188			`// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,`
189			`// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,`
190			`// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,`
191	14	lampret
192	34	gorand	`define GPIO_WB_BYTES4
193			`endif
194
195	14	lampret	`//`
196			`// WISHBONE address bits used for full decoding of GPIO registers.`
197			`//`
198	17	lampret	`define GPIO_ADDRHH 6
199	14	lampret	`define GPIO_ADDRHL 5
200			`define GPIO_ADDRLH 1
201			`define GPIO_ADDRLL 0
202
203			`//`
204			`// Bits of WISHBONE address used for partial decoding of GPIO registers.`
205			`//`
206			`// Default 4:2.`
207			`//`
208			`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
209
210			`//`
211			`// Addresses of GPIO registers`
212			`//`
213			`// To comply with GPIO IP core specification document they must go from`
214			`// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,`
215			`// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL`
216			`//`
217			`// If particular register is not needed, it's address definition can be omitted`
218			`// and the register will not be implemented. Instead a fixed default value will`
219			`// be used.`
220			`//`
221			`define GPIO_RGPIO_IN 3'h0 // Address 0x00
222			`define GPIO_RGPIO_OUT 3'h1 // Address 0x04
223			`define GPIO_RGPIO_OE 3'h2 // Address 0x08
224			`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c
225			`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
226			`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
227			`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
228	21	lampret	`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c
229	14	lampret
230			`//`
231			`// Default values for unimplemented GPIO registers`
232			`//`
233			`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
234			`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0
235			`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0
236			`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0
237			`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0
238			`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0
239			`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0
240
241			`//`
242			`// RGPIO_CTRL bits`
243			`//`
244			`// To comply with the GPIO IP core specification document they must go from`
245			`// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT`
246			`//`
247			`define GPIO_RGPIO_CTRL_ECLK 0
248			`define GPIO_RGPIO_CTRL_NEC 1
249			`define GPIO_RGPIO_CTRL_INTE 2
250	21	lampret	`define GPIO_RGPIO_CTRL_INTS 3

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[/] [gpio/] [tags/] [rel_15/] [rtl/] [verilog/] [gpio_defines.v] - Blame information for rev 52