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[/] [gpio/] [tags/] [rel_4/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] in_pad_i;       // GPIO Inputs
input                   ext_clk_pad_i;  // GPIO Eclk
output  [gw-1:0] out_pad_o;      // GPIO Outputs
output  [gw-1:0] oen_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_in_sel;   // RGPIO_IN select
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
reg     [dw-1:0] wb_dat_o;       // Data out
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err_o = 1'b0;
`endif
`endif
 
//
// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,
// external clock is used.
//
assign latch_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ?
                ext_clk_pad_i ^ rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] : wb_clk_i;
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_in_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_IN) & full_decoding;
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge latch_clk or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_pad_i;
`else
assign rgpio_in = in_pad_i;
`endif
 
//
// Read GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat_o[3:0] <= rgpio_ctrl;
                        wb_dat_o[dw-1:4] <= {dw-4{1'b0}};
                end
`endif
                default: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
                end
        endcase
 
//
// Generate interrupt request
//
assign wb_inta_o = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Generate output enables from inverted RGPIO_OE bits
//
assign oen_padoen_o = ~rgpio_oe;
 
//
// Generate outputs
//
assign out_pad_o = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign oen_padoen_o = {gw{1'b1}};
assign out_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

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[/] [gpio/] [tags/] [rel_4/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	15	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
49			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
50			`//`
51	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
52			`// Changed directory structure, port names and drfines.`
53			`//`
54			`// Revision 1.2 2001/07/14 20:39:26 lampret`
55			`// Better configurability.`
56			`//`
57			`// Revision 1.1 2001/06/05 07:45:26 lampret`
58			`// Added initial RTL and test benches. There are still some issues with these files.`
59			`//`
60			`//`
61
62			`// synopsys translate_off`
63			`include "timescale.v"
64			`// synopsys translate_on`
65			`include "gpio_defines.v"
66
67			`module gpio_top(`
68			`// WISHBONE Interface`
69			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
70			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
71
72			`// Auxiliary inputs interface`
73			`aux_i,`
74
75			`// External GPIO Interface`
76			`in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o`
77			`);`
78
79			`parameter dw = 32;`
80			parameter aw = `GPIO_ADDRHH+1;
81			parameter gw = `GPIO_IOS;
82
83			`//`
84			`// WISHBONE Interface`
85			`//`
86			`input wb_clk_i; // Clock`
87			`input wb_rst_i; // Reset`
88			`input wb_cyc_i; // cycle valid input`
89			`input [aw-1:0] wb_adr_i; // address bus inputs`
90			`input [dw-1:0] wb_dat_i; // input data bus`
91			`input [3:0] wb_sel_i; // byte select inputs`
92			`input wb_we_i; // indicates write transfer`
93			`input wb_stb_i; // strobe input`
94			`output [dw-1:0] wb_dat_o; // output data bus`
95			`output wb_ack_o; // normal termination`
96			`output wb_err_o; // termination w/ error`
97			`output wb_inta_o; // Interrupt request output`
98
99			`// Auxiliary Inputs Interface`
100			`input [gw-1:0] aux_i; // Auxiliary inputs`
101
102			`//`
103			`// External GPIO Interface`
104			`//`
105			`input [gw-1:0] in_pad_i; // GPIO Inputs`
106			`input ext_clk_pad_i; // GPIO Eclk`
107			`output [gw-1:0] out_pad_o; // GPIO Outputs`
108			`output [gw-1:0] oen_padoen_o; // GPIO output drivers enables`
109
110			`ifdef GPIO_IMPLEMENTED
111
112			`//`
113			`// GPIO Input Register (or no register)`
114			`//`
115			`ifdef GPIO_RGPIO_IN
116			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
117			`else
118			`wire [gw-1:0] rgpio_in; // No register`
119			`endif
120
121			`//`
122			`// GPIO Output Register (or no register)`
123			`//`
124			`ifdef GPIO_RGPIO_OUT
125			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
126			`else
127			`wire [gw-1:0] rgpio_out; // No register`
128			`endif
129
130			`//`
131			`// GPIO Output Driver Enable Register (or no register)`
132			`//`
133			`ifdef GPIO_RGPIO_OE
134			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
135			`else
136			`wire [gw-1:0] rgpio_oe; // No register`
137			`endif
138
139			`//`
140			`// GPIO Interrupt Enable Register (or no register)`
141			`//`
142			`ifdef GPIO_RGPIO_INTE
143			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
144			`else
145			`wire [gw-1:0] rgpio_inte; // No register`
146			`endif
147
148			`//`
149			`// GPIO Positive edge Triggered Register (or no register)`
150			`//`
151			`ifdef GPIO_RGPIO_PTRIG
152			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
153			`else
154			`wire [gw-1:0] rgpio_ptrig; // No register`
155			`endif
156
157			`//`
158			`// GPIO Auxiliary select Register (or no register)`
159			`//`
160			`ifdef GPIO_RGPIO_AUX
161			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
162			`else
163			`wire [gw-1:0] rgpio_aux; // No register`
164			`endif
165
166			`//`
167			`// GPIO Control Register (or no register)`
168			`//`
169			`ifdef GPIO_RGPIO_CTRL
170			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
171			`else
172			`wire [3:0] rgpio_ctrl; // No register`
173			`endif
174
175			`//`
176			`// Internal wires & regs`
177			`//`
178			`wire rgpio_in_sel; // RGPIO_IN select`
179			`wire rgpio_out_sel; // RGPIO_OUT select`
180			`wire rgpio_oe_sel; // RGPIO_OE select`
181			`wire rgpio_inte_sel; // RGPIO_INTE select`
182			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
183			`wire rgpio_aux_sel; // RGPIO_AUX select`
184			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
185			`wire latch_clk; // Latch clock`
186			`wire full_decoding; // Full address decoding qualification`
187			`reg [dw-1:0] wb_dat_o; // Data out`
188
189			`//`
190			`// All WISHBONE transfer terminations are successful except when:`
191			`// a) full address decoding is enabled and address doesn't match`
192			`// any of the GPIO registers`
193			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
194			`//`
195			`assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;`
196			`ifdef GPIO_FULL_DECODE
197			`ifdef GPIO_STRICT_32BIT_ACCESS
198	15	lampret	`assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
199	14	lampret	`else
200			`assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;`
201			`endif
202			`else
203			`ifdef GPIO_STRICT_32BIT_ACCESS
204	15	lampret	`assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
205	14	lampret	`else
206			`assign wb_err_o = 1'b0;`
207			`endif
208			`endif
209
210			`//`
211			`// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,`
212			`// external clock is used.`
213			`//`
214			assign latch_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ?
215			ext_clk_pad_i ^ rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] : wb_clk_i;
216
217			`//`
218			`// Full address decoder`
219			`//`
220			`ifdef GPIO_FULL_DECODE
221			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
222			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
223			`else
224			`assign full_decoding = 1'b1;`
225			`endif
226
227			`//`
228			`// GPIO registers address decoder`
229			`//`
230			assign rgpio_in_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_IN) & full_decoding;
231			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
232			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
233			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
234			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
235			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
236			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
237
238			`//`
239			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
240			`//`
241			`ifdef GPIO_RGPIO_CTRL
242			`always @(posedge wb_clk_i or posedge wb_rst_i)`
243			`if (wb_rst_i)`
244			`rgpio_ctrl <= #1 4'b0;`
245			`else if (rgpio_ctrl_sel && wb_we_i)`
246			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
247			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
248			rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] \| wb_inta_o;
249			`else
250			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
251			`endif
252
253			`//`
254			`// Write to RGPIO_OUT`
255			`//`
256			`ifdef GPIO_RGPIO_OUT
257			`always @(posedge wb_clk_i or posedge wb_rst_i)`
258			`if (wb_rst_i)`
259			`rgpio_out <= #1 {gw{1'b0}};`
260			`else if (rgpio_out_sel && wb_we_i)`
261			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
262			`else
263			assign rgpio_out = `GPIO_DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
264			`endif
265
266			`//`
267			`// Write to RGPIO_OE`
268			`//`
269			`ifdef GPIO_RGPIO_OE
270			`always @(posedge wb_clk_i or posedge wb_rst_i)`
271			`if (wb_rst_i)`
272			`rgpio_oe <= #1 {gw{1'b0}};`
273			`else if (rgpio_oe_sel && wb_we_i)`
274			`rgpio_oe <= #1 wb_dat_i[gw-1:0];`
275			`else
276			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
277			`endif
278
279			`//`
280			`// Write to RGPIO_INTE`
281			`//`
282			`ifdef GPIO_RGPIO_INTE
283			`always @(posedge wb_clk_i or posedge wb_rst_i)`
284			`if (wb_rst_i)`
285			`rgpio_inte <= #1 {gw{1'b0}};`
286			`else if (rgpio_inte_sel && wb_we_i)`
287			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
288			`else
289			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
290			`endif
291
292			`//`
293			`// Write to RGPIO_PTRIG`
294			`//`
295			`ifdef GPIO_RGPIO_PTRIG
296			`always @(posedge wb_clk_i or posedge wb_rst_i)`
297			`if (wb_rst_i)`
298			`rgpio_ptrig <= #1 {gw{1'b0}};`
299			`else if (rgpio_ptrig_sel && wb_we_i)`
300			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
301			`else
302			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
303			`endif
304
305			`//`
306			`// Write to RGPIO_AUX`
307			`//`
308			`ifdef GPIO_RGPIO_AUX
309			`always @(posedge wb_clk_i or posedge wb_rst_i)`
310			`if (wb_rst_i)`
311			`rgpio_aux <= #1 {gw{1'b0}};`
312			`else if (rgpio_aux_sel && wb_we_i)`
313			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
314			`else
315			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
316			`endif
317
318			`//`
319			`// Latch into RGPIO_IN`
320			`//`
321			`ifdef GPIO_RGPIO_IN
322			`always @(posedge latch_clk or posedge wb_rst_i)`
323			`if (wb_rst_i)`
324			`rgpio_in <= #1 {gw{1'b0}};`
325			`else`
326			`rgpio_in <= #1 in_pad_i;`
327			`else
328			`assign rgpio_in = in_pad_i;`
329			`endif
330
331			`//`
332			`// Read GPIO registers`
333			`//`
334			`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
335			`rgpio_ptrig or rgpio_aux or rgpio_ctrl)`
336			case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
337			`ifdef GPIO_READREGS
338			`GPIO_RGPIO_OUT: begin
339			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};`
340			`end`
341			`GPIO_RGPIO_OE: begin
342			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};`
343			`end`
344			`GPIO_RGPIO_INTE: begin
345			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};`
346			`end`
347			`GPIO_RGPIO_PTRIG: begin
348			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};`
349			`end`
350			`GPIO_RGPIO_AUX: begin
351			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};`
352			`end`
353			`GPIO_RGPIO_CTRL: begin
354			`wb_dat_o[3:0] <= rgpio_ctrl;`
355			`wb_dat_o[dw-1:4] <= {dw-4{1'b0}};`
356			`end`
357			`endif
358			`default: begin`
359			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};`
360			`end`
361			`endcase`
362
363			`//`
364			`// Generate interrupt request`
365			`//`
366			assign wb_inta_o = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
367
368			`//`
369			`// Generate output enables from inverted RGPIO_OE bits`
370			`//`
371			`assign oen_padoen_o = ~rgpio_oe;`
372
373			`//`
374			`// Generate outputs`
375			`//`
376			`assign out_pad_o = rgpio_out & ~rgpio_aux \| aux_i & rgpio_aux;`
377
378			`else
379
380			`//`
381			`// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL`
382			`// is cleared and WISHBONE transfers complete with errors`
383			`//`
384			`assign wb_inta_o = 1'b0;`
385			`assign wb_ack_o = 1'b0;`
386			`assign wb_err_o = wb_cyc_i & wb_stb_i;`
387			`assign oen_padoen_o = {gw{1'b1}};`
388			`assign out_pad_o = {gw{1'b0}};`
389
390			`//`
391			`// Read GPIO registers`
392			`//`
393			`assign wb_dat_o = {dw{1'b0}};`
394
395			`endif
396
397			`endmodule`