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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2002/03/09 03:43:27  lampret
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
//
// Revision 1.8  2002/01/14 19:06:28  lampret
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
//
// Revision 1.7  2001/12/25 17:21:21  lampret
// Fixed two typos.
//
// Revision 1.6  2001/12/25 17:12:35  lampret
// Added RGPIO_INTS.
//
// Revision 1.5  2001/12/12 20:35:53  lampret
// Fixing style.
//
// Revision 1.4  2001/12/12 07:12:58  lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
// Revision 1.3  2001/11/15 02:24:37  lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.2  2001/10/31 02:26:51  lampret
// Fixed wb_err_o.
//
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] ext_pad_i;      // GPIO Inputs
input                   clk_pad_i;      // GPIO Eclk
output  [gw-1:0] ext_pad_o;      // GPIO Outputs
output  [gw-1:0] ext_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
`else
wire    [gw-1:0] rgpio_ints;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    rgpio_ints_sel; // RGPIO_INTS select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
wire    [gw-1:0] in_muxed;       // Muxed inputs
wire                    wb_ack;         // WB Acknowledge
wire                    wb_err;         // WB Error
wire                    wb_inta;        // WB Interrupt
reg     [dw-1:0] wb_dat;         // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg                     wb_ack_o;       // WB Acknowledge
reg                     wb_err_o;       // WB Error
reg                     wb_inta_o;      // WB Interrupt
reg     [dw-1:0] wb_dat_o;       // WB Data out
`endif
wire    [gw-1:0] out_pad;        // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg     [gw-1:0] ext_pad_o;      // GPIO Outputs
`endif
wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock
wire                    pext_clk;       // External clock for posedge flops
reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs
`endif
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
 
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
 
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_ack & ~wb_ack_o;
`else
assign wb_ack_o = wb_ack;
`endif
 
//
// WB Error
//
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
`endif
`endif
 
//
// Optional registration of WB error
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & ~wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
`else
assign pext_clk = clk_pad_i;
`endif
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
`endif
 
//
// Latch using posedge external clock
//
always @(posedge pext_clk or posedge wb_rst_i)
        if (wb_rst_i)
                pextc_sampled <= #1 {gw{1'b0}};
        else
                pextc_sampled <= #1 ext_pad_i;
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge clk_pad_i or posedge wb_rst_i)
        if (wb_rst_i)
                nextc_sampled <= #1 {gw{1'b0}};
        else
                nextc_sampled <= #1 ext_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat[3:0] = rgpio_ctrl;
                        wb_dat[dw-1:4] = {dw-4{1'b0}};
                end
`endif
                `GPIO_RGPIO_INTS: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};
                end
                default: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
                end
        endcase
 
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else
                wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
 
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ints <= #1 {gw{1'b0}};
        else if (rgpio_ints_sel && wb_we_i)
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != ext_pad_i)
                rgpio_ints <= #1 (rgpio_ints | (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
`else
assign rgpio_ints = (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_inta_o <= #1 1'b0;
        else
                wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
 
//
// Output enables are RGPIO_OE bits
//
assign ext_padoen_o = rgpio_oe;
 
//
// Generate GPIO outputs
//
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                ext_pad_o <= #1 {gw{1'b0}};
        else
                ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign ext_padoen_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	25	lampret	`// Revision 1.9 2002/03/09 03:43:27 lampret`
49			`// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)`
50			`//`
51	24	lampret	`// Revision 1.8 2002/01/14 19:06:28 lampret`
52			`// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.`
53			`//`
54	23	lampret	`// Revision 1.7 2001/12/25 17:21:21 lampret`
55			`// Fixed two typos.`
56			`//`
57	22	lampret	`// Revision 1.6 2001/12/25 17:12:35 lampret`
58			`// Added RGPIO_INTS.`
59			`//`
60	21	lampret	`// Revision 1.5 2001/12/12 20:35:53 lampret`
61			`// Fixing style.`
62			`//`
63	20	lampret	`// Revision 1.4 2001/12/12 07:12:58 lampret`
64			`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`
65			`//`
66	19	lampret	`// Revision 1.3 2001/11/15 02:24:37 lampret`
67			`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
68			`//`
69	17	lampret	`// Revision 1.2 2001/10/31 02:26:51 lampret`
70			`// Fixed wb_err_o.`
71			`//`
72	15	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
73			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
74			`//`
75	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
76			`// Changed directory structure, port names and drfines.`
77			`//`
78			`// Revision 1.2 2001/07/14 20:39:26 lampret`
79			`// Better configurability.`
80			`//`
81			`// Revision 1.1 2001/06/05 07:45:26 lampret`
82			`// Added initial RTL and test benches. There are still some issues with these files.`
83			`//`
84			`//`
85
86			`// synopsys translate_off`
87			`include "timescale.v"
88			`// synopsys translate_on`
89			`include "gpio_defines.v"
90
91			`module gpio_top(`
92			`// WISHBONE Interface`
93			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
94			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
95
96			`// Auxiliary inputs interface`
97			`aux_i,`
98
99			`// External GPIO Interface`
100	25	lampret	`ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o`
101	14	lampret	`);`
102
103			`parameter dw = 32;`
104			parameter aw = `GPIO_ADDRHH+1;
105			parameter gw = `GPIO_IOS;
106
107			`//`
108			`// WISHBONE Interface`
109			`//`
110			`input wb_clk_i; // Clock`
111			`input wb_rst_i; // Reset`
112			`input wb_cyc_i; // cycle valid input`
113			`input [aw-1:0] wb_adr_i; // address bus inputs`
114			`input [dw-1:0] wb_dat_i; // input data bus`
115			`input [3:0] wb_sel_i; // byte select inputs`
116			`input wb_we_i; // indicates write transfer`
117			`input wb_stb_i; // strobe input`
118			`output [dw-1:0] wb_dat_o; // output data bus`
119			`output wb_ack_o; // normal termination`
120			`output wb_err_o; // termination w/ error`
121			`output wb_inta_o; // Interrupt request output`
122
123			`// Auxiliary Inputs Interface`
124			`input [gw-1:0] aux_i; // Auxiliary inputs`
125
126			`//`
127			`// External GPIO Interface`
128			`//`
129	25	lampret	`input [gw-1:0] ext_pad_i; // GPIO Inputs`
130			`input clk_pad_i; // GPIO Eclk`
131			`output [gw-1:0] ext_pad_o; // GPIO Outputs`
132			`output [gw-1:0] ext_padoen_o; // GPIO output drivers enables`
133	14	lampret
134			`ifdef GPIO_IMPLEMENTED
135
136			`//`
137			`// GPIO Input Register (or no register)`
138			`//`
139			`ifdef GPIO_RGPIO_IN
140			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
141			`else
142			`wire [gw-1:0] rgpio_in; // No register`
143			`endif
144
145			`//`
146			`// GPIO Output Register (or no register)`
147			`//`
148			`ifdef GPIO_RGPIO_OUT
149			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
150			`else
151			`wire [gw-1:0] rgpio_out; // No register`
152			`endif
153
154			`//`
155			`// GPIO Output Driver Enable Register (or no register)`
156			`//`
157			`ifdef GPIO_RGPIO_OE
158			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
159			`else
160			`wire [gw-1:0] rgpio_oe; // No register`
161			`endif
162
163			`//`
164			`// GPIO Interrupt Enable Register (or no register)`
165			`//`
166			`ifdef GPIO_RGPIO_INTE
167			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
168			`else
169			`wire [gw-1:0] rgpio_inte; // No register`
170			`endif
171
172			`//`
173			`// GPIO Positive edge Triggered Register (or no register)`
174			`//`
175			`ifdef GPIO_RGPIO_PTRIG
176			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
177			`else
178			`wire [gw-1:0] rgpio_ptrig; // No register`
179			`endif
180
181			`//`
182			`// GPIO Auxiliary select Register (or no register)`
183			`//`
184			`ifdef GPIO_RGPIO_AUX
185			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
186			`else
187			`wire [gw-1:0] rgpio_aux; // No register`
188			`endif
189
190			`//`
191			`// GPIO Control Register (or no register)`
192			`//`
193			`ifdef GPIO_RGPIO_CTRL
194			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
195			`else
196			`wire [3:0] rgpio_ctrl; // No register`
197			`endif
198
199			`//`
200	21	lampret	`// GPIO Interrupt Status Register (or no register)`
201			`//`
202			`ifdef GPIO_RGPIO_INTS
203			`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`
204			`else
205			`wire [gw-1:0] rgpio_ints; // No register`
206			`endif
207
208			`//`
209	14	lampret	`// Internal wires & regs`
210			`//`
211			`wire rgpio_out_sel; // RGPIO_OUT select`
212			`wire rgpio_oe_sel; // RGPIO_OE select`
213			`wire rgpio_inte_sel; // RGPIO_INTE select`
214			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
215			`wire rgpio_aux_sel; // RGPIO_AUX select`
216			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
217	21	lampret	`wire rgpio_ints_sel; // RGPIO_INTS select`
218	14	lampret	`wire latch_clk; // Latch clock`
219			`wire full_decoding; // Full address decoding qualification`
220	17	lampret	`wire [gw-1:0] in_muxed; // Muxed inputs`
221			`wire wb_ack; // WB Acknowledge`
222			`wire wb_err; // WB Error`
223			`wire wb_inta; // WB Interrupt`
224			`reg [dw-1:0] wb_dat; // WB Data out`
225			`ifdef GPIO_REGISTERED_WB_OUTPUTS
226			`reg wb_ack_o; // WB Acknowledge`
227			`reg wb_err_o; // WB Error`
228			`reg wb_inta_o; // WB Interrupt`
229			`reg [dw-1:0] wb_dat_o; // WB Data out`
230			`endif
231			`wire [gw-1:0] out_pad; // GPIO Outputs`
232			`ifdef GPIO_REGISTERED_IO_OUTPUTS
233	25	lampret	`reg [gw-1:0] ext_pad_o; // GPIO Outputs`
234	17	lampret	`endif
235			`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`
236			`wire pext_clk; // External clock for posedge flops`
237			`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`
238			`ifdef GPIO_NO_NEGEDGE_FLOPS
239			`else
240			`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`
241			`endif
242	14	lampret
243			`//`
244			`// All WISHBONE transfer terminations are successful except when:`
245			`// a) full address decoding is enabled and address doesn't match`
246			`// any of the GPIO registers`
247			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
248			`//`
249	17	lampret
250			`//`
251			`// WB Acknowledge`
252			`//`
253			`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`
254
255			`//`
256			`// Optional registration of WB Ack`
257			`//`
258			`ifdef GPIO_REGISTERED_WB_OUTPUTS
259			`always @(posedge wb_clk_i or posedge wb_rst_i)`
260			`if (wb_rst_i)`
261			`wb_ack_o <= #1 1'b0;`
262			`else`
263	23	lampret	`wb_ack_o <= #1 wb_ack & ~wb_ack_o;`
264	17	lampret	`else
265			`assign wb_ack_o = wb_ack;`
266			`endif
267
268			`//`
269			`// WB Error`
270			`//`
271	14	lampret	`ifdef GPIO_FULL_DECODE
272			`ifdef GPIO_STRICT_32BIT_ACCESS
273	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
274	14	lampret	`else
275	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`
276	14	lampret	`endif
277			`else
278			`ifdef GPIO_STRICT_32BIT_ACCESS
279	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
280	14	lampret	`else
281	17	lampret	`assign wb_err = 1'b0;`
282	14	lampret	`endif
283			`endif
284
285			`//`
286	17	lampret	`// Optional registration of WB error`
287	14	lampret	`//`
288	17	lampret	`ifdef GPIO_REGISTERED_WB_OUTPUTS
289			`always @(posedge wb_clk_i or posedge wb_rst_i)`
290			`if (wb_rst_i)`
291			`wb_err_o <= #1 1'b0;`
292			`else`
293	23	lampret	`wb_err_o <= #1 wb_err & ~wb_err_o;`
294	17	lampret	`else
295			`assign wb_err_o = wb_err;`
296			`endif
297	14	lampret
298			`//`
299			`// Full address decoder`
300			`//`
301			`ifdef GPIO_FULL_DECODE
302			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
303			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
304			`else
305			`assign full_decoding = 1'b1;`
306			`endif
307
308			`//`
309			`// GPIO registers address decoder`
310			`//`
311			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
312			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
313			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
314			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
315			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
316			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
317	21	lampret	assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
318	14	lampret
319			`//`
320			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
321			`//`
322			`ifdef GPIO_RGPIO_CTRL
323			`always @(posedge wb_clk_i or posedge wb_rst_i)`
324			`if (wb_rst_i)`
325			`rgpio_ctrl <= #1 4'b0;`
326			`else if (rgpio_ctrl_sel && wb_we_i)`
327			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
328			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
329	21	lampret	rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;
330	14	lampret	`else
331			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
332			`endif
333
334			`//`
335			`// Write to RGPIO_OUT`
336			`//`
337			`ifdef GPIO_RGPIO_OUT
338			`always @(posedge wb_clk_i or posedge wb_rst_i)`
339			`if (wb_rst_i)`
340			`rgpio_out <= #1 {gw{1'b0}};`
341			`else if (rgpio_out_sel && wb_we_i)`
342			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
343			`else
344	17	lampret	assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
345	14	lampret	`endif
346
347			`//`
348	17	lampret	`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`
349	14	lampret	`//`
350			`ifdef GPIO_RGPIO_OE
351			`always @(posedge wb_clk_i or posedge wb_rst_i)`
352			`if (wb_rst_i)`
353			`rgpio_oe <= #1 {gw{1'b0}};`
354			`else if (rgpio_oe_sel && wb_we_i)`
355	17	lampret	`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`
356	14	lampret	`else
357			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
358			`endif
359
360			`//`
361			`// Write to RGPIO_INTE`
362			`//`
363			`ifdef GPIO_RGPIO_INTE
364			`always @(posedge wb_clk_i or posedge wb_rst_i)`
365			`if (wb_rst_i)`
366			`rgpio_inte <= #1 {gw{1'b0}};`
367			`else if (rgpio_inte_sel && wb_we_i)`
368			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
369			`else
370			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
371			`endif
372
373			`//`
374			`// Write to RGPIO_PTRIG`
375			`//`
376			`ifdef GPIO_RGPIO_PTRIG
377			`always @(posedge wb_clk_i or posedge wb_rst_i)`
378			`if (wb_rst_i)`
379			`rgpio_ptrig <= #1 {gw{1'b0}};`
380			`else if (rgpio_ptrig_sel && wb_we_i)`
381			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
382			`else
383			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
384			`endif
385
386			`//`
387			`// Write to RGPIO_AUX`
388			`//`
389			`ifdef GPIO_RGPIO_AUX
390			`always @(posedge wb_clk_i or posedge wb_rst_i)`
391			`if (wb_rst_i)`
392			`rgpio_aux <= #1 {gw{1'b0}};`
393			`else if (rgpio_aux_sel && wb_we_i)`
394			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
395			`else
396			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
397			`endif
398
399			`//`
400			`// Latch into RGPIO_IN`
401			`//`
402			`ifdef GPIO_RGPIO_IN
403	17	lampret	`always @(posedge wb_clk_i or posedge wb_rst_i)`
404	14	lampret	`if (wb_rst_i)`
405			`rgpio_in <= #1 {gw{1'b0}};`
406			`else`
407	17	lampret	`rgpio_in <= #1 in_muxed;`
408	14	lampret	`else
409	17	lampret	`assign rgpio_in = in_muxed;`
410	14	lampret	`endif
411
412			`//`
413	17	lampret	`// Mux inputs directly from input pads with inputs sampled by external clock`
414	14	lampret	`//`
415	25	lampret	assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
416	17	lampret
417			`//`
418			`// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.`
419			`// If negedge flops are allowed, pext_clk only clocks posedge flops.`
420			`//`
421			`ifdef GPIO_NO_NEGEDGE_FLOPS
422	25	lampret	assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
423	17	lampret	`else
424	25	lampret	`assign pext_clk = clk_pad_i;`
425	17	lampret	`endif
426
427			`//`
428			`// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.`
429			`//`
430			`ifdef GPIO_NO_NEGEDGE_FLOPS
431			`assign extc_in = pextc_sampled;`
432			`else
433			assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
434			`endif
435
436			`//`
437			`// Latch using posedge external clock`
438			`//`
439			`always @(posedge pext_clk or posedge wb_rst_i)`
440			`if (wb_rst_i)`
441			`pextc_sampled <= #1 {gw{1'b0}};`
442			`else`
443	25	lampret	`pextc_sampled <= #1 ext_pad_i;`
444	17	lampret
445			`//`
446			`// Latch using negedge external clock`
447			`//`
448			`ifdef GPIO_NO_NEGEDGE_FLOPS
449			`else
450	25	lampret	`always @(negedge clk_pad_i or posedge wb_rst_i)`
451	17	lampret	`if (wb_rst_i)`
452			`nextc_sampled <= #1 {gw{1'b0}};`
453			`else`
454	25	lampret	`nextc_sampled <= #1 ext_pad_i;`
455	17	lampret	`endif
456
457			`//`
458			`// Mux all registers when doing a read of GPIO registers`
459			`//`
460	14	lampret	`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
461	22	lampret	`rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)`
462	14	lampret	case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
463			`ifdef GPIO_READREGS
464			`GPIO_RGPIO_OUT: begin
465	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};`
466	14	lampret	`end`
467			`GPIO_RGPIO_OE: begin
468	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};`
469	14	lampret	`end`
470			`GPIO_RGPIO_INTE: begin
471	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};`
472	14	lampret	`end`
473			`GPIO_RGPIO_PTRIG: begin
474	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};`
475	14	lampret	`end`
476			`GPIO_RGPIO_AUX: begin
477	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};`
478	14	lampret	`end`
479			`GPIO_RGPIO_CTRL: begin
480	20	lampret	`wb_dat[3:0] = rgpio_ctrl;`
481			`wb_dat[dw-1:4] = {dw-4{1'b0}};`
482	14	lampret	`end`
483			`endif
484	21	lampret	`GPIO_RGPIO_INTS: begin
485			`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};`
486			`end`
487	14	lampret	`default: begin`
488	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};`
489	14	lampret	`end`
490			`endcase`
491
492			`//`
493	17	lampret	`// WB data output`
494			`//`
495			`ifdef GPIO_REGISTERED_WB_OUTPUTS
496			`always @(posedge wb_clk_i or posedge wb_rst_i)`
497			`if (wb_rst_i)`
498			`wb_dat_o <= #1 {dw{1'b0}};`
499			`else`
500			`wb_dat_o <= #1 wb_dat;`

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