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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2002/03/13 20:56:28  lampret
// Removed zero padding as per Avi Shamli suggestion.
//
// Revision 1.10  2002/03/13 20:47:57  lampret
// Ports changed per Ran Aviram suggestions.
//
// Revision 1.9  2002/03/09 03:43:27  lampret
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
//
// Revision 1.8  2002/01/14 19:06:28  lampret
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
//
// Revision 1.7  2001/12/25 17:21:21  lampret
// Fixed two typos.
//
// Revision 1.6  2001/12/25 17:12:35  lampret
// Added RGPIO_INTS.
//
// Revision 1.5  2001/12/12 20:35:53  lampret
// Fixing style.
//
// Revision 1.4  2001/12/12 07:12:58  lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
// Revision 1.3  2001/11/15 02:24:37  lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.2  2001/10/31 02:26:51  lampret
// Fixed wb_err_o.
//
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] ext_pad_i;      // GPIO Inputs
input                   clk_pad_i;      // GPIO Eclk
output  [gw-1:0] ext_pad_o;      // GPIO Outputs
output  [gw-1:0] ext_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
`else
wire    [gw-1:0] rgpio_ints;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    rgpio_ints_sel; // RGPIO_INTS select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
wire    [gw-1:0] in_muxed;       // Muxed inputs
wire                    wb_ack;         // WB Acknowledge
wire                    wb_err;         // WB Error
wire                    wb_inta;        // WB Interrupt
reg     [dw-1:0] wb_dat;         // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg                     wb_ack_o;       // WB Acknowledge
reg                     wb_err_o;       // WB Error
reg                     wb_inta_o;      // WB Interrupt
reg     [dw-1:0] wb_dat_o;       // WB Data out
`endif
wire    [gw-1:0] out_pad;        // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg     [gw-1:0] ext_pad_o;      // GPIO Outputs
`endif
wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock
wire                    pext_clk;       // External clock for posedge flops
reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs
`endif
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
 
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
 
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_ack & ~wb_ack_o;
`else
assign wb_ack_o = wb_ack;
`endif
 
//
// WB Error
//
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
`endif
`endif
 
//
// Optional registration of WB error
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & ~wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
assign pext_clk = clk_pad_i;
`else
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
`endif
`else
assign pext_clk = clk_pad_i;
`endif
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
`endif
 
//
// Latch using posedge external clock
//
always @(posedge pext_clk or posedge wb_rst_i)
        if (wb_rst_i)
                pextc_sampled <= #1 {gw{1'b0}};
        else
                pextc_sampled <= #1 ext_pad_i;
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge clk_pad_i or posedge wb_rst_i)
        if (wb_rst_i)
                nextc_sampled <= #1 {gw{1'b0}};
        else
                nextc_sampled <= #1 ext_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat[dw-1:0] = rgpio_out;
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat[dw-1:0] = ~rgpio_oe;
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat[dw-1:0] = rgpio_inte;
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat[dw-1:0] = rgpio_ptrig;
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat[dw-1:0] = rgpio_aux;
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat[3:0] = rgpio_ctrl;
                        wb_dat[dw-1:4] = {dw-4{1'b0}};
                end
`endif
                `GPIO_RGPIO_INTS: begin
                        wb_dat[dw-1:0] = rgpio_ints;
                end
                default: begin
                        wb_dat[dw-1:0] = rgpio_in;
                end
        endcase
 
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else
                wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
 
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ints <= #1 {gw{1'b0}};
        else if (rgpio_ints_sel && wb_we_i)
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != ext_pad_i)
                rgpio_ints <= #1 (rgpio_ints | (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
`else
assign rgpio_ints = (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_inta_o <= #1 1'b0;
        else
                wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
 
//
// Output enables are RGPIO_OE bits
//
assign ext_padoen_o = rgpio_oe;
 
//
// Generate GPIO outputs
//
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                ext_pad_o <= #1 {gw{1'b0}};
        else
                ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign ext_padoen_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	29	lampret	`// Revision 1.11 2002/03/13 20:56:28 lampret`
49			`// Removed zero padding as per Avi Shamli suggestion.`
50			`//`
51	26	lampret	`// Revision 1.10 2002/03/13 20:47:57 lampret`
52			`// Ports changed per Ran Aviram suggestions.`
53			`//`
54	25	lampret	`// Revision 1.9 2002/03/09 03:43:27 lampret`
55			`// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)`
56			`//`
57	24	lampret	`// Revision 1.8 2002/01/14 19:06:28 lampret`
58			`// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.`
59			`//`
60	23	lampret	`// Revision 1.7 2001/12/25 17:21:21 lampret`
61			`// Fixed two typos.`
62			`//`
63	22	lampret	`// Revision 1.6 2001/12/25 17:12:35 lampret`
64			`// Added RGPIO_INTS.`
65			`//`
66	21	lampret	`// Revision 1.5 2001/12/12 20:35:53 lampret`
67			`// Fixing style.`
68			`//`
69	20	lampret	`// Revision 1.4 2001/12/12 07:12:58 lampret`
70			`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`
71			`//`
72	19	lampret	`// Revision 1.3 2001/11/15 02:24:37 lampret`
73			`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
74			`//`
75	17	lampret	`// Revision 1.2 2001/10/31 02:26:51 lampret`
76			`// Fixed wb_err_o.`
77			`//`
78	15	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
79			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
80			`//`
81	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
82			`// Changed directory structure, port names and drfines.`
83			`//`
84			`// Revision 1.2 2001/07/14 20:39:26 lampret`
85			`// Better configurability.`
86			`//`
87			`// Revision 1.1 2001/06/05 07:45:26 lampret`
88			`// Added initial RTL and test benches. There are still some issues with these files.`
89			`//`
90			`//`
91
92			`// synopsys translate_off`
93			`include "timescale.v"
94			`// synopsys translate_on`
95			`include "gpio_defines.v"
96
97			`module gpio_top(`
98			`// WISHBONE Interface`
99			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
100			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
101
102			`// Auxiliary inputs interface`
103			`aux_i,`
104
105			`// External GPIO Interface`
106	25	lampret	`ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o`
107	14	lampret	`);`
108
109			`parameter dw = 32;`
110			parameter aw = `GPIO_ADDRHH+1;
111			parameter gw = `GPIO_IOS;
112
113			`//`
114			`// WISHBONE Interface`
115			`//`
116			`input wb_clk_i; // Clock`
117			`input wb_rst_i; // Reset`
118			`input wb_cyc_i; // cycle valid input`
119			`input [aw-1:0] wb_adr_i; // address bus inputs`
120			`input [dw-1:0] wb_dat_i; // input data bus`
121			`input [3:0] wb_sel_i; // byte select inputs`
122			`input wb_we_i; // indicates write transfer`
123			`input wb_stb_i; // strobe input`
124			`output [dw-1:0] wb_dat_o; // output data bus`
125			`output wb_ack_o; // normal termination`
126			`output wb_err_o; // termination w/ error`
127			`output wb_inta_o; // Interrupt request output`
128
129			`// Auxiliary Inputs Interface`
130			`input [gw-1:0] aux_i; // Auxiliary inputs`
131
132			`//`
133			`// External GPIO Interface`
134			`//`
135	25	lampret	`input [gw-1:0] ext_pad_i; // GPIO Inputs`
136			`input clk_pad_i; // GPIO Eclk`
137			`output [gw-1:0] ext_pad_o; // GPIO Outputs`
138			`output [gw-1:0] ext_padoen_o; // GPIO output drivers enables`
139	14	lampret
140			`ifdef GPIO_IMPLEMENTED
141
142			`//`
143			`// GPIO Input Register (or no register)`
144			`//`
145			`ifdef GPIO_RGPIO_IN
146			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
147			`else
148			`wire [gw-1:0] rgpio_in; // No register`
149			`endif
150
151			`//`
152			`// GPIO Output Register (or no register)`
153			`//`
154			`ifdef GPIO_RGPIO_OUT
155			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
156			`else
157			`wire [gw-1:0] rgpio_out; // No register`
158			`endif
159
160			`//`
161			`// GPIO Output Driver Enable Register (or no register)`
162			`//`
163			`ifdef GPIO_RGPIO_OE
164			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
165			`else
166			`wire [gw-1:0] rgpio_oe; // No register`
167			`endif
168
169			`//`
170			`// GPIO Interrupt Enable Register (or no register)`
171			`//`
172			`ifdef GPIO_RGPIO_INTE
173			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
174			`else
175			`wire [gw-1:0] rgpio_inte; // No register`
176			`endif
177
178			`//`
179			`// GPIO Positive edge Triggered Register (or no register)`
180			`//`
181			`ifdef GPIO_RGPIO_PTRIG
182			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
183			`else
184			`wire [gw-1:0] rgpio_ptrig; // No register`
185			`endif
186
187			`//`
188			`// GPIO Auxiliary select Register (or no register)`
189			`//`
190			`ifdef GPIO_RGPIO_AUX
191			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
192			`else
193			`wire [gw-1:0] rgpio_aux; // No register`
194			`endif
195
196			`//`
197			`// GPIO Control Register (or no register)`
198			`//`
199			`ifdef GPIO_RGPIO_CTRL
200			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
201			`else
202			`wire [3:0] rgpio_ctrl; // No register`
203			`endif
204
205			`//`
206	21	lampret	`// GPIO Interrupt Status Register (or no register)`
207			`//`
208			`ifdef GPIO_RGPIO_INTS
209			`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`
210			`else
211			`wire [gw-1:0] rgpio_ints; // No register`
212			`endif
213
214			`//`
215	14	lampret	`// Internal wires & regs`
216			`//`
217			`wire rgpio_out_sel; // RGPIO_OUT select`
218			`wire rgpio_oe_sel; // RGPIO_OE select`
219			`wire rgpio_inte_sel; // RGPIO_INTE select`
220			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
221			`wire rgpio_aux_sel; // RGPIO_AUX select`
222			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
223	21	lampret	`wire rgpio_ints_sel; // RGPIO_INTS select`
224	14	lampret	`wire latch_clk; // Latch clock`
225			`wire full_decoding; // Full address decoding qualification`
226	17	lampret	`wire [gw-1:0] in_muxed; // Muxed inputs`
227			`wire wb_ack; // WB Acknowledge`
228			`wire wb_err; // WB Error`
229			`wire wb_inta; // WB Interrupt`
230			`reg [dw-1:0] wb_dat; // WB Data out`
231			`ifdef GPIO_REGISTERED_WB_OUTPUTS
232			`reg wb_ack_o; // WB Acknowledge`
233			`reg wb_err_o; // WB Error`
234			`reg wb_inta_o; // WB Interrupt`
235			`reg [dw-1:0] wb_dat_o; // WB Data out`
236			`endif
237			`wire [gw-1:0] out_pad; // GPIO Outputs`
238			`ifdef GPIO_REGISTERED_IO_OUTPUTS
239	25	lampret	`reg [gw-1:0] ext_pad_o; // GPIO Outputs`
240	17	lampret	`endif
241			`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`
242			`wire pext_clk; // External clock for posedge flops`
243			`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`
244			`ifdef GPIO_NO_NEGEDGE_FLOPS
245			`else
246			`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`
247			`endif
248	14	lampret
249			`//`
250			`// All WISHBONE transfer terminations are successful except when:`
251			`// a) full address decoding is enabled and address doesn't match`
252			`// any of the GPIO registers`
253			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
254			`//`
255	17	lampret
256			`//`
257			`// WB Acknowledge`
258			`//`
259			`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`
260
261			`//`
262			`// Optional registration of WB Ack`
263			`//`
264			`ifdef GPIO_REGISTERED_WB_OUTPUTS
265			`always @(posedge wb_clk_i or posedge wb_rst_i)`
266			`if (wb_rst_i)`
267			`wb_ack_o <= #1 1'b0;`
268			`else`
269	23	lampret	`wb_ack_o <= #1 wb_ack & ~wb_ack_o;`
270	17	lampret	`else
271			`assign wb_ack_o = wb_ack;`
272			`endif
273
274			`//`
275			`// WB Error`
276			`//`
277	14	lampret	`ifdef GPIO_FULL_DECODE
278			`ifdef GPIO_STRICT_32BIT_ACCESS
279	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
280	14	lampret	`else
281	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`
282	14	lampret	`endif
283			`else
284			`ifdef GPIO_STRICT_32BIT_ACCESS
285	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
286	14	lampret	`else
287	17	lampret	`assign wb_err = 1'b0;`
288	14	lampret	`endif
289			`endif
290
291			`//`
292	17	lampret	`// Optional registration of WB error`
293	14	lampret	`//`
294	17	lampret	`ifdef GPIO_REGISTERED_WB_OUTPUTS
295			`always @(posedge wb_clk_i or posedge wb_rst_i)`
296			`if (wb_rst_i)`
297			`wb_err_o <= #1 1'b0;`
298			`else`
299	23	lampret	`wb_err_o <= #1 wb_err & ~wb_err_o;`
300	17	lampret	`else
301			`assign wb_err_o = wb_err;`
302			`endif
303	14	lampret
304			`//`
305			`// Full address decoder`
306			`//`
307			`ifdef GPIO_FULL_DECODE
308			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
309			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
310			`else
311			`assign full_decoding = 1'b1;`
312			`endif
313
314			`//`
315			`// GPIO registers address decoder`
316			`//`
317			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
318			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
319			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
320			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
321			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
322			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
323	21	lampret	assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
324	14	lampret
325			`//`
326			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
327			`//`
328			`ifdef GPIO_RGPIO_CTRL
329			`always @(posedge wb_clk_i or posedge wb_rst_i)`
330			`if (wb_rst_i)`
331			`rgpio_ctrl <= #1 4'b0;`
332			`else if (rgpio_ctrl_sel && wb_we_i)`
333			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
334			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
335	21	lampret	rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;
336	14	lampret	`else
337			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
338			`endif
339
340			`//`
341			`// Write to RGPIO_OUT`
342			`//`
343			`ifdef GPIO_RGPIO_OUT
344			`always @(posedge wb_clk_i or posedge wb_rst_i)`
345			`if (wb_rst_i)`
346			`rgpio_out <= #1 {gw{1'b0}};`
347			`else if (rgpio_out_sel && wb_we_i)`
348			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
349			`else
350	17	lampret	assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
351	14	lampret	`endif
352
353			`//`
354	17	lampret	`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`
355	14	lampret	`//`
356			`ifdef GPIO_RGPIO_OE
357			`always @(posedge wb_clk_i or posedge wb_rst_i)`
358			`if (wb_rst_i)`
359			`rgpio_oe <= #1 {gw{1'b0}};`
360			`else if (rgpio_oe_sel && wb_we_i)`
361	17	lampret	`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`
362	14	lampret	`else
363			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
364			`endif
365
366			`//`
367			`// Write to RGPIO_INTE`
368			`//`
369			`ifdef GPIO_RGPIO_INTE
370			`always @(posedge wb_clk_i or posedge wb_rst_i)`
371			`if (wb_rst_i)`
372			`rgpio_inte <= #1 {gw{1'b0}};`
373			`else if (rgpio_inte_sel && wb_we_i)`
374			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
375			`else
376			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
377			`endif
378
379			`//`
380			`// Write to RGPIO_PTRIG`
381			`//`
382			`ifdef GPIO_RGPIO_PTRIG
383			`always @(posedge wb_clk_i or posedge wb_rst_i)`
384			`if (wb_rst_i)`
385			`rgpio_ptrig <= #1 {gw{1'b0}};`
386			`else if (rgpio_ptrig_sel && wb_we_i)`
387			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
388			`else
389			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
390			`endif
391
392			`//`
393			`// Write to RGPIO_AUX`
394			`//`
395			`ifdef GPIO_RGPIO_AUX
396			`always @(posedge wb_clk_i or posedge wb_rst_i)`
397			`if (wb_rst_i)`
398			`rgpio_aux <= #1 {gw{1'b0}};`
399			`else if (rgpio_aux_sel && wb_we_i)`
400			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
401			`else
402			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
403			`endif
404
405			`//`
406			`// Latch into RGPIO_IN`
407			`//`
408			`ifdef GPIO_RGPIO_IN
409	17	lampret	`always @(posedge wb_clk_i or posedge wb_rst_i)`
410	14	lampret	`if (wb_rst_i)`
411			`rgpio_in <= #1 {gw{1'b0}};`
412			`else`
413	17	lampret	`rgpio_in <= #1 in_muxed;`
414	14	lampret	`else
415	17	lampret	`assign rgpio_in = in_muxed;`
416	14	lampret	`endif
417
418			`//`
419	17	lampret	`// Mux inputs directly from input pads with inputs sampled by external clock`
420	14	lampret	`//`
421	25	lampret	assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
422	17	lampret
423			`//`
424			`// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.`
425			`// If negedge flops are allowed, pext_clk only clocks posedge flops.`
426			`//`
427			`ifdef GPIO_NO_NEGEDGE_FLOPS
428	29	lampret	`ifdef GPIO_NO_CLKPAD_LOGIC
429			`assign pext_clk = clk_pad_i;`
430			`else
431	25	lampret	assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
432	29	lampret	`endif
433	17	lampret	`else
434	25	lampret	`assign pext_clk = clk_pad_i;`
435	17	lampret	`endif
436
437			`//`
438			`// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.`
439			`//`
440			`ifdef GPIO_NO_NEGEDGE_FLOPS
441			`assign extc_in = pextc_sampled;`
442			`else
443			assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
444			`endif
445
446			`//`
447			`// Latch using posedge external clock`
448			`//`
449			`always @(posedge pext_clk or posedge wb_rst_i)`
450			`if (wb_rst_i)`
451			`pextc_sampled <= #1 {gw{1'b0}};`
452			`else`
453	25	lampret	`pextc_sampled <= #1 ext_pad_i;`
454	17	lampret
455			`//`
456			`// Latch using negedge external clock`
457			`//`
458			`ifdef GPIO_NO_NEGEDGE_FLOPS
459			`else
460	25	lampret	`always @(negedge clk_pad_i or posedge wb_rst_i)`
461	17	lampret	`if (wb_rst_i)`
462			`nextc_sampled <= #1 {gw{1'b0}};`
463			`else`
464	25	lampret	`nextc_sampled <= #1 ext_pad_i;`
465	17	lampret	`endif
466
467			`//`
468			`// Mux all registers when doing a read of GPIO registers`
469			`//`
470	14	lampret	`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
471	22	lampret	`rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)`
472	14	lampret	case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
473			`ifdef GPIO_READREGS
474			`GPIO_RGPIO_OUT: begin
475	26	lampret	`wb_dat[dw-1:0] = rgpio_out;`
476	14	lampret	`end`
477			`GPIO_RGPIO_OE: begin
478	26	lampret	`wb_dat[dw-1:0] = ~rgpio_oe;`
479	14	lampret	`end`
480			`GPIO_RGPIO_INTE: begin
481	26	lampret	`wb_dat[dw-1:0] = rgpio_inte;`
482	14	lampret	`end`
483			`GPIO_RGPIO_PTRIG: begin
484	26	lampret	`wb_dat[dw-1:0] = rgpio_ptrig;`
485	14	lampret	`end`
486			`GPIO_RGPIO_AUX: begin
487	26	lampret	`wb_dat[dw-1:0] = rgpio_aux;`
488	14	lampret	`end`
489			`GPIO_RGPIO_CTRL: begin
490	20	lampret	`wb_dat[3:0] = rgpio_ctrl;`
491			`wb_dat[dw-1:4] = {dw-4{1'b0}};`
492	14	lampret	`end`
493			`endif
494	21	lampret	`GPIO_RGPIO_INTS: begin
495	26	lampret	`wb_dat[dw-1:0] = rgpio_ints;`
496	21	lampret	`end`
497	14	lampret	`default: begin`
498	26	lampret	`wb_dat[dw-1:0] = rgpio_in;`
499	14	lampret	`end`
500			`endcase`

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