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[/] [gpio/] [tags/] [rel_7/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 8

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  GPIO Testbench Tasks                                        ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Testbench tasks.                                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/14 20:37:23  lampret
// Test bench improvements.
//
// Revision 1.1  2001/06/05 07:45:22  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.v"
`include "defines.v"
`include "tb_defines.v"
 
module tb_tasks;
 
integer nr_failed;
integer ints_disabled;
integer ints_working;
integer local_errs;
 
parameter sh_addr = `GPIO_ADDRLH+1;
 
//
// Count/report failed tests
//
task failed;
begin
        $display("FAILED !!!");
        nr_failed = nr_failed + 1;
end
endtask
 
//
// Set RGPIO_OUT register
//
task setout;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_OE register
//
task setoe;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_INTE register
//
task setinte;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_PTRIG register
//
task setptrig;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_AUX register
//
task setaux;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_CTRL register
//
task setctrl;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Display RGPIO_IN register
//
task showin;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
        $write(" RGPIO_IN: %h", tmp);
end
 
endtask
 
//
// Display RGPIO_OUT register
//
task showout;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
        $write(" RGPIO_OUT: %h", tmp);
end
 
endtask
 
 
//
// Display RGPIO_OE register
//
task showoe;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
        $write(" RGPIO_OE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_INTE register
//
task showinte;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
        $write(" RGPIO_INTE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_PTRIG register
//
task showptrig;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
        $write(" RGPIO_PTRIG:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_AUX register
//
task showaux;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
        $write(" RGPIO_AUX:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_CTRL register
//
task showctrl;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
        $write(" RGPIO_CTRL: %h", tmp);
end
 
endtask
 
//
// Compare parameter with RGPIO_IN register
//
task comp_in;
input   [31:0]   val;
output          ret;
 
reg     [31:0]   tmp;
reg             ret;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
 
        if (tmp == val)
                ret = 1;
        else
                ret = 0;
end
 
endtask
 
//
// Get RGPIO_IN register
//
task getin;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OUT register
//
task getout;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OE register
//
task getoe;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_INTE register
//
task getinte;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_PTRIG register
//
task getptrig;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_AUX register
//
task getaux;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_CTRL register
//
task getctrl;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
end
 
endtask
 
//
// Calculate a random and make it narrow to fit on GPIO I/O pins
//
task random_gpio;
output  [31:0]   tmp;
 
begin
        tmp = $random & ((1<<`GPIO_IOS)-1);
end
 
endtask
 
//
// Test operation of control bit RGPIO_CTRL[ECLK]
//
task test_eclk;
integer         l1, l2, l3;
integer         r1, r2;
begin
 
        //
        // Phase 1
        //
        // GPIO uses WISHBONE clock to latch gpio_in
        //
 
        // Put something on gpio_in pins
        random_gpio(r1);
        tb_top.gpio_mon.set_gpioin(r1);
 
        // Reset GPIO_CTRL
        setctrl(0);
 
        // Wait for time to advance
        #1000;
 
        // Read GPIO_RGPIO_IN
        getin(l1);
 
        //
        // Phase 2
        //
        // GPIO uses external clock to latch gpio_in
        //
 
        // Set GPIO to use external clock
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
 
        // Put something else on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Wait for time to advance
        #1000;
 
        // Read GPIO_RGPIO_IN (should be the same as l1)
        getin(l2);
 
        // Make an external clock
        tb_top.gpio_mon.set_gpioeclk(0);
        #10;
        tb_top.gpio_mon.set_gpioeclk(1);
        #10;
 
        // Read RGPIO_IN (should be different than l2)
        getin(l3);
 
        //
        // Phase 3
        //
        // Compare phases
        //
        if (l1 == l2 && l2 == r1 && l3 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test operation of control bit RGPIO_CTRL[NEC]
//
task test_nec;
integer         l1, l2;
integer         r2;
begin
        //
        // Phase 1
        //
        // Compare RGPIO_IN before and after negative edge
        //
 
        // Clear GPIO_RGPIO_IN
        tb_top.gpio_mon.set_gpioin('d0);
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        // Advance time
        #1000;
 
        // Set GPIO to use external clock and set RGPIO_CTRL[NEC]
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
 
        // Put something on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Wait for time to advance
        #1000;
 
        // Read RGPIO_IN
        getin(l1);
 
        // Make an external clock
        tb_top.gpio_mon.set_gpioeclk(1);
        #10;
        tb_top.gpio_mon.set_gpioeclk(0);
        #10;
 
        // Read RGPIO_IN (should be different than l1)
        getin(l2);
 
        //
        // Phase 2
        //
        // Compare phases
        //
        if (!l1 && l2 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test input polled mode, output mode and bidirectional
//
task test_simple;
integer         l1, l2, l3, l4;
integer         i, err;
begin
        $write("  Testing input mode ...");
 
        //
        // Phase 1
        //
        // Compare RGPIO_IN and gpio_in
        //
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_in pins
                random_gpio(l1);
                tb_top.gpio_mon.set_gpioin(l1);
 
                // Advance time
                #1000;
 
                // Read GPIO_RGPIO_IN
                getin(l2);
 
                // Compare gpio_in and RGPIO_IN. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 2
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing output mode ...");
 
        //
        // Phase 3
        //
        // Compare RGPIO_OUT and gpio_out
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OUT pins
                l1 = $random;
                setout(l1);
 
                // Advance time
                #1000;
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l2);
 
                // Compare gpio_out and RGPIO_OUT. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 4
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing bidirectional I/O ...");
 
        //
        // Phase 5
        //
        // Compare RGPIO_OE and gpio_oen
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OE pins
                l1 = $random;
                setoe(l1);
 
                // Advance time
                #1000;
 
                // Read gpio_oen
                tb_top.gpio_mon.get_gpiooen(l2);
 
                // Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
                if (l1 != ~l2)
                        err = err + 1;
        end
 
        // Phase 6
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing auxiliary feature ...");
 
        //
        // Phase 7
        //
        // Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_aux pins
                l1 = $random;
                tb_top.gpio_mon.set_gpioaux(l1);
 
                // Put something in RGPIO_AUX pins
                l2 = $random;
                setaux(l2);
 
                // Put something in RGPIO_OUT pins
                l3 = $random;
                setout(l3);
 
                // Advance time
                #1000;
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l4);
 
                // Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
                // RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT 
                // bits are present on gpio_out and where
                if ((l1 & l2 | l3 & ~l2) != l4)
                        err = err + 1;
        end
 
        // Phase 8
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
end
endtask
 
//
// Test interrupts
//
task test_ints;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
 
        $write("  Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set gpio_in pins
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
                tb_top.gpio_mon.set_gpioin(r1);
 
                // Low level triggering
                setptrig(0);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Test ptrig
//
task test_ptrig;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
        $write("  Testing ptrig features ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set bits to one
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
                // Set gpio_in pins
                tb_top.gpio_mon.set_gpioin('h00000000);
 
                // High level triggering
                setptrig('hffffffff);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin('hffffffff);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Do continues check for interrupts
//
always @(posedge tb_top.gpio.wb_inta_o)
        if (ints_disabled) begin
                $display("Spurious interrupt detected. ");
                failed;
                ints_working = 9876;
                $display;
        end
 
//
// Start of testbench test tasks
//
integer         i;
initial begin
`ifdef DUMP_VCD
        $dumpfile("../sim/tb_top.vcd");
        $dumpvars(0);
`endif
        nr_failed = 0;
        ints_disabled = 1;
        ints_working = 0;
        tb_top.gpio_mon.set_gpioin(0);
        tb_top.gpio_mon.set_gpioaux(0);
        tb_top.gpio_mon.set_gpioeclk(0);
        $display;
        $display("###");
        $display("### GPIO IP Core Verification ###");
        $display("###");
        $display;
        $display("I. Testing correct operation of RGPIO_CTRL control bits");
        $display;
 
 
        $write("  Testing control bit RGPIO_CTRL[ECLK] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_eclk;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
 
        $write("  Testing control bit RGPIO_CTRL[NEC] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_nec;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
        test_ints;
 
        $display;
        $display("II. Testing modes of operation ...");
        $display;
 
        test_simple;
        test_ptrig;
 
        $display;
        $display("###");
        $display("### FAILED TESTS: %d ###", nr_failed);
        $display("###");
        $display;
        $finish;
end
 
endmodule

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Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_7/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	8	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// GPIO Testbench Tasks ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Testbench tasks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2001/07/14 20:37:23 lampret`
48			`// Test bench improvements.`
49			`//`
50			`// Revision 1.1 2001/06/05 07:45:22 lampret`
51			`// Added initial RTL and test benches. There are still some issues with these files.`
52			`//`
53			`//`
54
55			`include "timescale.v"
56			`include "defines.v"
57			`include "tb_defines.v"
58
59			`module tb_tasks;`
60
61			`integer nr_failed;`
62			`integer ints_disabled;`
63			`integer ints_working;`
64			`integer local_errs;`
65
66			parameter sh_addr = `GPIO_ADDRLH+1;
67
68			`//`
69			`// Count/report failed tests`
70			`//`
71			`task failed;`
72			`begin`
73			`$display("FAILED !!!");`
74			`nr_failed = nr_failed + 1;`
75			`end`
76			`endtask`
77
78			`//`
79			`// Set RGPIO_OUT register`
80			`//`
81			`task setout;`
82			`input [31:0] val;`
83
84			`begin`
85			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
86			`end`
87
88			`endtask`
89
90			`//`
91			`// Set RGPIO_OE register`
92			`//`
93			`task setoe;`
94			`input [31:0] val;`
95
96			`begin`
97			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
98			`end`
99
100			`endtask`
101
102			`//`
103			`// Set RGPIO_INTE register`
104			`//`
105			`task setinte;`
106			`input [31:0] val;`
107
108			`begin`
109			#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
110			`end`
111
112			`endtask`
113
114			`//`
115			`// Set RGPIO_PTRIG register`
116			`//`
117			`task setptrig;`
118			`input [31:0] val;`
119
120			`begin`
121			#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
122			`end`
123
124			`endtask`
125
126			`//`
127			`// Set RGPIO_AUX register`
128			`//`
129			`task setaux;`
130			`input [31:0] val;`
131
132			`begin`
133			#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
134			`end`
135
136			`endtask`
137
138			`//`
139			`// Set RGPIO_CTRL register`
140			`//`
141			`task setctrl;`
142			`input [31:0] val;`
143
144			`begin`
145			#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
146			`end`
147
148			`endtask`
149
150			`//`
151			`// Display RGPIO_IN register`
152			`//`
153			`task showin;`
154
155			`reg [31:0] tmp;`
156			`begin`
157			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
158			`$write(" RGPIO_IN: %h", tmp);`
159			`end`
160
161			`endtask`
162
163			`//`
164			`// Display RGPIO_OUT register`
165			`//`
166			`task showout;`
167
168			`reg [31:0] tmp;`
169			`begin`
170			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
171			`$write(" RGPIO_OUT: %h", tmp);`
172			`end`
173
174			`endtask`
175
176
177			`//`
178			`// Display RGPIO_OE register`
179			`//`
180			`task showoe;`
181
182			`reg [31:0] tmp;`
183			`begin`
184			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
185			`$write(" RGPIO_OE:%h", tmp);`
186			`end`
187
188			`endtask`
189
190			`//`
191			`// Display RGPIO_INTE register`
192			`//`
193			`task showinte;`
194
195			`reg [31:0] tmp;`
196			`begin`
197			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
198			`$write(" RGPIO_INTE:%h", tmp);`
199			`end`
200
201			`endtask`
202
203			`//`
204			`// Display RGPIO_PTRIG register`
205			`//`
206			`task showptrig;`
207
208			`reg [31:0] tmp;`
209			`begin`
210			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
211			`$write(" RGPIO_PTRIG:%h", tmp);`
212			`end`
213
214			`endtask`
215
216			`//`
217			`// Display RGPIO_AUX register`
218			`//`
219			`task showaux;`
220
221			`reg [31:0] tmp;`
222			`begin`
223			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
224			`$write(" RGPIO_AUX:%h", tmp);`
225			`end`
226
227			`endtask`
228
229			`//`
230			`// Display RGPIO_CTRL register`
231			`//`
232			`task showctrl;`
233
234			`reg [31:0] tmp;`
235			`begin`
236			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
237			`$write(" RGPIO_CTRL: %h", tmp);`
238			`end`
239
240			`endtask`
241
242			`//`
243			`// Compare parameter with RGPIO_IN register`
244			`//`
245			`task comp_in;`
246			`input [31:0] val;`
247			`output ret;`
248
249			`reg [31:0] tmp;`
250			`reg ret;`
251			`begin`
252			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
253
254			`if (tmp == val)`
255			`ret = 1;`
256			`else`
257			`ret = 0;`
258			`end`
259
260			`endtask`
261
262			`//`
263			`// Get RGPIO_IN register`
264			`//`
265			`task getin;`
266			`output [31:0] tmp;`
267
268			`begin`
269			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
270			`end`
271
272			`endtask`
273
274			`//`
275			`// Get RGPIO_OUT register`
276			`//`
277			`task getout;`
278			`output [31:0] tmp;`
279
280			`begin`
281			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
282			`end`
283
284			`endtask`
285
286			`//`
287			`// Get RGPIO_OE register`
288			`//`
289			`task getoe;`
290			`output [31:0] tmp;`
291
292			`begin`
293			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
294			`end`
295
296			`endtask`
297
298			`//`
299			`// Get RGPIO_INTE register`
300			`//`
301			`task getinte;`
302			`output [31:0] tmp;`
303
304			`begin`
305			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
306			`end`
307
308			`endtask`
309
310			`//`
311			`// Get RGPIO_PTRIG register`
312			`//`
313			`task getptrig;`
314			`output [31:0] tmp;`
315
316			`begin`
317			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
318			`end`
319
320			`endtask`
321
322			`//`
323			`// Get RGPIO_AUX register`
324			`//`
325			`task getaux;`
326			`output [31:0] tmp;`
327
328			`begin`
329			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
330			`end`
331
332			`endtask`
333
334			`//`
335			`// Get RGPIO_CTRL register`
336			`//`
337			`task getctrl;`
338			`output [31:0] tmp;`
339
340			`begin`
341			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
342			`end`
343
344			`endtask`
345
346			`//`
347			`// Calculate a random and make it narrow to fit on GPIO I/O pins`
348			`//`
349			`task random_gpio;`
350			`output [31:0] tmp;`
351
352			`begin`
353			tmp = $random & ((1<<`GPIO_IOS)-1);
354			`end`
355
356			`endtask`
357
358			`//`
359			`// Test operation of control bit RGPIO_CTRL[ECLK]`
360			`//`
361			`task test_eclk;`
362			`integer l1, l2, l3;`
363			`integer r1, r2;`
364			`begin`
365
366			`//`
367			`// Phase 1`
368			`//`
369			`// GPIO uses WISHBONE clock to latch gpio_in`
370			`//`
371
372			`// Put something on gpio_in pins`
373			`random_gpio(r1);`
374			`tb_top.gpio_mon.set_gpioin(r1);`
375
376			`// Reset GPIO_CTRL`
377			`setctrl(0);`
378
379			`// Wait for time to advance`
380			`#1000;`
381
382			`// Read GPIO_RGPIO_IN`
383			`getin(l1);`
384
385			`//`
386			`// Phase 2`
387			`//`
388			`// GPIO uses external clock to latch gpio_in`
389			`//`
390
391			`// Set GPIO to use external clock`
392			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
393
394			`// Put something else on gpio_in pins`
395			`random_gpio(r2);`
396			`tb_top.gpio_mon.set_gpioin(r2);`
397
398			`// Wait for time to advance`
399			`#1000;`
400
401			`// Read GPIO_RGPIO_IN (should be the same as l1)`
402			`getin(l2);`
403
404			`// Make an external clock`
405			`tb_top.gpio_mon.set_gpioeclk(0);`
406			`#10;`
407			`tb_top.gpio_mon.set_gpioeclk(1);`
408			`#10;`
409
410			`// Read RGPIO_IN (should be different than l2)`
411			`getin(l3);`
412
413			`//`
414			`// Phase 3`
415			`//`
416			`// Compare phases`
417			`//`
418			`if (l1 == l2 && l2 == r1 && l3 == r2)`
419			`$write(".");`
420			`else`
421			`local_errs = local_errs + 1;`
422			`end`
423			`endtask`
424
425			`//`
426			`// Test operation of control bit RGPIO_CTRL[NEC]`
427			`//`
428			`task test_nec;`
429			`integer l1, l2;`
430			`integer r2;`
431			`begin`
432			`//`
433			`// Phase 1`
434			`//`
435			`// Compare RGPIO_IN before and after negative edge`
436			`//`
437
438			`// Clear GPIO_RGPIO_IN`
439			`tb_top.gpio_mon.set_gpioin('d0);`
440
441			`// Set GPIO to use WB clock`
442			`setctrl(0);`
443
444			`// Advance time`
445			`#1000;`
446
447			`// Set GPIO to use external clock and set RGPIO_CTRL[NEC]`
448			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK \| 1 << `GPIO_RGPIO_CTRL_NEC);
449
450			`// Put something on gpio_in pins`
451			`random_gpio(r2);`
452			`tb_top.gpio_mon.set_gpioin(r2);`
453
454			`// Wait for time to advance`
455			`#1000;`
456
457			`// Read RGPIO_IN`
458			`getin(l1);`
459
460			`// Make an external clock`
461			`tb_top.gpio_mon.set_gpioeclk(1);`
462			`#10;`
463			`tb_top.gpio_mon.set_gpioeclk(0);`
464			`#10;`
465
466			`// Read RGPIO_IN (should be different than l1)`
467			`getin(l2);`
468
469			`//`
470			`// Phase 2`
471			`//`
472			`// Compare phases`
473			`//`
474			`if (!l1 && l2 == r2)`
475			`$write(".");`
476			`else`
477			`local_errs = local_errs + 1;`
478			`end`
479			`endtask`
480
481			`//`
482			`// Test input polled mode, output mode and bidirectional`
483			`//`
484			`task test_simple;`
485			`integer l1, l2, l3, l4;`
486			`integer i, err;`
487			`begin`
488			`$write(" Testing input mode ...");`
489
490			`//`
491			`// Phase 1`
492			`//`
493			`// Compare RGPIO_IN and gpio_in`
494			`//`
495
496			`// Set GPIO to use WB clock`
497			`setctrl(0);`
498
499			`err = 0;`
500			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
501			`// Put something on gpio_in pins`
502			`random_gpio(l1);`
503			`tb_top.gpio_mon.set_gpioin(l1);`
504
505			`// Advance time`
506			`#1000;`
507
508			`// Read GPIO_RGPIO_IN`
509			`getin(l2);`
510
511			`// Compare gpio_in and RGPIO_IN. Should be equal.`
512			`if (l1 != l2)`
513			`err = err + 1;`
514			`end`
515
516			`// Phase 2`
517			`//`
518			`// Output result for previous test`
519			`//`
520			`if (!err)`
521			`$display(" OK");`
522			`else`
523			`failed;`
524
525			`$write(" Testing output mode ...");`
526
527			`//`
528			`// Phase 3`
529			`//`
530			`// Compare RGPIO_OUT and gpio_out`
531			`//`
532
533			`err = 0;`
534			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
535			`// Put something in RGPIO_OUT pins`
536			`l1 = $random;`
537			`setout(l1);`
538
539			`// Advance time`
540			`#1000;`
541
542			`// Read gpio_out`
543			`tb_top.gpio_mon.get_gpioout(l2);`
544
545			`// Compare gpio_out and RGPIO_OUT. Should be equal.`
546			`if (l1 != l2)`
547			`err = err + 1;`
548			`end`
549
550			`// Phase 4`
551			`//`
552			`// Output result for previous test`
553			`//`
554			`if (!err)`
555			`$display(" OK");`
556			`else`
557			`failed;`
558
559			`$write(" Testing bidirectional I/O ...");`
560
561			`//`
562			`// Phase 5`
563			`//`
564			`// Compare RGPIO_OE and gpio_oen`
565			`//`
566
567			`err = 0;`
568			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
569			`// Put something in RGPIO_OE pins`
570			`l1 = $random;`
571			`setoe(l1);`
572
573			`// Advance time`
574			`#1000;`
575
576			`// Read gpio_oen`
577			`tb_top.gpio_mon.get_gpiooen(l2);`
578
579			`// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.`
580			`if (l1 != ~l2)`
581			`err = err + 1;`
582			`end`
583
584			`// Phase 6`
585			`//`
586			`// Output result for previous test`
587			`//`
588			`if (!err)`
589			`$display(" OK");`
590			`else`
591			`failed;`
592
593			`$write(" Testing auxiliary feature ...");`
594
595			`//`
596			`// Phase 7`
597			`//`
598			`// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux`
599			`//`
600
601			`err = 0;`
602			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
603			`// Put something on gpio_aux pins`
604			`l1 = $random;`
605			`tb_top.gpio_mon.set_gpioaux(l1);`
606
607			`// Put something in RGPIO_AUX pins`
608			`l2 = $random;`
609			`setaux(l2);`
610
611			`// Put something in RGPIO_OUT pins`
612			`l3 = $random;`
613			`setout(l3);`
614
615			`// Advance time`
616			`#1000;`
617
618			`// Read gpio_out`
619			`tb_top.gpio_mon.get_gpioout(l4);`
620
621			`// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.`
622			`// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT`
623			`// bits are present on gpio_out and where`
624			`if ((l1 & l2 \| l3 & ~l2) != l4)`
625			`err = err + 1;`
626			`end`
627
628			`// Phase 8`
629			`//`
630			`// Output result for previous test`
631			`//`
632			`if (!err)`
633			`$display(" OK");`
634			`else`
635			`failed;`
636
637			`end`
638			`endtask`
639
640			`//`
641			`// Test interrupts`
642			`//`
643			`task test_ints;`
644			`integer l1, l2, l3;`
645			`integer i, rnd, err;`
646			`integer r1;`
647			`begin`
648
649			`$write(" Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");`
650
651			`//`
652			`// Phase 1`
653			`//`
654			`// Generate patterns on inputs in interrupt mode`
655			`//`
656
657			`// Disable spurious interrupt monitor`
658			`ints_disabled = 0;`
659
660			`err = 0;`
661			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
662
663			`// Set gpio_in pins`
664			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
665			`tb_top.gpio_mon.set_gpioin(r1);`
666
667			`// Low level triggering`
668			`setptrig(0);`
669
670			`// Enable interrupts in RGPIO_CTRL`
671			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
672
673			`// Enable interrupts in RGPIO_INTE`
674			`setinte(r1);`
675
676			`// Advance time`
677			`#100;`
678
679			`// Sample interrupt request. Should be zero.`
680			`l1 = tb_top.gpio.wb_inta_o;`
681
682			`// Clear gpio_in pins`
683			`tb_top.gpio_mon.set_gpioin(0);`
684
685			`// Advance time`
686			`#100;`
687
688			`// Sample interrupt request. Should be one.`
689			`l2 = tb_top.gpio.wb_inta_o;`
690
691			`// Clear interrupt request`
692			`setctrl(0);`
693
694			`// Advance time`
695			`#100;`
696
697			`// Sample interrupt request. Should be zero.`
698			`l3 = tb_top.gpio.wb_inta_o;`
699
700			`// Check for errors`
701			`if (l1 \|\| !l2 \|\| l3)`
702			`err = err +1;`
703			`end`
704
705			`// Enable spurious interrupt monitor`
706			`ints_disabled = 1;`
707
708			`// Phase 2`
709			`//`
710			`// Check results`
711			`//`
712			`if (!err)`
713			`$display(" OK");`
714			`else`
715			`failed;`
716			`end`
717			`endtask`
718
719			`//`
720			`// Test ptrig`
721			`//`
722			`task test_ptrig;`
723			`integer l1, l2, l3;`
724			`integer i, rnd, err;`
725			`integer r1;`
726			`begin`
727			`$write(" Testing ptrig features ...");`
728
729			`//`
730			`// Phase 1`
731			`//`
732			`// Generate patterns on inputs in interrupt mode`
733			`//`
734
735			`// Disable spurious interrupt monitor`
736			`ints_disabled = 0;`
737
738			`err = 0;`
739			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
740
741			`// Set bits to one`
742			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
743
744			`// Set gpio_in pins`
745			`tb_top.gpio_mon.set_gpioin('h00000000);`
746
747			`// High level triggering`
748			`setptrig('hffffffff);`
749
750			`// Enable interrupts in RGPIO_CTRL`
751			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
752
753			`// Enable interrupts in RGPIO_INTE`
754			`setinte(r1);`
755
756			`// Advance time`
757			`#100;`
758
759			`// Sample interrupt request. Should be zero.`
760			`l1 = tb_top.gpio.wb_inta_o;`
761
762			`// Clear gpio_in pins`
763			`tb_top.gpio_mon.set_gpioin('hffffffff);`
764
765			`// Advance time`
766			`#100;`
767
768			`// Sample interrupt request. Should be one.`
769			`l2 = tb_top.gpio.wb_inta_o;`
770
771			`// Clear interrupt request`
772			`setctrl(0);`
773
774			`// Advance time`
775			`#100;`
776
777			`// Sample interrupt request. Should be zero.`
778			`l3 = tb_top.gpio.wb_inta_o;`
779
780			`// Check for errors`
781			`if (l1 \|\| !l2 \|\| l3)`
782			`err = err +1;`
783			`end`
784
785			`// Enable spurious interrupt monitor`
786			`ints_disabled = 1;`
787
788			`// Phase 2`
789			`//`
790			`// Check results`
791			`//`
792			`if (!err)`
793			`$display(" OK");`
794			`else`
795			`failed;`
796			`end`
797			`endtask`
798
799			`//`
800			`// Do continues check for interrupts`
801			`//`
802			`always @(posedge tb_top.gpio.wb_inta_o)`
803			`if (ints_disabled) begin`
804			`$display("Spurious interrupt detected. ");`
805			`failed;`
806			`ints_working = 9876;`
807			`$display;`
808			`end`
809
810			`//`
811			`// Start of testbench test tasks`
812			`//`
813			`integer i;`
814			`initial begin`
815			`ifdef DUMP_VCD
816			`$dumpfile("../sim/tb_top.vcd");`
817			`$dumpvars(0);`
818			`endif
819			`nr_failed = 0;`
820			`ints_disabled = 1;`
821			`ints_working = 0;`
822			`tb_top.gpio_mon.set_gpioin(0);`
823			`tb_top.gpio_mon.set_gpioaux(0);`
824			`tb_top.gpio_mon.set_gpioeclk(0);`
825			`$display;`
826			`$display("###");`
827			`$display("### GPIO IP Core Verification ###");`
828			`$display("###");`
829			`$display;`
830			`$display("I. Testing correct operation of RGPIO_CTRL control bits");`
831			`$display;`
832
833
834			`$write(" Testing control bit RGPIO_CTRL[ECLK] ...");`
835			`local_errs = 0;`
836			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
837			`test_eclk;`
838			`if (local_errs == 0)`
839			`$display(" OK");`
840			`else`
841			`failed;`
842
843
844			`$write(" Testing control bit RGPIO_CTRL[NEC] ...");`
845			`local_errs = 0;`
846			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
847			`test_nec;`
848			`if (local_errs == 0)`
849			`$display(" OK");`
850			`else`
851			`failed;`
852
853			`test_ints;`
854
855			`$display;`
856			`$display("II. Testing modes of operation ...");`
857			`$display;`
858
859			`test_simple;`
860			`test_ptrig;`
861
862			`$display;`
863			`$display("###");`
864			`$display("### FAILED TESTS: %d ###", nr_failed);`
865			`$display("###");`
866			`$display;`
867			`$finish;`
868			`end`
869
870			`endmodule`