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[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] in_pad_i;       // GPIO Inputs
input                   ext_clk_pad_i;  // GPIO Eclk
output  [gw-1:0] out_pad_o;      // GPIO Outputs
output  [gw-1:0] oen_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_in_sel;   // RGPIO_IN select
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
reg     [dw-1:0] wb_dat_o;       // Data out
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding | (wb_sel_i != 4'b1111);
`else
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err_o = (wb_sel_i != 4'b1111);
`else
assign wb_err_o = 1'b0;
`endif
`endif
 
//
// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,
// external clock is used.
//
assign latch_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ?
                ext_clk_pad_i ^ rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] : wb_clk_i;
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_in_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_IN) & full_decoding;
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge latch_clk or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_pad_i;
`else
assign rgpio_in = in_pad_i;
`endif
 
//
// Read GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
//                      wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};
//                      wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
//                      wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
//                      wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
//                      wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat_o[3:0] <= rgpio_ctrl;
                        wb_dat_o[dw-1:4] <= {dw-4{1'b0}};
                end
`endif
                default: begin
                        wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
//                      wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
                end
        endcase
 
//
// Generate interrupt request
//
assign wb_inta_o = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Generate output enables from inverted RGPIO_OE bits
//
assign oen_padoen_o = ~rgpio_oe;
 
//
// Generate outputs
//
assign out_pad_o = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign oen_padoen_o = {gw{1'b1}};
assign out_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

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[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 14

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.1 2001/08/21 21:39:28 lampret`
49			`// Changed directory structure, port names and drfines.`
50			`//`
51			`// Revision 1.2 2001/07/14 20:39:26 lampret`
52			`// Better configurability.`
53			`//`
54			`// Revision 1.1 2001/06/05 07:45:26 lampret`
55			`// Added initial RTL and test benches. There are still some issues with these files.`
56			`//`
57			`//`
58
59			`// synopsys translate_off`
60			`include "timescale.v"
61			`// synopsys translate_on`
62			`include "gpio_defines.v"
63
64			`module gpio_top(`
65			`// WISHBONE Interface`
66			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
67			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
68
69			`// Auxiliary inputs interface`
70			`aux_i,`
71
72			`// External GPIO Interface`
73			`in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o`
74			`);`
75
76			`parameter dw = 32;`
77			parameter aw = `GPIO_ADDRHH+1;
78			parameter gw = `GPIO_IOS;
79
80			`//`
81			`// WISHBONE Interface`
82			`//`
83			`input wb_clk_i; // Clock`
84			`input wb_rst_i; // Reset`
85			`input wb_cyc_i; // cycle valid input`
86			`input [aw-1:0] wb_adr_i; // address bus inputs`
87			`input [dw-1:0] wb_dat_i; // input data bus`
88			`input [3:0] wb_sel_i; // byte select inputs`
89			`input wb_we_i; // indicates write transfer`
90			`input wb_stb_i; // strobe input`
91			`output [dw-1:0] wb_dat_o; // output data bus`
92			`output wb_ack_o; // normal termination`
93			`output wb_err_o; // termination w/ error`
94			`output wb_inta_o; // Interrupt request output`
95
96			`// Auxiliary Inputs Interface`
97			`input [gw-1:0] aux_i; // Auxiliary inputs`
98
99			`//`
100			`// External GPIO Interface`
101			`//`
102			`input [gw-1:0] in_pad_i; // GPIO Inputs`
103			`input ext_clk_pad_i; // GPIO Eclk`
104			`output [gw-1:0] out_pad_o; // GPIO Outputs`
105			`output [gw-1:0] oen_padoen_o; // GPIO output drivers enables`
106
107			`ifdef GPIO_IMPLEMENTED
108
109			`//`
110			`// GPIO Input Register (or no register)`
111			`//`
112			`ifdef GPIO_RGPIO_IN
113			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
114			`else
115			`wire [gw-1:0] rgpio_in; // No register`
116			`endif
117
118			`//`
119			`// GPIO Output Register (or no register)`
120			`//`
121			`ifdef GPIO_RGPIO_OUT
122			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
123			`else
124			`wire [gw-1:0] rgpio_out; // No register`
125			`endif
126
127			`//`
128			`// GPIO Output Driver Enable Register (or no register)`
129			`//`
130			`ifdef GPIO_RGPIO_OE
131			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
132			`else
133			`wire [gw-1:0] rgpio_oe; // No register`
134			`endif
135
136			`//`
137			`// GPIO Interrupt Enable Register (or no register)`
138			`//`
139			`ifdef GPIO_RGPIO_INTE
140			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
141			`else
142			`wire [gw-1:0] rgpio_inte; // No register`
143			`endif
144
145			`//`
146			`// GPIO Positive edge Triggered Register (or no register)`
147			`//`
148			`ifdef GPIO_RGPIO_PTRIG
149			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
150			`else
151			`wire [gw-1:0] rgpio_ptrig; // No register`
152			`endif
153
154			`//`
155			`// GPIO Auxiliary select Register (or no register)`
156			`//`
157			`ifdef GPIO_RGPIO_AUX
158			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
159			`else
160			`wire [gw-1:0] rgpio_aux; // No register`
161			`endif
162
163			`//`
164			`// GPIO Control Register (or no register)`
165			`//`
166			`ifdef GPIO_RGPIO_CTRL
167			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
168			`else
169			`wire [3:0] rgpio_ctrl; // No register`
170			`endif
171
172			`//`
173			`// Internal wires & regs`
174			`//`
175			`wire rgpio_in_sel; // RGPIO_IN select`
176			`wire rgpio_out_sel; // RGPIO_OUT select`
177			`wire rgpio_oe_sel; // RGPIO_OE select`
178			`wire rgpio_inte_sel; // RGPIO_INTE select`
179			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
180			`wire rgpio_aux_sel; // RGPIO_AUX select`
181			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
182			`wire latch_clk; // Latch clock`
183			`wire full_decoding; // Full address decoding qualification`
184			`reg [dw-1:0] wb_dat_o; // Data out`
185
186			`//`
187			`// All WISHBONE transfer terminations are successful except when:`
188			`// a) full address decoding is enabled and address doesn't match`
189			`// any of the GPIO registers`
190			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
191			`//`
192			`assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;`
193			`ifdef GPIO_FULL_DECODE
194			`ifdef GPIO_STRICT_32BIT_ACCESS
195			`assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding \| (wb_sel_i != 4'b1111);`
196			`else
197			`assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;`
198			`endif
199			`else
200			`ifdef GPIO_STRICT_32BIT_ACCESS
201			`assign wb_err_o = (wb_sel_i != 4'b1111);`
202			`else
203			`assign wb_err_o = 1'b0;`
204			`endif
205			`endif
206
207			`//`
208			`// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,`
209			`// external clock is used.`
210			`//`
211			assign latch_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ?
212			ext_clk_pad_i ^ rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] : wb_clk_i;
213
214			`//`
215			`// Full address decoder`
216			`//`
217			`ifdef GPIO_FULL_DECODE
218			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
219			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
220			`else
221			`assign full_decoding = 1'b1;`
222			`endif
223
224			`//`
225			`// GPIO registers address decoder`
226			`//`
227			assign rgpio_in_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_IN) & full_decoding;
228			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
229			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
230			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
231			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
232			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
233			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
234
235			`//`
236			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
237			`//`
238			`ifdef GPIO_RGPIO_CTRL
239			`always @(posedge wb_clk_i or posedge wb_rst_i)`
240			`if (wb_rst_i)`
241			`rgpio_ctrl <= #1 4'b0;`
242			`else if (rgpio_ctrl_sel && wb_we_i)`
243			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
244			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
245			rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] \| wb_inta_o;
246			`else
247			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
248			`endif
249
250			`//`
251			`// Write to RGPIO_OUT`
252			`//`
253			`ifdef GPIO_RGPIO_OUT
254			`always @(posedge wb_clk_i or posedge wb_rst_i)`
255			`if (wb_rst_i)`
256			`rgpio_out <= #1 {gw{1'b0}};`
257			`else if (rgpio_out_sel && wb_we_i)`
258			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
259			`else
260			assign rgpio_out = `GPIO_DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
261			`endif
262
263			`//`
264			`// Write to RGPIO_OE`
265			`//`
266			`ifdef GPIO_RGPIO_OE
267			`always @(posedge wb_clk_i or posedge wb_rst_i)`
268			`if (wb_rst_i)`
269			`rgpio_oe <= #1 {gw{1'b0}};`
270			`else if (rgpio_oe_sel && wb_we_i)`
271			`rgpio_oe <= #1 wb_dat_i[gw-1:0];`
272			`else
273			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
274			`endif
275
276			`//`
277			`// Write to RGPIO_INTE`
278			`//`
279			`ifdef GPIO_RGPIO_INTE
280			`always @(posedge wb_clk_i or posedge wb_rst_i)`
281			`if (wb_rst_i)`
282			`rgpio_inte <= #1 {gw{1'b0}};`
283			`else if (rgpio_inte_sel && wb_we_i)`
284			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
285			`else
286			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
287			`endif
288
289			`//`
290			`// Write to RGPIO_PTRIG`
291			`//`
292			`ifdef GPIO_RGPIO_PTRIG
293			`always @(posedge wb_clk_i or posedge wb_rst_i)`
294			`if (wb_rst_i)`
295			`rgpio_ptrig <= #1 {gw{1'b0}};`
296			`else if (rgpio_ptrig_sel && wb_we_i)`
297			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
298			`else
299			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
300			`endif
301
302			`//`
303			`// Write to RGPIO_AUX`
304			`//`
305			`ifdef GPIO_RGPIO_AUX
306			`always @(posedge wb_clk_i or posedge wb_rst_i)`
307			`if (wb_rst_i)`
308			`rgpio_aux <= #1 {gw{1'b0}};`
309			`else if (rgpio_aux_sel && wb_we_i)`
310			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
311			`else
312			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
313			`endif
314
315			`//`
316			`// Latch into RGPIO_IN`
317			`//`
318			`ifdef GPIO_RGPIO_IN
319			`always @(posedge latch_clk or posedge wb_rst_i)`
320			`if (wb_rst_i)`
321			`rgpio_in <= #1 {gw{1'b0}};`
322			`else`
323			`rgpio_in <= #1 in_pad_i;`
324			`else
325			`assign rgpio_in = in_pad_i;`
326			`endif
327
328			`//`
329			`// Read GPIO registers`
330			`//`
331			`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
332			`rgpio_ptrig or rgpio_aux or rgpio_ctrl)`
333			case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
334			`ifdef GPIO_READREGS
335			`GPIO_RGPIO_OUT: begin
336			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};`
337			`// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};`
338			`end`
339			`GPIO_RGPIO_OE: begin
340			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};`
341			`// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};`
342			`end`
343			`GPIO_RGPIO_INTE: begin
344			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};`
345			`// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};`
346			`end`
347			`GPIO_RGPIO_PTRIG: begin
348			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};`
349			`// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};`
350			`end`
351			`GPIO_RGPIO_AUX: begin
352			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};`
353			`// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};`
354			`end`
355			`GPIO_RGPIO_CTRL: begin
356			`wb_dat_o[3:0] <= rgpio_ctrl;`
357			`wb_dat_o[dw-1:4] <= {dw-4{1'b0}};`
358			`end`
359			`endif
360			`default: begin`
361			`wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};`
362			`// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};`
363			`end`
364			`endcase`
365
366			`//`
367			`// Generate interrupt request`
368			`//`
369			assign wb_inta_o = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
370
371			`//`
372			`// Generate output enables from inverted RGPIO_OE bits`
373			`//`
374			`assign oen_padoen_o = ~rgpio_oe;`
375
376			`//`
377			`// Generate outputs`
378			`//`
379			`assign out_pad_o = rgpio_out & ~rgpio_aux \| aux_i & rgpio_aux;`
380
381			`else
382
383			`//`
384			`// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL`
385			`// is cleared and WISHBONE transfers complete with errors`
386			`//`
387			`assign wb_inta_o = 1'b0;`
388			`assign wb_ack_o = 1'b0;`
389			`assign wb_err_o = wb_cyc_i & wb_stb_i;`
390			`assign oen_padoen_o = {gw{1'b1}};`
391			`assign out_pad_o = {gw{1'b0}};`
392
393			`//`
394			`// Read GPIO registers`
395			`//`
396			`assign wb_dat_o = {dw{1'b0}};`
397
398			`endif
399
400			`endmodule`