URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 22

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2001/12/25 17:12:35  lampret
// Added RGPIO_INTS.
//
// Revision 1.5  2001/12/12 20:35:53  lampret
// Fixing style.
//
// Revision 1.4  2001/12/12 07:12:58  lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
// Revision 1.3  2001/11/15 02:24:37  lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.2  2001/10/31 02:26:51  lampret
// Fixed wb_err_o.
//
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] in_pad_i;       // GPIO Inputs
input                   ext_clk_pad_i;  // GPIO Eclk
output  [gw-1:0] out_pad_o;      // GPIO Outputs
output  [gw-1:0] oen_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
`else
wire    [gw-1:0] rgpio_ints;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    rgpio_ints_sel; // RGPIO_INTS select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
wire    [gw-1:0] in_muxed;       // Muxed inputs
wire                    wb_ack;         // WB Acknowledge
wire                    wb_err;         // WB Error
wire                    wb_inta;        // WB Interrupt
reg     [dw-1:0] wb_dat;         // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg                     wb_ack_o;       // WB Acknowledge
reg                     wb_err_o;       // WB Error
reg                     wb_inta_o;      // WB Interrupt
reg     [dw-1:0] wb_dat_o;       // WB Data out
`endif
wire    [gw-1:0] out_pad;        // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg     [gw-1:0] out_pad_o;      // GPIO Outputs
`endif
wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock
wire                    pext_clk;       // External clock for posedge flops
reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs
`endif
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
 
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
 
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_ack;
`else
assign wb_ack_o = wb_ack;
`endif
 
//
// WB Error
//
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
`endif
`endif
 
//
// Optional registration of WB error
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
`else
assign pext_clk = ext_clk_pad_i;
`endif
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
`endif
 
//
// Latch using posedge external clock
//
always @(posedge pext_clk or posedge wb_rst_i)
        if (wb_rst_i)
                pextc_sampled <= #1 {gw{1'b0}};
        else
                pextc_sampled <= #1 in_pad_i;
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge ext_clk_pad_i or posedge wb_rst_i)
        if (wb_rst_i)
                nextc_sampled <= #1 {gw{1'b0}};
        else
                nextc_sampled <= #1 in_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat[3:0] = rgpio_ctrl;
                        wb_dat[dw-1:4] = {dw-4{1'b0}};
                end
`endif
                `GPIO_RGPIO_INTS: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};
                end
                default: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
                end
        endcase
 
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else
                wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
 
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ints <= #1 {gw{1'b0}};
        else if (rgpio_ints_sel && wb_we_i)
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ints <= #1 rgpio_ints | (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`else
assign rgpio_ints = (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_inta_o <= #1 1'b0;
        else
                wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
 
//
// Output enables are RGPIO_OE bits
//
assign oen_padoen_o = rgpio_oe;
 
//
// Generate GPIO outputs
//
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                out_pad_o <= #1 {gw{1'b0}};
        else
                out_pad_o <= #1 out_pad;
`else
assign out_pad_o = out_pad;
`endif
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign oen_padoen_o = {gw{1'b1}};
assign out_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	22	lampret	`// Revision 1.6 2001/12/25 17:12:35 lampret`
49			`// Added RGPIO_INTS.`
50			`//`
51	21	lampret	`// Revision 1.5 2001/12/12 20:35:53 lampret`
52			`// Fixing style.`
53			`//`
54	20	lampret	`// Revision 1.4 2001/12/12 07:12:58 lampret`
55			`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`
56			`//`
57	19	lampret	`// Revision 1.3 2001/11/15 02:24:37 lampret`
58			`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
59			`//`
60	17	lampret	`// Revision 1.2 2001/10/31 02:26:51 lampret`
61			`// Fixed wb_err_o.`
62			`//`
63	15	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
64			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
65			`//`
66	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
67			`// Changed directory structure, port names and drfines.`
68			`//`
69			`// Revision 1.2 2001/07/14 20:39:26 lampret`
70			`// Better configurability.`
71			`//`
72			`// Revision 1.1 2001/06/05 07:45:26 lampret`
73			`// Added initial RTL and test benches. There are still some issues with these files.`
74			`//`
75			`//`
76
77			`// synopsys translate_off`
78			`include "timescale.v"
79			`// synopsys translate_on`
80			`include "gpio_defines.v"
81
82			`module gpio_top(`
83			`// WISHBONE Interface`
84			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
85			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
86
87			`// Auxiliary inputs interface`
88			`aux_i,`
89
90			`// External GPIO Interface`
91			`in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o`
92			`);`
93
94			`parameter dw = 32;`
95			parameter aw = `GPIO_ADDRHH+1;
96			parameter gw = `GPIO_IOS;
97
98			`//`
99			`// WISHBONE Interface`
100			`//`
101			`input wb_clk_i; // Clock`
102			`input wb_rst_i; // Reset`
103			`input wb_cyc_i; // cycle valid input`
104			`input [aw-1:0] wb_adr_i; // address bus inputs`
105			`input [dw-1:0] wb_dat_i; // input data bus`
106			`input [3:0] wb_sel_i; // byte select inputs`
107			`input wb_we_i; // indicates write transfer`
108			`input wb_stb_i; // strobe input`
109			`output [dw-1:0] wb_dat_o; // output data bus`
110			`output wb_ack_o; // normal termination`
111			`output wb_err_o; // termination w/ error`
112			`output wb_inta_o; // Interrupt request output`
113
114			`// Auxiliary Inputs Interface`
115			`input [gw-1:0] aux_i; // Auxiliary inputs`
116
117			`//`
118			`// External GPIO Interface`
119			`//`
120			`input [gw-1:0] in_pad_i; // GPIO Inputs`
121			`input ext_clk_pad_i; // GPIO Eclk`
122			`output [gw-1:0] out_pad_o; // GPIO Outputs`
123			`output [gw-1:0] oen_padoen_o; // GPIO output drivers enables`
124
125			`ifdef GPIO_IMPLEMENTED
126
127			`//`
128			`// GPIO Input Register (or no register)`
129			`//`
130			`ifdef GPIO_RGPIO_IN
131			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
132			`else
133			`wire [gw-1:0] rgpio_in; // No register`
134			`endif
135
136			`//`
137			`// GPIO Output Register (or no register)`
138			`//`
139			`ifdef GPIO_RGPIO_OUT
140			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
141			`else
142			`wire [gw-1:0] rgpio_out; // No register`
143			`endif
144
145			`//`
146			`// GPIO Output Driver Enable Register (or no register)`
147			`//`
148			`ifdef GPIO_RGPIO_OE
149			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
150			`else
151			`wire [gw-1:0] rgpio_oe; // No register`
152			`endif
153
154			`//`
155			`// GPIO Interrupt Enable Register (or no register)`
156			`//`
157			`ifdef GPIO_RGPIO_INTE
158			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
159			`else
160			`wire [gw-1:0] rgpio_inte; // No register`
161			`endif
162
163			`//`
164			`// GPIO Positive edge Triggered Register (or no register)`
165			`//`
166			`ifdef GPIO_RGPIO_PTRIG
167			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
168			`else
169			`wire [gw-1:0] rgpio_ptrig; // No register`
170			`endif
171
172			`//`
173			`// GPIO Auxiliary select Register (or no register)`
174			`//`
175			`ifdef GPIO_RGPIO_AUX
176			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
177			`else
178			`wire [gw-1:0] rgpio_aux; // No register`
179			`endif
180
181			`//`
182			`// GPIO Control Register (or no register)`
183			`//`
184			`ifdef GPIO_RGPIO_CTRL
185			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
186			`else
187			`wire [3:0] rgpio_ctrl; // No register`
188			`endif
189
190			`//`
191	21	lampret	`// GPIO Interrupt Status Register (or no register)`
192			`//`
193			`ifdef GPIO_RGPIO_INTS
194			`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`
195			`else
196			`wire [gw-1:0] rgpio_ints; // No register`
197			`endif
198
199			`//`
200	14	lampret	`// Internal wires & regs`
201			`//`
202			`wire rgpio_out_sel; // RGPIO_OUT select`
203			`wire rgpio_oe_sel; // RGPIO_OE select`
204			`wire rgpio_inte_sel; // RGPIO_INTE select`
205			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
206			`wire rgpio_aux_sel; // RGPIO_AUX select`
207			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
208	21	lampret	`wire rgpio_ints_sel; // RGPIO_INTS select`
209	14	lampret	`wire latch_clk; // Latch clock`
210			`wire full_decoding; // Full address decoding qualification`
211	17	lampret	`wire [gw-1:0] in_muxed; // Muxed inputs`
212			`wire wb_ack; // WB Acknowledge`
213			`wire wb_err; // WB Error`
214			`wire wb_inta; // WB Interrupt`
215			`reg [dw-1:0] wb_dat; // WB Data out`
216			`ifdef GPIO_REGISTERED_WB_OUTPUTS
217			`reg wb_ack_o; // WB Acknowledge`
218			`reg wb_err_o; // WB Error`
219			`reg wb_inta_o; // WB Interrupt`
220			`reg [dw-1:0] wb_dat_o; // WB Data out`
221			`endif
222			`wire [gw-1:0] out_pad; // GPIO Outputs`
223			`ifdef GPIO_REGISTERED_IO_OUTPUTS
224			`reg [gw-1:0] out_pad_o; // GPIO Outputs`
225			`endif
226			`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`
227			`wire pext_clk; // External clock for posedge flops`
228			`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`
229			`ifdef GPIO_NO_NEGEDGE_FLOPS
230			`else
231			`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`
232			`endif
233	14	lampret
234			`//`
235			`// All WISHBONE transfer terminations are successful except when:`
236			`// a) full address decoding is enabled and address doesn't match`
237			`// any of the GPIO registers`
238			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
239			`//`
240	17	lampret
241			`//`
242			`// WB Acknowledge`
243			`//`
244			`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`
245
246			`//`
247			`// Optional registration of WB Ack`
248			`//`
249			`ifdef GPIO_REGISTERED_WB_OUTPUTS
250			`always @(posedge wb_clk_i or posedge wb_rst_i)`
251			`if (wb_rst_i)`
252			`wb_ack_o <= #1 1'b0;`
253			`else`
254			`wb_ack_o <= #1 wb_ack;`
255			`else
256			`assign wb_ack_o = wb_ack;`
257			`endif
258
259			`//`
260			`// WB Error`
261			`//`
262	14	lampret	`ifdef GPIO_FULL_DECODE
263			`ifdef GPIO_STRICT_32BIT_ACCESS
264	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
265	14	lampret	`else
266	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`
267	14	lampret	`endif
268			`else
269			`ifdef GPIO_STRICT_32BIT_ACCESS
270	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
271	14	lampret	`else
272	17	lampret	`assign wb_err = 1'b0;`
273	14	lampret	`endif
274			`endif
275
276			`//`
277	17	lampret	`// Optional registration of WB error`
278	14	lampret	`//`
279	17	lampret	`ifdef GPIO_REGISTERED_WB_OUTPUTS
280			`always @(posedge wb_clk_i or posedge wb_rst_i)`
281			`if (wb_rst_i)`
282			`wb_err_o <= #1 1'b0;`
283			`else`
284			`wb_err_o <= #1 wb_err;`
285			`else
286			`assign wb_err_o = wb_err;`
287			`endif
288	14	lampret
289			`//`
290			`// Full address decoder`
291			`//`
292			`ifdef GPIO_FULL_DECODE
293			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
294			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
295			`else
296			`assign full_decoding = 1'b1;`
297			`endif
298
299			`//`
300			`// GPIO registers address decoder`
301			`//`
302			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
303			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
304			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
305			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
306			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
307			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
308	21	lampret	assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
309	14	lampret
310			`//`
311			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
312			`//`
313			`ifdef GPIO_RGPIO_CTRL
314			`always @(posedge wb_clk_i or posedge wb_rst_i)`
315			`if (wb_rst_i)`
316			`rgpio_ctrl <= #1 4'b0;`
317			`else if (rgpio_ctrl_sel && wb_we_i)`
318			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
319			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
320	21	lampret	rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;
321	14	lampret	`else
322			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
323			`endif
324
325			`//`
326			`// Write to RGPIO_OUT`
327			`//`
328			`ifdef GPIO_RGPIO_OUT
329			`always @(posedge wb_clk_i or posedge wb_rst_i)`
330			`if (wb_rst_i)`
331			`rgpio_out <= #1 {gw{1'b0}};`
332			`else if (rgpio_out_sel && wb_we_i)`
333			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
334			`else
335	17	lampret	assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
336	14	lampret	`endif
337
338			`//`
339	17	lampret	`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`
340	14	lampret	`//`
341			`ifdef GPIO_RGPIO_OE
342			`always @(posedge wb_clk_i or posedge wb_rst_i)`
343			`if (wb_rst_i)`
344			`rgpio_oe <= #1 {gw{1'b0}};`
345			`else if (rgpio_oe_sel && wb_we_i)`
346	17	lampret	`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`
347	14	lampret	`else
348			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
349			`endif
350
351			`//`
352			`// Write to RGPIO_INTE`
353			`//`
354			`ifdef GPIO_RGPIO_INTE
355			`always @(posedge wb_clk_i or posedge wb_rst_i)`
356			`if (wb_rst_i)`
357			`rgpio_inte <= #1 {gw{1'b0}};`
358			`else if (rgpio_inte_sel && wb_we_i)`
359			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
360			`else
361			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
362			`endif
363
364			`//`
365			`// Write to RGPIO_PTRIG`
366			`//`
367			`ifdef GPIO_RGPIO_PTRIG
368			`always @(posedge wb_clk_i or posedge wb_rst_i)`
369			`if (wb_rst_i)`
370			`rgpio_ptrig <= #1 {gw{1'b0}};`
371			`else if (rgpio_ptrig_sel && wb_we_i)`
372			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
373			`else
374			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
375			`endif
376
377			`//`
378			`// Write to RGPIO_AUX`
379			`//`
380			`ifdef GPIO_RGPIO_AUX
381			`always @(posedge wb_clk_i or posedge wb_rst_i)`
382			`if (wb_rst_i)`
383			`rgpio_aux <= #1 {gw{1'b0}};`
384			`else if (rgpio_aux_sel && wb_we_i)`
385			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
386			`else
387			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
388			`endif
389
390			`//`
391			`// Latch into RGPIO_IN`
392			`//`
393			`ifdef GPIO_RGPIO_IN
394	17	lampret	`always @(posedge wb_clk_i or posedge wb_rst_i)`
395	14	lampret	`if (wb_rst_i)`
396			`rgpio_in <= #1 {gw{1'b0}};`
397			`else`
398	17	lampret	`rgpio_in <= #1 in_muxed;`
399	14	lampret	`else
400	17	lampret	`assign rgpio_in = in_muxed;`
401	14	lampret	`endif
402
403			`//`
404	17	lampret	`// Mux inputs directly from input pads with inputs sampled by external clock`
405	14	lampret	`//`
406	17	lampret	assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
407
408			`//`
409			`// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.`
410			`// If negedge flops are allowed, pext_clk only clocks posedge flops.`
411			`//`
412			`ifdef GPIO_NO_NEGEDGE_FLOPS
413			assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
414			`else
415			`assign pext_clk = ext_clk_pad_i;`
416			`endif
417
418			`//`
419			`// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.`
420			`//`
421			`ifdef GPIO_NO_NEGEDGE_FLOPS
422			`assign extc_in = pextc_sampled;`
423			`else
424			assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
425			`endif
426
427			`//`
428			`// Latch using posedge external clock`
429			`//`
430			`always @(posedge pext_clk or posedge wb_rst_i)`
431			`if (wb_rst_i)`
432			`pextc_sampled <= #1 {gw{1'b0}};`
433			`else`
434			`pextc_sampled <= #1 in_pad_i;`
435
436			`//`
437			`// Latch using negedge external clock`
438			`//`
439			`ifdef GPIO_NO_NEGEDGE_FLOPS
440			`else
441			`always @(negedge ext_clk_pad_i or posedge wb_rst_i)`
442			`if (wb_rst_i)`
443			`nextc_sampled <= #1 {gw{1'b0}};`
444			`else`
445			`nextc_sampled <= #1 in_pad_i;`
446			`endif
447
448			`//`
449			`// Mux all registers when doing a read of GPIO registers`
450			`//`
451	14	lampret	`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
452	22	lampret	`rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)`
453	14	lampret	case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
454			`ifdef GPIO_READREGS
455			`GPIO_RGPIO_OUT: begin
456	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};`
457	14	lampret	`end`
458			`GPIO_RGPIO_OE: begin
459	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};`
460	14	lampret	`end`
461			`GPIO_RGPIO_INTE: begin
462	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};`
463	14	lampret	`end`
464			`GPIO_RGPIO_PTRIG: begin
465	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};`
466	14	lampret	`end`
467			`GPIO_RGPIO_AUX: begin
468	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};`
469	14	lampret	`end`
470			`GPIO_RGPIO_CTRL: begin
471	20	lampret	`wb_dat[3:0] = rgpio_ctrl;`
472			`wb_dat[dw-1:4] = {dw-4{1'b0}};`
473	14	lampret	`end`
474			`endif
475	21	lampret	`GPIO_RGPIO_INTS: begin
476			`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};`
477			`end`
478	14	lampret	`default: begin`
479	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};`
480	14	lampret	`end`
481			`endcase`
482
483			`//`
484	17	lampret	`// WB data output`
485			`//`
486			`ifdef GPIO_REGISTERED_WB_OUTPUTS
487			`always @(posedge wb_clk_i or posedge wb_rst_i)`
488			`if (wb_rst_i)`
489			`wb_dat_o <= #1 {dw{1'b0}};`
490			`else`
491			`wb_dat_o <= #1 wb_dat;`
492			`else
493			`assign wb_dat_o = wb_dat;`
494			`endif
495
496			`//`
497	21	lampret	`// RGPIO_INTS`
498			`//`
499			`ifdef GPIO_RGPIO_INTS
500			`always @(posedge wb_clk_i or posedge wb_rst_i)`

Browse

Tools

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 22