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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2002/03/13 20:47:57  lampret
// Ports changed per Ran Aviram suggestions.
//
// Revision 1.9  2002/03/09 03:43:27  lampret
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
//
// Revision 1.8  2002/01/14 19:06:28  lampret
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
//
// Revision 1.7  2001/12/25 17:21:21  lampret
// Fixed two typos.
//
// Revision 1.6  2001/12/25 17:12:35  lampret
// Added RGPIO_INTS.
//
// Revision 1.5  2001/12/12 20:35:53  lampret
// Fixing style.
//
// Revision 1.4  2001/12/12 07:12:58  lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
// Revision 1.3  2001/11/15 02:24:37  lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.2  2001/10/31 02:26:51  lampret
// Fixed wb_err_o.
//
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] ext_pad_i;      // GPIO Inputs
input                   clk_pad_i;      // GPIO Eclk
output  [gw-1:0] ext_pad_o;      // GPIO Outputs
output  [gw-1:0] ext_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
`else
wire    [gw-1:0] rgpio_ints;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    rgpio_ints_sel; // RGPIO_INTS select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
wire    [gw-1:0] in_muxed;       // Muxed inputs
wire                    wb_ack;         // WB Acknowledge
wire                    wb_err;         // WB Error
wire                    wb_inta;        // WB Interrupt
reg     [dw-1:0] wb_dat;         // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg                     wb_ack_o;       // WB Acknowledge
reg                     wb_err_o;       // WB Error
reg                     wb_inta_o;      // WB Interrupt
reg     [dw-1:0] wb_dat_o;       // WB Data out
`endif
wire    [gw-1:0] out_pad;        // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg     [gw-1:0] ext_pad_o;      // GPIO Outputs
`endif
wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock
wire                    pext_clk;       // External clock for posedge flops
reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs
`endif
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
 
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
 
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_ack & ~wb_ack_o;
`else
assign wb_ack_o = wb_ack;
`endif
 
//
// WB Error
//
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
`endif
`endif
 
//
// Optional registration of WB error
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & ~wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
`else
assign pext_clk = clk_pad_i;
`endif
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
`endif
 
//
// Latch using posedge external clock
//
always @(posedge pext_clk or posedge wb_rst_i)
        if (wb_rst_i)
                pextc_sampled <= #1 {gw{1'b0}};
        else
                pextc_sampled <= #1 ext_pad_i;
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge clk_pad_i or posedge wb_rst_i)
        if (wb_rst_i)
                nextc_sampled <= #1 {gw{1'b0}};
        else
                nextc_sampled <= #1 ext_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat[dw-1:0] = rgpio_out;
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat[dw-1:0] = ~rgpio_oe;
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat[dw-1:0] = rgpio_inte;
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat[dw-1:0] = rgpio_ptrig;
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat[dw-1:0] = rgpio_aux;
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat[3:0] = rgpio_ctrl;
                        wb_dat[dw-1:4] = {dw-4{1'b0}};
                end
`endif
                `GPIO_RGPIO_INTS: begin
                        wb_dat[dw-1:0] = rgpio_ints;
                end
                default: begin
                        wb_dat[dw-1:0] = rgpio_in;
                end
        endcase
 
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else
                wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
 
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ints <= #1 {gw{1'b0}};
        else if (rgpio_ints_sel && wb_we_i)
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != ext_pad_i)
                rgpio_ints <= #1 (rgpio_ints | (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
`else
assign rgpio_ints = (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_inta_o <= #1 1'b0;
        else
                wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
 
//
// Output enables are RGPIO_OE bits
//
assign ext_padoen_o = rgpio_oe;
 
//
// Generate GPIO outputs
//
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                ext_pad_o <= #1 {gw{1'b0}};
        else
                ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign ext_padoen_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	26	lampret	`// Revision 1.10 2002/03/13 20:47:57 lampret`
49			`// Ports changed per Ran Aviram suggestions.`
50			`//`
51	25	lampret	`// Revision 1.9 2002/03/09 03:43:27 lampret`
52			`// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)`
53			`//`
54	24	lampret	`// Revision 1.8 2002/01/14 19:06:28 lampret`
55			`// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.`
56			`//`
57	23	lampret	`// Revision 1.7 2001/12/25 17:21:21 lampret`
58			`// Fixed two typos.`
59			`//`
60	22	lampret	`// Revision 1.6 2001/12/25 17:12:35 lampret`
61			`// Added RGPIO_INTS.`
62			`//`
63	21	lampret	`// Revision 1.5 2001/12/12 20:35:53 lampret`
64			`// Fixing style.`
65			`//`
66	20	lampret	`// Revision 1.4 2001/12/12 07:12:58 lampret`
67			`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`
68			`//`
69	19	lampret	`// Revision 1.3 2001/11/15 02:24:37 lampret`
70			`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
71			`//`
72	17	lampret	`// Revision 1.2 2001/10/31 02:26:51 lampret`
73			`// Fixed wb_err_o.`
74			`//`
75	15	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
76			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
77			`//`
78	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
79			`// Changed directory structure, port names and drfines.`
80			`//`
81			`// Revision 1.2 2001/07/14 20:39:26 lampret`
82			`// Better configurability.`
83			`//`
84			`// Revision 1.1 2001/06/05 07:45:26 lampret`
85			`// Added initial RTL and test benches. There are still some issues with these files.`
86			`//`
87			`//`
88
89			`// synopsys translate_off`
90			`include "timescale.v"
91			`// synopsys translate_on`
92			`include "gpio_defines.v"
93
94			`module gpio_top(`
95			`// WISHBONE Interface`
96			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
97			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
98
99			`// Auxiliary inputs interface`
100			`aux_i,`
101
102			`// External GPIO Interface`
103	25	lampret	`ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o`
104	14	lampret	`);`
105
106			`parameter dw = 32;`
107			parameter aw = `GPIO_ADDRHH+1;
108			parameter gw = `GPIO_IOS;
109
110			`//`
111			`// WISHBONE Interface`
112			`//`
113			`input wb_clk_i; // Clock`
114			`input wb_rst_i; // Reset`
115			`input wb_cyc_i; // cycle valid input`
116			`input [aw-1:0] wb_adr_i; // address bus inputs`
117			`input [dw-1:0] wb_dat_i; // input data bus`
118			`input [3:0] wb_sel_i; // byte select inputs`
119			`input wb_we_i; // indicates write transfer`
120			`input wb_stb_i; // strobe input`
121			`output [dw-1:0] wb_dat_o; // output data bus`
122			`output wb_ack_o; // normal termination`
123			`output wb_err_o; // termination w/ error`
124			`output wb_inta_o; // Interrupt request output`
125
126			`// Auxiliary Inputs Interface`
127			`input [gw-1:0] aux_i; // Auxiliary inputs`
128
129			`//`
130			`// External GPIO Interface`
131			`//`
132	25	lampret	`input [gw-1:0] ext_pad_i; // GPIO Inputs`
133			`input clk_pad_i; // GPIO Eclk`
134			`output [gw-1:0] ext_pad_o; // GPIO Outputs`
135			`output [gw-1:0] ext_padoen_o; // GPIO output drivers enables`
136	14	lampret
137			`ifdef GPIO_IMPLEMENTED
138
139			`//`
140			`// GPIO Input Register (or no register)`
141			`//`
142			`ifdef GPIO_RGPIO_IN
143			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
144			`else
145			`wire [gw-1:0] rgpio_in; // No register`
146			`endif
147
148			`//`
149			`// GPIO Output Register (or no register)`
150			`//`
151			`ifdef GPIO_RGPIO_OUT
152			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
153			`else
154			`wire [gw-1:0] rgpio_out; // No register`
155			`endif
156
157			`//`
158			`// GPIO Output Driver Enable Register (or no register)`
159			`//`
160			`ifdef GPIO_RGPIO_OE
161			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
162			`else
163			`wire [gw-1:0] rgpio_oe; // No register`
164			`endif
165
166			`//`
167			`// GPIO Interrupt Enable Register (or no register)`
168			`//`
169			`ifdef GPIO_RGPIO_INTE
170			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
171			`else
172			`wire [gw-1:0] rgpio_inte; // No register`
173			`endif
174
175			`//`
176			`// GPIO Positive edge Triggered Register (or no register)`
177			`//`
178			`ifdef GPIO_RGPIO_PTRIG
179			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
180			`else
181			`wire [gw-1:0] rgpio_ptrig; // No register`
182			`endif
183
184			`//`
185			`// GPIO Auxiliary select Register (or no register)`
186			`//`
187			`ifdef GPIO_RGPIO_AUX
188			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
189			`else
190			`wire [gw-1:0] rgpio_aux; // No register`
191			`endif
192
193			`//`
194			`// GPIO Control Register (or no register)`
195			`//`
196			`ifdef GPIO_RGPIO_CTRL
197			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
198			`else
199			`wire [3:0] rgpio_ctrl; // No register`
200			`endif
201
202			`//`
203	21	lampret	`// GPIO Interrupt Status Register (or no register)`
204			`//`
205			`ifdef GPIO_RGPIO_INTS
206			`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`
207			`else
208			`wire [gw-1:0] rgpio_ints; // No register`
209			`endif
210
211			`//`
212	14	lampret	`// Internal wires & regs`
213			`//`
214			`wire rgpio_out_sel; // RGPIO_OUT select`
215			`wire rgpio_oe_sel; // RGPIO_OE select`
216			`wire rgpio_inte_sel; // RGPIO_INTE select`
217			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
218			`wire rgpio_aux_sel; // RGPIO_AUX select`
219			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
220	21	lampret	`wire rgpio_ints_sel; // RGPIO_INTS select`
221	14	lampret	`wire latch_clk; // Latch clock`
222			`wire full_decoding; // Full address decoding qualification`
223	17	lampret	`wire [gw-1:0] in_muxed; // Muxed inputs`
224			`wire wb_ack; // WB Acknowledge`
225			`wire wb_err; // WB Error`
226			`wire wb_inta; // WB Interrupt`
227			`reg [dw-1:0] wb_dat; // WB Data out`
228			`ifdef GPIO_REGISTERED_WB_OUTPUTS
229			`reg wb_ack_o; // WB Acknowledge`
230			`reg wb_err_o; // WB Error`
231			`reg wb_inta_o; // WB Interrupt`
232			`reg [dw-1:0] wb_dat_o; // WB Data out`
233			`endif
234			`wire [gw-1:0] out_pad; // GPIO Outputs`
235			`ifdef GPIO_REGISTERED_IO_OUTPUTS
236	25	lampret	`reg [gw-1:0] ext_pad_o; // GPIO Outputs`
237	17	lampret	`endif
238			`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`
239			`wire pext_clk; // External clock for posedge flops`
240			`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`
241			`ifdef GPIO_NO_NEGEDGE_FLOPS
242			`else
243			`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`
244			`endif
245	14	lampret
246			`//`
247			`// All WISHBONE transfer terminations are successful except when:`
248			`// a) full address decoding is enabled and address doesn't match`
249			`// any of the GPIO registers`
250			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
251			`//`
252	17	lampret
253			`//`
254			`// WB Acknowledge`
255			`//`
256			`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`
257
258			`//`
259			`// Optional registration of WB Ack`
260			`//`
261			`ifdef GPIO_REGISTERED_WB_OUTPUTS
262			`always @(posedge wb_clk_i or posedge wb_rst_i)`
263			`if (wb_rst_i)`
264			`wb_ack_o <= #1 1'b0;`
265			`else`
266	23	lampret	`wb_ack_o <= #1 wb_ack & ~wb_ack_o;`
267	17	lampret	`else
268			`assign wb_ack_o = wb_ack;`
269			`endif
270
271			`//`
272			`// WB Error`
273			`//`
274	14	lampret	`ifdef GPIO_FULL_DECODE
275			`ifdef GPIO_STRICT_32BIT_ACCESS
276	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
277	14	lampret	`else
278	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`
279	14	lampret	`endif
280			`else
281			`ifdef GPIO_STRICT_32BIT_ACCESS
282	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
283	14	lampret	`else
284	17	lampret	`assign wb_err = 1'b0;`
285	14	lampret	`endif
286			`endif
287
288			`//`
289	17	lampret	`// Optional registration of WB error`
290	14	lampret	`//`
291	17	lampret	`ifdef GPIO_REGISTERED_WB_OUTPUTS
292			`always @(posedge wb_clk_i or posedge wb_rst_i)`
293			`if (wb_rst_i)`
294			`wb_err_o <= #1 1'b0;`
295			`else`
296	23	lampret	`wb_err_o <= #1 wb_err & ~wb_err_o;`
297	17	lampret	`else
298			`assign wb_err_o = wb_err;`
299			`endif
300	14	lampret
301			`//`
302			`// Full address decoder`
303			`//`
304			`ifdef GPIO_FULL_DECODE
305			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
306			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
307			`else
308			`assign full_decoding = 1'b1;`
309			`endif
310
311			`//`
312			`// GPIO registers address decoder`
313			`//`
314			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
315			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
316			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
317			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
318			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
319			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
320	21	lampret	assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
321	14	lampret
322			`//`
323			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
324			`//`
325			`ifdef GPIO_RGPIO_CTRL
326			`always @(posedge wb_clk_i or posedge wb_rst_i)`
327			`if (wb_rst_i)`
328			`rgpio_ctrl <= #1 4'b0;`
329			`else if (rgpio_ctrl_sel && wb_we_i)`
330			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
331			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
332	21	lampret	rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;
333	14	lampret	`else
334			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
335			`endif
336
337			`//`
338			`// Write to RGPIO_OUT`
339			`//`
340			`ifdef GPIO_RGPIO_OUT
341			`always @(posedge wb_clk_i or posedge wb_rst_i)`
342			`if (wb_rst_i)`
343			`rgpio_out <= #1 {gw{1'b0}};`
344			`else if (rgpio_out_sel && wb_we_i)`
345			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
346			`else
347	17	lampret	assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
348	14	lampret	`endif
349
350			`//`
351	17	lampret	`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`
352	14	lampret	`//`
353			`ifdef GPIO_RGPIO_OE
354			`always @(posedge wb_clk_i or posedge wb_rst_i)`
355			`if (wb_rst_i)`
356			`rgpio_oe <= #1 {gw{1'b0}};`
357			`else if (rgpio_oe_sel && wb_we_i)`
358	17	lampret	`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`
359	14	lampret	`else
360			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
361			`endif
362
363			`//`
364			`// Write to RGPIO_INTE`
365			`//`
366			`ifdef GPIO_RGPIO_INTE
367			`always @(posedge wb_clk_i or posedge wb_rst_i)`
368			`if (wb_rst_i)`
369			`rgpio_inte <= #1 {gw{1'b0}};`
370			`else if (rgpio_inte_sel && wb_we_i)`
371			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
372			`else
373			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
374			`endif
375
376			`//`
377			`// Write to RGPIO_PTRIG`
378			`//`
379			`ifdef GPIO_RGPIO_PTRIG
380			`always @(posedge wb_clk_i or posedge wb_rst_i)`
381			`if (wb_rst_i)`
382			`rgpio_ptrig <= #1 {gw{1'b0}};`
383			`else if (rgpio_ptrig_sel && wb_we_i)`
384			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
385			`else
386			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
387			`endif
388
389			`//`
390			`// Write to RGPIO_AUX`
391			`//`
392			`ifdef GPIO_RGPIO_AUX
393			`always @(posedge wb_clk_i or posedge wb_rst_i)`
394			`if (wb_rst_i)`
395			`rgpio_aux <= #1 {gw{1'b0}};`
396			`else if (rgpio_aux_sel && wb_we_i)`
397			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
398			`else
399			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
400			`endif
401
402			`//`
403			`// Latch into RGPIO_IN`
404			`//`
405			`ifdef GPIO_RGPIO_IN
406	17	lampret	`always @(posedge wb_clk_i or posedge wb_rst_i)`
407	14	lampret	`if (wb_rst_i)`
408			`rgpio_in <= #1 {gw{1'b0}};`
409			`else`
410	17	lampret	`rgpio_in <= #1 in_muxed;`
411	14	lampret	`else
412	17	lampret	`assign rgpio_in = in_muxed;`
413	14	lampret	`endif
414
415			`//`
416	17	lampret	`// Mux inputs directly from input pads with inputs sampled by external clock`
417	14	lampret	`//`
418	25	lampret	assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
419	17	lampret
420			`//`
421			`// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.`
422			`// If negedge flops are allowed, pext_clk only clocks posedge flops.`
423			`//`
424			`ifdef GPIO_NO_NEGEDGE_FLOPS
425	25	lampret	assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
426	17	lampret	`else
427	25	lampret	`assign pext_clk = clk_pad_i;`
428	17	lampret	`endif
429
430			`//`
431			`// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.`
432			`//`
433			`ifdef GPIO_NO_NEGEDGE_FLOPS
434			`assign extc_in = pextc_sampled;`
435			`else
436			assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
437			`endif
438
439			`//`
440			`// Latch using posedge external clock`
441			`//`
442			`always @(posedge pext_clk or posedge wb_rst_i)`
443			`if (wb_rst_i)`
444			`pextc_sampled <= #1 {gw{1'b0}};`
445			`else`
446	25	lampret	`pextc_sampled <= #1 ext_pad_i;`
447	17	lampret
448			`//`
449			`// Latch using negedge external clock`
450			`//`
451			`ifdef GPIO_NO_NEGEDGE_FLOPS
452			`else
453	25	lampret	`always @(negedge clk_pad_i or posedge wb_rst_i)`
454	17	lampret	`if (wb_rst_i)`
455			`nextc_sampled <= #1 {gw{1'b0}};`
456			`else`
457	25	lampret	`nextc_sampled <= #1 ext_pad_i;`
458	17	lampret	`endif
459
460			`//`
461			`// Mux all registers when doing a read of GPIO registers`
462			`//`
463	14	lampret	`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
464	22	lampret	`rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)`
465	14	lampret	case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
466			`ifdef GPIO_READREGS
467			`GPIO_RGPIO_OUT: begin
468	26	lampret	`wb_dat[dw-1:0] = rgpio_out;`
469	14	lampret	`end`
470			`GPIO_RGPIO_OE: begin
471	26	lampret	`wb_dat[dw-1:0] = ~rgpio_oe;`
472	14	lampret	`end`
473			`GPIO_RGPIO_INTE: begin
474	26	lampret	`wb_dat[dw-1:0] = rgpio_inte;`
475	14	lampret	`end`
476			`GPIO_RGPIO_PTRIG: begin
477	26	lampret	`wb_dat[dw-1:0] = rgpio_ptrig;`
478	14	lampret	`end`
479			`GPIO_RGPIO_AUX: begin
480	26	lampret	`wb_dat[dw-1:0] = rgpio_aux;`
481	14	lampret	`end`
482			`GPIO_RGPIO_CTRL: begin
483	20	lampret	`wb_dat[3:0] = rgpio_ctrl;`
484			`wb_dat[dw-1:4] = {dw-4{1'b0}};`
485	14	lampret	`end`
486			`endif
487	21	lampret	`GPIO_RGPIO_INTS: begin
488	26	lampret	`wb_dat[dw-1:0] = rgpio_ints;`
489	21	lampret	`end`
490	14	lampret	`default: begin`
491	26	lampret	`wb_dat[dw-1:0] = rgpio_in;`
492	14	lampret	`end`
493			`endcase`
494
495			`//`
496	17	lampret	`// WB data output`
497			`//`
498			`ifdef GPIO_REGISTERED_WB_OUTPUTS
499			`always @(posedge wb_clk_i or posedge wb_rst_i)`
500			`if (wb_rst_i)`

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