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[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  GPIO Testbench Tasks                                        ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Testbench tasks.                                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/21 21:39:27  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:37:23  lampret
// Test bench improvements.
//
// Revision 1.1  2001/06/05 07:45:22  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.v"
`include "gpio_defines.v"
`include "tb_defines.v"
 
module tb_tasks;
 
integer nr_failed;
integer ints_disabled;
integer ints_working;
integer local_errs;
 
parameter sh_addr = `GPIO_ADDRLH+1;
 
//
// Count/report failed tests
//
task failed;
begin
        $display("FAILED !!!");
        nr_failed = nr_failed + 1;
end
endtask
 
//
// Set RGPIO_OUT register
//
task setout;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_OE register
//
task setoe;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_INTE register
//
task setinte;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_PTRIG register
//
task setptrig;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_AUX register
//
task setaux;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_CTRL register
//
task setctrl;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Display RGPIO_IN register
//
task showin;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
        $write(" RGPIO_IN: %h", tmp);
end
 
endtask
 
//
// Display RGPIO_OUT register
//
task showout;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
        $write(" RGPIO_OUT: %h", tmp);
end
 
endtask
 
 
//
// Display RGPIO_OE register
//
task showoe;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
        $write(" RGPIO_OE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_INTE register
//
task showinte;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
        $write(" RGPIO_INTE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_PTRIG register
//
task showptrig;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
        $write(" RGPIO_PTRIG:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_AUX register
//
task showaux;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
        $write(" RGPIO_AUX:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_CTRL register
//
task showctrl;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
        $write(" RGPIO_CTRL: %h", tmp);
end
 
endtask
 
//
// Compare parameter with RGPIO_IN register
//
task comp_in;
input   [31:0]   val;
output          ret;
 
reg     [31:0]   tmp;
reg             ret;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
 
        if (tmp == val)
                ret = 1;
        else
                ret = 0;
end
 
endtask
 
//
// Get RGPIO_IN register
//
task getin;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OUT register
//
task getout;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OE register
//
task getoe;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_INTE register
//
task getinte;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_PTRIG register
//
task getptrig;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_AUX register
//
task getaux;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_CTRL register
//
task getctrl;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
end
 
endtask
 
//
// Calculate a random and make it narrow to fit on GPIO I/O pins
//
task random_gpio;
output  [31:0]   tmp;
 
begin
        tmp = $random & ((1<<`GPIO_IOS)-1);
end
 
endtask
 
//
// Test operation of control bit RGPIO_CTRL[ECLK]
//
task test_eclk;
integer         l1, l2, l3;
integer         r1, r2;
begin
 
        //
        // Phase 1
        //
        // GPIO uses WISHBONE clock to latch gpio_in
        //
 
        // Put something on gpio_in pins
        random_gpio(r1);
        tb_top.gpio_mon.set_gpioin(r1);
 
        // Reset GPIO_CTRL
        setctrl(0);
 
        // Wait for time to advance
        #1000;
 
        // Read GPIO_RGPIO_IN
        getin(l1);
 
        //
        // Phase 2
        //
        // GPIO uses external clock to latch gpio_in
        //
 
        // Set GPIO to use external clock
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
 
        // Put something else on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Wait for time to advance
        #1000;
 
        // Read GPIO_RGPIO_IN (should be the same as l1)
        getin(l2);
 
        // Make an external clock
        tb_top.gpio_mon.set_gpioeclk(0);
        #10;
        tb_top.gpio_mon.set_gpioeclk(1);
        #10;
 
        // Read RGPIO_IN (should be different than l2)
        getin(l3);
 
        //
        // Phase 3
        //
        // Compare phases
        //
        if (l1 == l2 && l2 == r1 && l3 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test operation of control bit RGPIO_CTRL[NEC]
//
task test_nec;
integer         l1, l2;
integer         r2;
begin
        //
        // Phase 1
        //
        // Compare RGPIO_IN before and after negative edge
        //
 
        // Clear GPIO_RGPIO_IN
        tb_top.gpio_mon.set_gpioin('d0);
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        // Advance time
        #1000;
 
        // Set GPIO to use external clock and set RGPIO_CTRL[NEC]
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
 
        // Put something on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Wait for time to advance
        #1000;
 
        // Read RGPIO_IN
        getin(l1);
 
        // Make an external clock
        tb_top.gpio_mon.set_gpioeclk(1);
        #10;
        tb_top.gpio_mon.set_gpioeclk(0);
        #10;
 
        // Read RGPIO_IN (should be different than l1)
        getin(l2);
 
        //
        // Phase 2
        //
        // Compare phases
        //
        if (!l1 && l2 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test input polled mode, output mode and bidirectional
//
task test_simple;
integer         l1, l2, l3, l4;
integer         i, err;
begin
        $write("  Testing input mode ...");
 
        //
        // Phase 1
        //
        // Compare RGPIO_IN and gpio_in
        //
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_in pins
                random_gpio(l1);
                tb_top.gpio_mon.set_gpioin(l1);
 
                // Advance time
                #1000;
 
                // Read GPIO_RGPIO_IN
                getin(l2);
 
                // Compare gpio_in and RGPIO_IN. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 2
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing output mode ...");
 
        //
        // Phase 3
        //
        // Compare RGPIO_OUT and gpio_out
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OUT pins
                l1 = $random;
                setout(l1);
 
                // Advance time
                #1000;
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l2);
 
                // Compare gpio_out and RGPIO_OUT. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 4
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing bidirectional I/O ...");
 
        //
        // Phase 5
        //
        // Compare RGPIO_OE and gpio_oen
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OE pins
                l1 = $random;
                setoe(l1);
 
                // Advance time
                #1000;
 
                // Read gpio_oen
                tb_top.gpio_mon.get_gpiooen(l2);
 
                // Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
                if (l1 != ~l2)
                        err = err + 1;
        end
 
        // Phase 6
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing auxiliary feature ...");
 
        //
        // Phase 7
        //
        // Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_aux pins
                l1 = $random;
                tb_top.gpio_mon.set_gpioaux(l1);
 
                // Put something in RGPIO_AUX pins
                l2 = $random;
                setaux(l2);
 
                // Put something in RGPIO_OUT pins
                l3 = $random;
                setout(l3);
 
                // Advance time
                #1000;
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l4);
 
                // Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
                // RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT 
                // bits are present on gpio_out and where
                if ((l1 & l2 | l3 & ~l2) != l4)
                        err = err + 1;
        end
 
        // Phase 8
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
end
endtask
 
//
// Test interrupts
//
task test_ints;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
 
        $write("  Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set gpio_in pins
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
                tb_top.gpio_mon.set_gpioin(r1);
 
                // Low level triggering
                setptrig(0);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio_top.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio_top.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio_top.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Test ptrig
//
task test_ptrig;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
        $write("  Testing ptrig features ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set bits to one
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
                // Set gpio_in pins
                tb_top.gpio_mon.set_gpioin('h00000000);
 
                // High level triggering
                setptrig('hffffffff);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio_top.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin('hffffffff);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio_top.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio_top.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Do continues check for interrupts
//
always @(posedge tb_top.gpio_top.wb_inta_o)
        if (ints_disabled) begin
                $display("Spurious interrupt detected. ");
                failed;
                ints_working = 9876;
                $display;
        end
 
//
// Start of testbench test tasks
//
integer         i;
initial begin
`ifdef DUMP_VCD
        $dumpfile("../sim/tb_top.vcd");
        $dumpvars(0);
`endif
        nr_failed = 0;
        ints_disabled = 1;
        ints_working = 0;
        tb_top.gpio_mon.set_gpioin(0);
        tb_top.gpio_mon.set_gpioaux(0);
        tb_top.gpio_mon.set_gpioeclk(0);
        $display;
        $display("###");
        $display("### GPIO IP Core Verification ###");
        $display("###");
        $display;
        $display("I. Testing correct operation of RGPIO_CTRL control bits");
        $display;
 
 
        $write("  Testing control bit RGPIO_CTRL[ECLK] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_eclk;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
 
        $write("  Testing control bit RGPIO_CTRL[NEC] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_nec;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
        test_ints;
 
        $display;
        $display("II. Testing modes of operation ...");
        $display;
 
        test_simple;
        test_ptrig;
 
        $display;
        $display("###");
        $display("### FAILED TESTS: %d ###", nr_failed);
        $display("###");
        $display;
        $finish;
end
 
endmodule

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Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	8	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// GPIO Testbench Tasks ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Testbench tasks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	12	lampret	`// Revision 1.1 2001/08/21 21:39:27 lampret`
48			`// Changed directory structure, port names and drfines.`
49			`//`
50	8	lampret	`// Revision 1.2 2001/07/14 20:37:23 lampret`
51			`// Test bench improvements.`
52			`//`
53			`// Revision 1.1 2001/06/05 07:45:22 lampret`
54			`// Added initial RTL and test benches. There are still some issues with these files.`
55			`//`
56			`//`
57
58			`include "timescale.v"
59	12	lampret	`include "gpio_defines.v"
60	8	lampret	`include "tb_defines.v"
61
62			`module tb_tasks;`
63
64			`integer nr_failed;`
65			`integer ints_disabled;`
66			`integer ints_working;`
67			`integer local_errs;`
68
69			parameter sh_addr = `GPIO_ADDRLH+1;
70
71			`//`
72			`// Count/report failed tests`
73			`//`
74			`task failed;`
75			`begin`
76			`$display("FAILED !!!");`
77			`nr_failed = nr_failed + 1;`
78			`end`
79			`endtask`
80
81			`//`
82			`// Set RGPIO_OUT register`
83			`//`
84			`task setout;`
85			`input [31:0] val;`
86
87			`begin`
88			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
89			`end`
90
91			`endtask`
92
93			`//`
94			`// Set RGPIO_OE register`
95			`//`
96			`task setoe;`
97			`input [31:0] val;`
98
99			`begin`
100			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
101			`end`
102
103			`endtask`
104
105			`//`
106			`// Set RGPIO_INTE register`
107			`//`
108			`task setinte;`
109			`input [31:0] val;`
110
111			`begin`
112			#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
113			`end`
114
115			`endtask`
116
117			`//`
118			`// Set RGPIO_PTRIG register`
119			`//`
120			`task setptrig;`
121			`input [31:0] val;`
122
123			`begin`
124			#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
125			`end`
126
127			`endtask`
128
129			`//`
130			`// Set RGPIO_AUX register`
131			`//`
132			`task setaux;`
133			`input [31:0] val;`
134
135			`begin`
136			#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
137			`end`
138
139			`endtask`
140
141			`//`
142			`// Set RGPIO_CTRL register`
143			`//`
144			`task setctrl;`
145			`input [31:0] val;`
146
147			`begin`
148			#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
149			`end`
150
151			`endtask`
152
153			`//`
154			`// Display RGPIO_IN register`
155			`//`
156			`task showin;`
157
158			`reg [31:0] tmp;`
159			`begin`
160			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
161			`$write(" RGPIO_IN: %h", tmp);`
162			`end`
163
164			`endtask`
165
166			`//`
167			`// Display RGPIO_OUT register`
168			`//`
169			`task showout;`
170
171			`reg [31:0] tmp;`
172			`begin`
173			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
174			`$write(" RGPIO_OUT: %h", tmp);`
175			`end`
176
177			`endtask`
178
179
180			`//`
181			`// Display RGPIO_OE register`
182			`//`
183			`task showoe;`
184
185			`reg [31:0] tmp;`
186			`begin`
187			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
188			`$write(" RGPIO_OE:%h", tmp);`
189			`end`
190
191			`endtask`
192
193			`//`
194			`// Display RGPIO_INTE register`
195			`//`
196			`task showinte;`
197
198			`reg [31:0] tmp;`
199			`begin`
200			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
201			`$write(" RGPIO_INTE:%h", tmp);`
202			`end`
203
204			`endtask`
205
206			`//`
207			`// Display RGPIO_PTRIG register`
208			`//`
209			`task showptrig;`
210
211			`reg [31:0] tmp;`
212			`begin`
213			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
214			`$write(" RGPIO_PTRIG:%h", tmp);`
215			`end`
216
217			`endtask`
218
219			`//`
220			`// Display RGPIO_AUX register`
221			`//`
222			`task showaux;`
223
224			`reg [31:0] tmp;`
225			`begin`
226			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
227			`$write(" RGPIO_AUX:%h", tmp);`
228			`end`
229
230			`endtask`
231
232			`//`
233			`// Display RGPIO_CTRL register`
234			`//`
235			`task showctrl;`
236
237			`reg [31:0] tmp;`
238			`begin`
239			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
240			`$write(" RGPIO_CTRL: %h", tmp);`
241			`end`
242
243			`endtask`
244
245			`//`
246			`// Compare parameter with RGPIO_IN register`
247			`//`
248			`task comp_in;`
249			`input [31:0] val;`
250			`output ret;`
251
252			`reg [31:0] tmp;`
253			`reg ret;`
254			`begin`
255			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
256
257			`if (tmp == val)`
258			`ret = 1;`
259			`else`
260			`ret = 0;`
261			`end`
262
263			`endtask`
264
265			`//`
266			`// Get RGPIO_IN register`
267			`//`
268			`task getin;`
269			`output [31:0] tmp;`
270
271			`begin`
272			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
273			`end`
274
275			`endtask`
276
277			`//`
278			`// Get RGPIO_OUT register`
279			`//`
280			`task getout;`
281			`output [31:0] tmp;`
282
283			`begin`
284			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
285			`end`
286
287			`endtask`
288
289			`//`
290			`// Get RGPIO_OE register`
291			`//`
292			`task getoe;`
293			`output [31:0] tmp;`
294
295			`begin`
296			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
297			`end`
298
299			`endtask`
300
301			`//`
302			`// Get RGPIO_INTE register`
303			`//`
304			`task getinte;`
305			`output [31:0] tmp;`
306
307			`begin`
308			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
309			`end`
310
311			`endtask`
312
313			`//`
314			`// Get RGPIO_PTRIG register`
315			`//`
316			`task getptrig;`
317			`output [31:0] tmp;`
318
319			`begin`
320			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
321			`end`
322
323			`endtask`
324
325			`//`
326			`// Get RGPIO_AUX register`
327			`//`
328			`task getaux;`
329			`output [31:0] tmp;`
330
331			`begin`
332			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
333			`end`
334
335			`endtask`
336
337			`//`
338			`// Get RGPIO_CTRL register`
339			`//`
340			`task getctrl;`
341			`output [31:0] tmp;`
342
343			`begin`
344			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
345			`end`
346
347			`endtask`
348
349			`//`
350			`// Calculate a random and make it narrow to fit on GPIO I/O pins`
351			`//`
352			`task random_gpio;`
353			`output [31:0] tmp;`
354
355			`begin`
356			tmp = $random & ((1<<`GPIO_IOS)-1);
357			`end`
358
359			`endtask`
360
361			`//`
362			`// Test operation of control bit RGPIO_CTRL[ECLK]`
363			`//`
364			`task test_eclk;`
365			`integer l1, l2, l3;`
366			`integer r1, r2;`
367			`begin`
368
369			`//`
370			`// Phase 1`
371			`//`
372			`// GPIO uses WISHBONE clock to latch gpio_in`
373			`//`
374
375			`// Put something on gpio_in pins`
376			`random_gpio(r1);`
377			`tb_top.gpio_mon.set_gpioin(r1);`
378
379			`// Reset GPIO_CTRL`
380			`setctrl(0);`
381
382			`// Wait for time to advance`
383			`#1000;`
384
385			`// Read GPIO_RGPIO_IN`
386			`getin(l1);`
387
388			`//`
389			`// Phase 2`
390			`//`
391			`// GPIO uses external clock to latch gpio_in`
392			`//`
393
394			`// Set GPIO to use external clock`
395			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
396
397			`// Put something else on gpio_in pins`
398			`random_gpio(r2);`
399			`tb_top.gpio_mon.set_gpioin(r2);`
400
401			`// Wait for time to advance`
402			`#1000;`
403
404			`// Read GPIO_RGPIO_IN (should be the same as l1)`
405			`getin(l2);`
406
407			`// Make an external clock`
408			`tb_top.gpio_mon.set_gpioeclk(0);`
409			`#10;`
410			`tb_top.gpio_mon.set_gpioeclk(1);`
411			`#10;`
412
413			`// Read RGPIO_IN (should be different than l2)`
414			`getin(l3);`
415
416			`//`
417			`// Phase 3`
418			`//`
419			`// Compare phases`
420			`//`
421			`if (l1 == l2 && l2 == r1 && l3 == r2)`
422			`$write(".");`
423			`else`
424			`local_errs = local_errs + 1;`
425			`end`
426			`endtask`
427
428			`//`
429			`// Test operation of control bit RGPIO_CTRL[NEC]`
430			`//`
431			`task test_nec;`
432			`integer l1, l2;`
433			`integer r2;`
434			`begin`
435			`//`
436			`// Phase 1`
437			`//`
438			`// Compare RGPIO_IN before and after negative edge`
439			`//`
440
441			`// Clear GPIO_RGPIO_IN`
442			`tb_top.gpio_mon.set_gpioin('d0);`
443
444			`// Set GPIO to use WB clock`
445			`setctrl(0);`
446
447			`// Advance time`
448			`#1000;`
449
450			`// Set GPIO to use external clock and set RGPIO_CTRL[NEC]`
451			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK \| 1 << `GPIO_RGPIO_CTRL_NEC);
452
453			`// Put something on gpio_in pins`
454			`random_gpio(r2);`
455			`tb_top.gpio_mon.set_gpioin(r2);`
456
457			`// Wait for time to advance`
458			`#1000;`
459
460			`// Read RGPIO_IN`
461			`getin(l1);`
462
463			`// Make an external clock`
464			`tb_top.gpio_mon.set_gpioeclk(1);`
465			`#10;`
466			`tb_top.gpio_mon.set_gpioeclk(0);`
467			`#10;`
468
469			`// Read RGPIO_IN (should be different than l1)`
470			`getin(l2);`
471
472			`//`
473			`// Phase 2`
474			`//`
475			`// Compare phases`
476			`//`
477			`if (!l1 && l2 == r2)`
478			`$write(".");`
479			`else`
480			`local_errs = local_errs + 1;`
481			`end`
482			`endtask`
483
484			`//`
485			`// Test input polled mode, output mode and bidirectional`
486			`//`
487			`task test_simple;`
488			`integer l1, l2, l3, l4;`
489			`integer i, err;`
490			`begin`
491			`$write(" Testing input mode ...");`
492
493			`//`
494			`// Phase 1`
495			`//`
496			`// Compare RGPIO_IN and gpio_in`
497			`//`
498
499			`// Set GPIO to use WB clock`
500			`setctrl(0);`
501
502			`err = 0;`
503			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
504			`// Put something on gpio_in pins`
505			`random_gpio(l1);`
506			`tb_top.gpio_mon.set_gpioin(l1);`
507
508			`// Advance time`
509			`#1000;`
510
511			`// Read GPIO_RGPIO_IN`
512			`getin(l2);`
513
514			`// Compare gpio_in and RGPIO_IN. Should be equal.`
515			`if (l1 != l2)`
516			`err = err + 1;`
517			`end`
518
519			`// Phase 2`
520			`//`
521			`// Output result for previous test`
522			`//`
523			`if (!err)`
524			`$display(" OK");`
525			`else`
526			`failed;`
527
528			`$write(" Testing output mode ...");`
529
530			`//`
531			`// Phase 3`
532			`//`
533			`// Compare RGPIO_OUT and gpio_out`
534			`//`
535
536			`err = 0;`
537			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
538			`// Put something in RGPIO_OUT pins`
539			`l1 = $random;`
540			`setout(l1);`
541
542			`// Advance time`
543			`#1000;`
544
545			`// Read gpio_out`
546			`tb_top.gpio_mon.get_gpioout(l2);`
547
548			`// Compare gpio_out and RGPIO_OUT. Should be equal.`
549			`if (l1 != l2)`
550			`err = err + 1;`
551			`end`
552
553			`// Phase 4`
554			`//`
555			`// Output result for previous test`
556			`//`
557			`if (!err)`
558			`$display(" OK");`
559			`else`
560			`failed;`
561
562			`$write(" Testing bidirectional I/O ...");`
563
564			`//`
565			`// Phase 5`
566			`//`
567			`// Compare RGPIO_OE and gpio_oen`
568			`//`
569
570			`err = 0;`
571			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
572			`// Put something in RGPIO_OE pins`
573			`l1 = $random;`
574			`setoe(l1);`
575
576			`// Advance time`
577			`#1000;`
578
579			`// Read gpio_oen`
580			`tb_top.gpio_mon.get_gpiooen(l2);`
581
582			`// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.`
583			`if (l1 != ~l2)`
584			`err = err + 1;`
585			`end`
586
587			`// Phase 6`
588			`//`
589			`// Output result for previous test`
590			`//`
591			`if (!err)`
592			`$display(" OK");`
593			`else`
594			`failed;`
595
596			`$write(" Testing auxiliary feature ...");`
597
598			`//`
599			`// Phase 7`
600			`//`
601			`// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux`
602			`//`
603
604			`err = 0;`
605			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
606			`// Put something on gpio_aux pins`
607			`l1 = $random;`
608			`tb_top.gpio_mon.set_gpioaux(l1);`
609
610			`// Put something in RGPIO_AUX pins`
611			`l2 = $random;`
612			`setaux(l2);`
613
614			`// Put something in RGPIO_OUT pins`
615			`l3 = $random;`
616			`setout(l3);`
617
618			`// Advance time`
619			`#1000;`
620
621			`// Read gpio_out`
622			`tb_top.gpio_mon.get_gpioout(l4);`
623
624			`// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.`
625			`// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT`
626			`// bits are present on gpio_out and where`
627			`if ((l1 & l2 \| l3 & ~l2) != l4)`
628			`err = err + 1;`
629			`end`
630
631			`// Phase 8`
632			`//`
633			`// Output result for previous test`
634			`//`
635			`if (!err)`
636			`$display(" OK");`
637			`else`
638			`failed;`
639
640			`end`
641			`endtask`
642
643			`//`
644			`// Test interrupts`
645			`//`
646			`task test_ints;`
647			`integer l1, l2, l3;`
648			`integer i, rnd, err;`
649			`integer r1;`
650			`begin`
651
652			`$write(" Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");`
653
654			`//`
655			`// Phase 1`
656			`//`
657			`// Generate patterns on inputs in interrupt mode`
658			`//`
659
660			`// Disable spurious interrupt monitor`
661			`ints_disabled = 0;`
662
663			`err = 0;`
664			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
665
666			`// Set gpio_in pins`
667			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
668			`tb_top.gpio_mon.set_gpioin(r1);`
669
670			`// Low level triggering`
671			`setptrig(0);`
672
673			`// Enable interrupts in RGPIO_CTRL`
674			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
675
676			`// Enable interrupts in RGPIO_INTE`
677			`setinte(r1);`
678
679			`// Advance time`
680			`#100;`
681
682			`// Sample interrupt request. Should be zero.`
683	12	lampret	`l1 = tb_top.gpio_top.wb_inta_o;`
684	8	lampret
685			`// Clear gpio_in pins`
686			`tb_top.gpio_mon.set_gpioin(0);`
687
688			`// Advance time`
689			`#100;`
690
691			`// Sample interrupt request. Should be one.`
692	12	lampret	`l2 = tb_top.gpio_top.wb_inta_o;`
693	8	lampret
694			`// Clear interrupt request`
695			`setctrl(0);`
696
697			`// Advance time`
698			`#100;`
699
700			`// Sample interrupt request. Should be zero.`
701	12	lampret	`l3 = tb_top.gpio_top.wb_inta_o;`
702	8	lampret
703			`// Check for errors`
704			`if (l1 \|\| !l2 \|\| l3)`
705			`err = err +1;`
706			`end`
707
708			`// Enable spurious interrupt monitor`
709			`ints_disabled = 1;`
710
711			`// Phase 2`
712			`//`
713			`// Check results`
714			`//`
715			`if (!err)`
716			`$display(" OK");`
717			`else`
718			`failed;`
719			`end`
720			`endtask`
721
722			`//`
723			`// Test ptrig`
724			`//`
725			`task test_ptrig;`
726			`integer l1, l2, l3;`
727			`integer i, rnd, err;`
728			`integer r1;`
729			`begin`
730			`$write(" Testing ptrig features ...");`
731
732			`//`
733			`// Phase 1`
734			`//`
735			`// Generate patterns on inputs in interrupt mode`
736			`//`
737
738			`// Disable spurious interrupt monitor`
739			`ints_disabled = 0;`
740
741			`err = 0;`
742			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
743
744			`// Set bits to one`
745			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
746
747			`// Set gpio_in pins`
748			`tb_top.gpio_mon.set_gpioin('h00000000);`
749
750			`// High level triggering`
751			`setptrig('hffffffff);`
752
753			`// Enable interrupts in RGPIO_CTRL`
754			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
755
756			`// Enable interrupts in RGPIO_INTE`
757			`setinte(r1);`
758
759			`// Advance time`
760			`#100;`
761
762			`// Sample interrupt request. Should be zero.`
763	12	lampret	`l1 = tb_top.gpio_top.wb_inta_o;`
764	8	lampret
765			`// Clear gpio_in pins`
766			`tb_top.gpio_mon.set_gpioin('hffffffff);`
767
768			`// Advance time`
769			`#100;`
770
771			`// Sample interrupt request. Should be one.`
772	12	lampret	`l2 = tb_top.gpio_top.wb_inta_o;`
773	8	lampret
774			`// Clear interrupt request`
775			`setctrl(0);`
776
777			`// Advance time`
778			`#100;`
779
780			`// Sample interrupt request. Should be zero.`
781	12	lampret	`l3 = tb_top.gpio_top.wb_inta_o;`
782	8	lampret
783			`// Check for errors`
784			`if (l1 \|\| !l2 \|\| l3)`
785			`err = err +1;`
786			`end`
787
788			`// Enable spurious interrupt monitor`
789			`ints_disabled = 1;`
790
791			`// Phase 2`
792			`//`
793			`// Check results`
794			`//`
795			`if (!err)`
796			`$display(" OK");`
797			`else`
798			`failed;`
799			`end`
800			`endtask`
801
802			`//`
803			`// Do continues check for interrupts`
804			`//`
805	12	lampret	`always @(posedge tb_top.gpio_top.wb_inta_o)`
806	8	lampret	`if (ints_disabled) begin`
807			`$display("Spurious interrupt detected. ");`
808			`failed;`
809			`ints_working = 9876;`
810			`$display;`
811			`end`
812
813			`//`
814			`// Start of testbench test tasks`
815			`//`
816			`integer i;`
817			`initial begin`
818			`ifdef DUMP_VCD
819			`$dumpfile("../sim/tb_top.vcd");`
820			`$dumpvars(0);`
821			`endif
822			`nr_failed = 0;`
823			`ints_disabled = 1;`
824			`ints_working = 0;`
825			`tb_top.gpio_mon.set_gpioin(0);`
826			`tb_top.gpio_mon.set_gpioaux(0);`
827			`tb_top.gpio_mon.set_gpioeclk(0);`
828			`$display;`
829			`$display("###");`
830			`$display("### GPIO IP Core Verification ###");`
831			`$display("###");`
832			`$display;`
833			`$display("I. Testing correct operation of RGPIO_CTRL control bits");`
834			`$display;`
835
836
837			`$write(" Testing control bit RGPIO_CTRL[ECLK] ...");`
838			`local_errs = 0;`
839			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
840			`test_eclk;`
841			`if (local_errs == 0)`
842			`$display(" OK");`
843			`else`
844			`failed;`
845
846
847			`$write(" Testing control bit RGPIO_CTRL[NEC] ...");`
848			`local_errs = 0;`
849			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
850			`test_nec;`
851			`if (local_errs == 0)`
852			`$display(" OK");`
853			`else`
854			`failed;`
855
856			`test_ints;`
857
858			`$display;`
859			`$display("II. Testing modes of operation ...");`
860			`$display;`
861
862			`test_simple;`
863			`test_ptrig;`
864
865			`$display;`
866			`$display("###");`
867			`$display("### FAILED TESTS: %d ###", nr_failed);`
868			`$display("###");`
869			`$display;`
870			`$finish;`
871			`end`
872
873			`endmodule`