URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 13

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  GPIO Testbench Tasks                                        ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Testbench tasks.                                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/09/18 15:43:27  lampret
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:27  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:37:23  lampret
// Test bench improvements.
//
// Revision 1.1  2001/06/05 07:45:22  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.v"
`include "gpio_defines.v"
`include "tb_defines.v"
 
module tb_tasks;
 
integer nr_failed;
integer ints_disabled;
integer ints_working;
integer local_errs;
 
parameter sh_addr = `GPIO_ADDRLH+1;
 
//
// Count/report failed tests
//
task failed;
begin
        $display("FAILED !!!");
        nr_failed = nr_failed + 1;
end
endtask
 
//
// Set RGPIO_OUT register
//
task setout;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_OE register
//
task setoe;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_INTE register
//
task setinte;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_PTRIG register
//
task setptrig;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_AUX register
//
task setaux;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_CTRL register
//
task setctrl;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Display RGPIO_IN register
//
task showin;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
        $write(" RGPIO_IN: %h", tmp);
end
 
endtask
 
//
// Display RGPIO_OUT register
//
task showout;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
        $write(" RGPIO_OUT: %h", tmp);
end
 
endtask
 
 
//
// Display RGPIO_OE register
//
task showoe;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
        $write(" RGPIO_OE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_INTE register
//
task showinte;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
        $write(" RGPIO_INTE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_PTRIG register
//
task showptrig;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
        $write(" RGPIO_PTRIG:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_AUX register
//
task showaux;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
        $write(" RGPIO_AUX:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_CTRL register
//
task showctrl;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
        $write(" RGPIO_CTRL: %h", tmp);
end
 
endtask
 
//
// Compare parameter with RGPIO_IN register
//
task comp_in;
input   [31:0]   val;
output          ret;
 
reg     [31:0]   tmp;
reg             ret;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
 
        if (tmp == val)
                ret = 1;
        else
                ret = 0;
end
 
endtask
 
//
// Get RGPIO_IN register
//
task getin;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OUT register
//
task getout;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OE register
//
task getoe;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_INTE register
//
task getinte;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_PTRIG register
//
task getptrig;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_AUX register
//
task getaux;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_CTRL register
//
task getctrl;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
end
 
endtask
 
//
// Calculate a random and make it narrow to fit on GPIO I/O pins
//
task random_gpio;
output  [31:0]   tmp;
 
begin
        tmp = $random & ((1<<`GPIO_IOS)-1);
end
 
endtask
 
//
// Test operation of control bit RGPIO_CTRL[ECLK]
//
task test_eclk;
integer         l1, l2, l3;
integer         r1, r2;
begin
 
        //
        // Phase 1
        //
        // GPIO uses WISHBONE clock to latch gpio_in
        //
 
        // Put something on gpio_in pins
        random_gpio(r1);
        tb_top.gpio_mon.set_gpioin(r1);
 
        // Reset GPIO_CTRL
        setctrl(0);
 
        // Wait for time to advance
        #1000;
 
        // Read GPIO_RGPIO_IN
        getin(l1);
 
        //
        // Phase 2
        //
        // GPIO uses external clock to latch gpio_in
        //
 
        // Set GPIO to use external clock
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
 
        // Put something else on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Wait for time to advance
        #1000;
 
        // Read GPIO_RGPIO_IN (should be the same as l1)
        getin(l2);
 
        // Make an external clock
        tb_top.gpio_mon.set_gpioeclk(0);
        #10;
        tb_top.gpio_mon.set_gpioeclk(1);
        #10;
 
        // Read RGPIO_IN (should be different than l2)
        getin(l3);
 
        //
        // Phase 3
        //
        // Compare phases
        //
        if (l1 == l2 && l2 == r1 && l3 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test operation of control bit RGPIO_CTRL[NEC]
//
task test_nec;
integer         l1, l2;
integer         r2;
begin
        //
        // Phase 1
        //
        // Compare RGPIO_IN before and after negative edge
        //
 
        // Clear GPIO_RGPIO_IN
        tb_top.gpio_mon.set_gpioin('d0);
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        // Advance time
        #1000;
 
        // Set GPIO to use external clock and set RGPIO_CTRL[NEC]
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
 
        // Put something on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Wait for time to advance
        #1000;
 
        // Read RGPIO_IN
        getin(l1);
 
        // Make an external clock
        tb_top.gpio_mon.set_gpioeclk(1);
        #10;
        tb_top.gpio_mon.set_gpioeclk(0);
        #10;
 
        // Read RGPIO_IN (should be different than l1)
        getin(l2);
 
        //
        // Phase 2
        //
        // Compare phases
        //
        if (!l1 && l2 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test input polled mode, output mode and bidirectional
//
task test_simple;
integer         l1, l2, l3, l4;
integer         i, err;
begin
        $write("  Testing input mode ...");
 
        //
        // Phase 1
        //
        // Compare RGPIO_IN and gpio_in
        //
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_in pins
                random_gpio(l1);
                tb_top.gpio_mon.set_gpioin(l1);
 
                // Advance time
                #1000;
 
                // Read GPIO_RGPIO_IN
                getin(l2);
 
                // Compare gpio_in and RGPIO_IN. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 2
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing output mode ...");
 
        //
        // Phase 3
        //
        // Compare RGPIO_OUT and gpio_out
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OUT pins
                l1 = $random;
                setout(l1);
 
                // Advance time
                #1000;
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l2);
 
                // Compare gpio_out and RGPIO_OUT. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 4
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing bidirectional I/O ...");
 
        //
        // Phase 5
        //
        // Compare RGPIO_OE and gpio_oen
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OE pins
                l1 = $random;
                setoe(l1);
 
                // Advance time
                #1000;
 
                // Read gpio_oen
                tb_top.gpio_mon.get_gpiooen(l2);
 
                // Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
                if (l1 != ~l2)
                        err = err + 1;
        end
 
        // Phase 6
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing auxiliary feature ...");
 
        //
        // Phase 7
        //
        // Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_aux pins
                l1 = $random;
                tb_top.gpio_mon.set_gpioaux(l1);
 
                // Put something in RGPIO_AUX pins
                l2 = $random;
                setaux(l2);
 
                // Put something in RGPIO_OUT pins
                l3 = $random;
                setout(l3);
 
                // Advance time
                #1000;
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l4);
 
                // Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
                // RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT 
                // bits are present on gpio_out and where
                if ((l1 & l2 | l3 & ~l2) != l4)
                        err = err + 1;
        end
 
        // Phase 8
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
end
endtask
 
//
// Test interrupts
//
task test_ints;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
 
        $write("  Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set gpio_in pins
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
                tb_top.gpio_mon.set_gpioin(r1);
 
                // Low level triggering
                setptrig(0);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio_top.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio_top.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio_top.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Test ptrig
//
task test_ptrig;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
        $write("  Testing ptrig features ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set bits to one
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
                // Set gpio_in pins
                tb_top.gpio_mon.set_gpioin('h00000000);
 
                // High level triggering
                setptrig('hffffffff);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio_top.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin('hffffffff);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio_top.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                #100;
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio_top.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Do continues check for interrupts
//
always @(posedge tb_top.gpio_top.wb_inta_o)
        if (ints_disabled) begin
                $display("Spurious interrupt detected. ");
                failed;
                ints_working = 9876;
                $display;
        end
 
//
// Start of testbench test tasks
//
integer         i;
initial begin
`ifdef DUMP_VCD
        $dumpfile("../out/tb_top.vcd");
        $dumpvars(0);
`endif
        nr_failed = 0;
        ints_disabled = 1;
        ints_working = 0;
        tb_top.gpio_mon.set_gpioin(0);
        tb_top.gpio_mon.set_gpioaux(0);
        tb_top.gpio_mon.set_gpioeclk(0);
        $display;
        $display("###");
        $display("### GPIO IP Core Verification ###");
        $display("###");
        $display;
        $display("I. Testing correct operation of RGPIO_CTRL control bits");
        $display;
 
 
        $write("  Testing control bit RGPIO_CTRL[ECLK] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_eclk;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
 
        $write("  Testing control bit RGPIO_CTRL[NEC] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_nec;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
        test_ints;
 
        $display;
        $display("II. Testing modes of operation ...");
        $display;
 
        test_simple;
        test_ptrig;
 
        $display;
        $display("###");
        $display("### FAILED TESTS: %d ###", nr_failed);
        $display("###");
        $display;
        $finish;
end
 
endmodule

Browse

Tools

Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 13

Line No.	Rev	Author	Line
1	8	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// GPIO Testbench Tasks ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Testbench tasks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	13	lampret	`// Revision 1.2 2001/09/18 15:43:27 lampret`
48			`// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.`
49			`//`
50	12	lampret	`// Revision 1.1 2001/08/21 21:39:27 lampret`
51			`// Changed directory structure, port names and drfines.`
52			`//`
53	8	lampret	`// Revision 1.2 2001/07/14 20:37:23 lampret`
54			`// Test bench improvements.`
55			`//`
56			`// Revision 1.1 2001/06/05 07:45:22 lampret`
57			`// Added initial RTL and test benches. There are still some issues with these files.`
58			`//`
59			`//`
60
61			`include "timescale.v"
62	12	lampret	`include "gpio_defines.v"
63	8	lampret	`include "tb_defines.v"
64
65			`module tb_tasks;`
66
67			`integer nr_failed;`
68			`integer ints_disabled;`
69			`integer ints_working;`
70			`integer local_errs;`
71
72			parameter sh_addr = `GPIO_ADDRLH+1;
73
74			`//`
75			`// Count/report failed tests`
76			`//`
77			`task failed;`
78			`begin`
79			`$display("FAILED !!!");`
80			`nr_failed = nr_failed + 1;`
81			`end`
82			`endtask`
83
84			`//`
85			`// Set RGPIO_OUT register`
86			`//`
87			`task setout;`
88			`input [31:0] val;`
89
90			`begin`
91			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
92			`end`
93
94			`endtask`
95
96			`//`
97			`// Set RGPIO_OE register`
98			`//`
99			`task setoe;`
100			`input [31:0] val;`
101
102			`begin`
103			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
104			`end`
105
106			`endtask`
107
108			`//`
109			`// Set RGPIO_INTE register`
110			`//`
111			`task setinte;`
112			`input [31:0] val;`
113
114			`begin`
115			#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
116			`end`
117
118			`endtask`
119
120			`//`
121			`// Set RGPIO_PTRIG register`
122			`//`
123			`task setptrig;`
124			`input [31:0] val;`
125
126			`begin`
127			#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
128			`end`
129
130			`endtask`
131
132			`//`
133			`// Set RGPIO_AUX register`
134			`//`
135			`task setaux;`
136			`input [31:0] val;`
137
138			`begin`
139			#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
140			`end`
141
142			`endtask`
143
144			`//`
145			`// Set RGPIO_CTRL register`
146			`//`
147			`task setctrl;`
148			`input [31:0] val;`
149
150			`begin`
151			#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
152			`end`
153
154			`endtask`
155
156			`//`
157			`// Display RGPIO_IN register`
158			`//`
159			`task showin;`
160
161			`reg [31:0] tmp;`
162			`begin`
163			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
164			`$write(" RGPIO_IN: %h", tmp);`
165			`end`
166
167			`endtask`
168
169			`//`
170			`// Display RGPIO_OUT register`
171			`//`
172			`task showout;`
173
174			`reg [31:0] tmp;`
175			`begin`
176			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
177			`$write(" RGPIO_OUT: %h", tmp);`
178			`end`
179
180			`endtask`
181
182
183			`//`
184			`// Display RGPIO_OE register`
185			`//`
186			`task showoe;`
187
188			`reg [31:0] tmp;`
189			`begin`
190			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
191			`$write(" RGPIO_OE:%h", tmp);`
192			`end`
193
194			`endtask`
195
196			`//`
197			`// Display RGPIO_INTE register`
198			`//`
199			`task showinte;`
200
201			`reg [31:0] tmp;`
202			`begin`
203			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
204			`$write(" RGPIO_INTE:%h", tmp);`
205			`end`
206
207			`endtask`
208
209			`//`
210			`// Display RGPIO_PTRIG register`
211			`//`
212			`task showptrig;`
213
214			`reg [31:0] tmp;`
215			`begin`
216			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
217			`$write(" RGPIO_PTRIG:%h", tmp);`
218			`end`
219
220			`endtask`
221
222			`//`
223			`// Display RGPIO_AUX register`
224			`//`
225			`task showaux;`
226
227			`reg [31:0] tmp;`
228			`begin`
229			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
230			`$write(" RGPIO_AUX:%h", tmp);`
231			`end`
232
233			`endtask`
234
235			`//`
236			`// Display RGPIO_CTRL register`
237			`//`
238			`task showctrl;`
239
240			`reg [31:0] tmp;`
241			`begin`
242			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
243			`$write(" RGPIO_CTRL: %h", tmp);`
244			`end`
245
246			`endtask`
247
248			`//`
249			`// Compare parameter with RGPIO_IN register`
250			`//`
251			`task comp_in;`
252			`input [31:0] val;`
253			`output ret;`
254
255			`reg [31:0] tmp;`
256			`reg ret;`
257			`begin`
258			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
259
260			`if (tmp == val)`
261			`ret = 1;`
262			`else`
263			`ret = 0;`
264			`end`
265
266			`endtask`
267
268			`//`
269			`// Get RGPIO_IN register`
270			`//`
271			`task getin;`
272			`output [31:0] tmp;`
273
274			`begin`
275			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
276			`end`
277
278			`endtask`
279
280			`//`
281			`// Get RGPIO_OUT register`
282			`//`
283			`task getout;`
284			`output [31:0] tmp;`
285
286			`begin`
287			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
288			`end`
289
290			`endtask`
291
292			`//`
293			`// Get RGPIO_OE register`
294			`//`
295			`task getoe;`
296			`output [31:0] tmp;`
297
298			`begin`
299			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
300			`end`
301
302			`endtask`
303
304			`//`
305			`// Get RGPIO_INTE register`
306			`//`
307			`task getinte;`
308			`output [31:0] tmp;`
309
310			`begin`
311			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
312			`end`
313
314			`endtask`
315
316			`//`
317			`// Get RGPIO_PTRIG register`
318			`//`
319			`task getptrig;`
320			`output [31:0] tmp;`
321
322			`begin`
323			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
324			`end`
325
326			`endtask`
327
328			`//`
329			`// Get RGPIO_AUX register`
330			`//`
331			`task getaux;`
332			`output [31:0] tmp;`
333
334			`begin`
335			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
336			`end`
337
338			`endtask`
339
340			`//`
341			`// Get RGPIO_CTRL register`
342			`//`
343			`task getctrl;`
344			`output [31:0] tmp;`
345
346			`begin`
347			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
348			`end`
349
350			`endtask`
351
352			`//`
353			`// Calculate a random and make it narrow to fit on GPIO I/O pins`
354			`//`
355			`task random_gpio;`
356			`output [31:0] tmp;`
357
358			`begin`
359			tmp = $random & ((1<<`GPIO_IOS)-1);
360			`end`
361
362			`endtask`
363
364			`//`
365			`// Test operation of control bit RGPIO_CTRL[ECLK]`
366			`//`
367			`task test_eclk;`
368			`integer l1, l2, l3;`
369			`integer r1, r2;`
370			`begin`
371
372			`//`
373			`// Phase 1`
374			`//`
375			`// GPIO uses WISHBONE clock to latch gpio_in`
376			`//`
377
378			`// Put something on gpio_in pins`
379			`random_gpio(r1);`
380			`tb_top.gpio_mon.set_gpioin(r1);`
381
382			`// Reset GPIO_CTRL`
383			`setctrl(0);`
384
385			`// Wait for time to advance`
386			`#1000;`
387
388			`// Read GPIO_RGPIO_IN`
389			`getin(l1);`
390
391			`//`
392			`// Phase 2`
393			`//`
394			`// GPIO uses external clock to latch gpio_in`
395			`//`
396
397			`// Set GPIO to use external clock`
398			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
399
400			`// Put something else on gpio_in pins`
401			`random_gpio(r2);`
402			`tb_top.gpio_mon.set_gpioin(r2);`
403
404			`// Wait for time to advance`
405			`#1000;`
406
407			`// Read GPIO_RGPIO_IN (should be the same as l1)`
408			`getin(l2);`
409
410			`// Make an external clock`
411			`tb_top.gpio_mon.set_gpioeclk(0);`
412			`#10;`
413			`tb_top.gpio_mon.set_gpioeclk(1);`
414			`#10;`
415
416			`// Read RGPIO_IN (should be different than l2)`
417			`getin(l3);`
418
419			`//`
420			`// Phase 3`
421			`//`
422			`// Compare phases`
423			`//`
424			`if (l1 == l2 && l2 == r1 && l3 == r2)`
425			`$write(".");`
426			`else`
427			`local_errs = local_errs + 1;`
428			`end`
429			`endtask`
430
431			`//`
432			`// Test operation of control bit RGPIO_CTRL[NEC]`
433			`//`
434			`task test_nec;`
435			`integer l1, l2;`
436			`integer r2;`
437			`begin`
438			`//`
439			`// Phase 1`
440			`//`
441			`// Compare RGPIO_IN before and after negative edge`
442			`//`
443
444			`// Clear GPIO_RGPIO_IN`
445			`tb_top.gpio_mon.set_gpioin('d0);`
446
447			`// Set GPIO to use WB clock`
448			`setctrl(0);`
449
450			`// Advance time`
451			`#1000;`
452
453			`// Set GPIO to use external clock and set RGPIO_CTRL[NEC]`
454			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK \| 1 << `GPIO_RGPIO_CTRL_NEC);
455
456			`// Put something on gpio_in pins`
457			`random_gpio(r2);`
458			`tb_top.gpio_mon.set_gpioin(r2);`
459
460			`// Wait for time to advance`
461			`#1000;`
462
463			`// Read RGPIO_IN`
464			`getin(l1);`
465
466			`// Make an external clock`
467			`tb_top.gpio_mon.set_gpioeclk(1);`
468			`#10;`
469			`tb_top.gpio_mon.set_gpioeclk(0);`
470			`#10;`
471
472			`// Read RGPIO_IN (should be different than l1)`
473			`getin(l2);`
474
475			`//`
476			`// Phase 2`
477			`//`
478			`// Compare phases`
479			`//`
480			`if (!l1 && l2 == r2)`
481			`$write(".");`
482			`else`
483			`local_errs = local_errs + 1;`
484			`end`
485			`endtask`
486
487			`//`
488			`// Test input polled mode, output mode and bidirectional`
489			`//`
490			`task test_simple;`
491			`integer l1, l2, l3, l4;`
492			`integer i, err;`
493			`begin`
494			`$write(" Testing input mode ...");`
495
496			`//`
497			`// Phase 1`
498			`//`
499			`// Compare RGPIO_IN and gpio_in`
500			`//`
501
502			`// Set GPIO to use WB clock`
503			`setctrl(0);`
504
505			`err = 0;`
506			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
507			`// Put something on gpio_in pins`
508			`random_gpio(l1);`
509			`tb_top.gpio_mon.set_gpioin(l1);`
510
511			`// Advance time`
512			`#1000;`
513
514			`// Read GPIO_RGPIO_IN`
515			`getin(l2);`
516
517			`// Compare gpio_in and RGPIO_IN. Should be equal.`
518			`if (l1 != l2)`
519			`err = err + 1;`
520			`end`
521
522			`// Phase 2`
523			`//`
524			`// Output result for previous test`
525			`//`
526			`if (!err)`
527			`$display(" OK");`
528			`else`
529			`failed;`
530
531			`$write(" Testing output mode ...");`
532
533			`//`
534			`// Phase 3`
535			`//`
536			`// Compare RGPIO_OUT and gpio_out`
537			`//`
538
539			`err = 0;`
540			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
541			`// Put something in RGPIO_OUT pins`
542			`l1 = $random;`
543			`setout(l1);`
544
545			`// Advance time`
546			`#1000;`
547
548			`// Read gpio_out`
549			`tb_top.gpio_mon.get_gpioout(l2);`
550
551			`// Compare gpio_out and RGPIO_OUT. Should be equal.`
552			`if (l1 != l2)`
553			`err = err + 1;`
554			`end`
555
556			`// Phase 4`
557			`//`
558			`// Output result for previous test`
559			`//`
560			`if (!err)`
561			`$display(" OK");`
562			`else`
563			`failed;`
564
565			`$write(" Testing bidirectional I/O ...");`
566
567			`//`
568			`// Phase 5`
569			`//`
570			`// Compare RGPIO_OE and gpio_oen`
571			`//`
572
573			`err = 0;`
574			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
575			`// Put something in RGPIO_OE pins`
576			`l1 = $random;`
577			`setoe(l1);`
578
579			`// Advance time`
580			`#1000;`
581
582			`// Read gpio_oen`
583			`tb_top.gpio_mon.get_gpiooen(l2);`
584
585			`// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.`
586			`if (l1 != ~l2)`
587			`err = err + 1;`
588			`end`
589
590			`// Phase 6`
591			`//`
592			`// Output result for previous test`
593			`//`
594			`if (!err)`
595			`$display(" OK");`
596			`else`
597			`failed;`
598
599			`$write(" Testing auxiliary feature ...");`
600
601			`//`
602			`// Phase 7`
603			`//`
604			`// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux`
605			`//`
606
607			`err = 0;`
608			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
609			`// Put something on gpio_aux pins`
610			`l1 = $random;`
611			`tb_top.gpio_mon.set_gpioaux(l1);`
612
613			`// Put something in RGPIO_AUX pins`
614			`l2 = $random;`
615			`setaux(l2);`
616
617			`// Put something in RGPIO_OUT pins`
618			`l3 = $random;`
619			`setout(l3);`
620
621			`// Advance time`
622			`#1000;`
623
624			`// Read gpio_out`
625			`tb_top.gpio_mon.get_gpioout(l4);`
626
627			`// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.`
628			`// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT`
629			`// bits are present on gpio_out and where`
630			`if ((l1 & l2 \| l3 & ~l2) != l4)`
631			`err = err + 1;`
632			`end`
633
634			`// Phase 8`
635			`//`
636			`// Output result for previous test`
637			`//`
638			`if (!err)`
639			`$display(" OK");`
640			`else`
641			`failed;`
642
643			`end`
644			`endtask`
645
646			`//`
647			`// Test interrupts`
648			`//`
649			`task test_ints;`
650			`integer l1, l2, l3;`
651			`integer i, rnd, err;`
652			`integer r1;`
653			`begin`
654
655			`$write(" Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");`
656
657			`//`
658			`// Phase 1`
659			`//`
660			`// Generate patterns on inputs in interrupt mode`
661			`//`
662
663			`// Disable spurious interrupt monitor`
664			`ints_disabled = 0;`
665
666			`err = 0;`
667			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
668
669			`// Set gpio_in pins`
670			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
671			`tb_top.gpio_mon.set_gpioin(r1);`
672
673			`// Low level triggering`
674			`setptrig(0);`
675
676			`// Enable interrupts in RGPIO_CTRL`
677			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
678
679			`// Enable interrupts in RGPIO_INTE`
680			`setinte(r1);`
681
682			`// Advance time`
683			`#100;`
684
685			`// Sample interrupt request. Should be zero.`
686	12	lampret	`l1 = tb_top.gpio_top.wb_inta_o;`
687	8	lampret
688			`// Clear gpio_in pins`
689			`tb_top.gpio_mon.set_gpioin(0);`
690
691			`// Advance time`
692			`#100;`
693
694			`// Sample interrupt request. Should be one.`
695	12	lampret	`l2 = tb_top.gpio_top.wb_inta_o;`
696	8	lampret
697			`// Clear interrupt request`
698			`setctrl(0);`
699
700			`// Advance time`
701			`#100;`
702
703			`// Sample interrupt request. Should be zero.`
704	12	lampret	`l3 = tb_top.gpio_top.wb_inta_o;`
705	8	lampret
706			`// Check for errors`
707			`if (l1 \|\| !l2 \|\| l3)`
708			`err = err +1;`
709			`end`
710
711			`// Enable spurious interrupt monitor`
712			`ints_disabled = 1;`
713
714			`// Phase 2`
715			`//`
716			`// Check results`
717			`//`
718			`if (!err)`
719			`$display(" OK");`
720			`else`
721			`failed;`
722			`end`
723			`endtask`
724
725			`//`
726			`// Test ptrig`
727			`//`
728			`task test_ptrig;`
729			`integer l1, l2, l3;`
730			`integer i, rnd, err;`
731			`integer r1;`
732			`begin`
733			`$write(" Testing ptrig features ...");`
734
735			`//`
736			`// Phase 1`
737			`//`
738			`// Generate patterns on inputs in interrupt mode`
739			`//`
740
741			`// Disable spurious interrupt monitor`
742			`ints_disabled = 0;`
743
744			`err = 0;`
745			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
746
747			`// Set bits to one`
748			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
749
750			`// Set gpio_in pins`
751			`tb_top.gpio_mon.set_gpioin('h00000000);`
752
753			`// High level triggering`
754			`setptrig('hffffffff);`
755
756			`// Enable interrupts in RGPIO_CTRL`
757			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
758
759			`// Enable interrupts in RGPIO_INTE`
760			`setinte(r1);`
761
762			`// Advance time`
763			`#100;`
764
765			`// Sample interrupt request. Should be zero.`
766	12	lampret	`l1 = tb_top.gpio_top.wb_inta_o;`
767	8	lampret
768			`// Clear gpio_in pins`
769			`tb_top.gpio_mon.set_gpioin('hffffffff);`
770
771			`// Advance time`
772			`#100;`
773
774			`// Sample interrupt request. Should be one.`
775	12	lampret	`l2 = tb_top.gpio_top.wb_inta_o;`
776	8	lampret
777			`// Clear interrupt request`
778			`setctrl(0);`
779
780			`// Advance time`
781			`#100;`
782
783			`// Sample interrupt request. Should be zero.`
784	12	lampret	`l3 = tb_top.gpio_top.wb_inta_o;`
785	8	lampret
786			`// Check for errors`
787			`if (l1 \|\| !l2 \|\| l3)`
788			`err = err +1;`
789			`end`
790
791			`// Enable spurious interrupt monitor`
792			`ints_disabled = 1;`
793
794			`// Phase 2`
795			`//`
796			`// Check results`
797			`//`
798			`if (!err)`
799			`$display(" OK");`
800			`else`
801			`failed;`
802			`end`
803			`endtask`
804
805			`//`
806			`// Do continues check for interrupts`
807			`//`
808	12	lampret	`always @(posedge tb_top.gpio_top.wb_inta_o)`
809	8	lampret	`if (ints_disabled) begin`
810			`$display("Spurious interrupt detected. ");`
811			`failed;`
812			`ints_working = 9876;`
813			`$display;`
814			`end`
815
816			`//`
817			`// Start of testbench test tasks`
818			`//`
819			`integer i;`
820			`initial begin`
821			`ifdef DUMP_VCD
822	13	lampret	`$dumpfile("../out/tb_top.vcd");`
823	8	lampret	`$dumpvars(0);`
824			`endif
825			`nr_failed = 0;`
826			`ints_disabled = 1;`
827			`ints_working = 0;`
828			`tb_top.gpio_mon.set_gpioin(0);`
829			`tb_top.gpio_mon.set_gpioaux(0);`
830			`tb_top.gpio_mon.set_gpioeclk(0);`
831			`$display;`
832			`$display("###");`
833			`$display("### GPIO IP Core Verification ###");`
834			`$display("###");`
835			`$display;`
836			`$display("I. Testing correct operation of RGPIO_CTRL control bits");`
837			`$display;`
838
839
840			`$write(" Testing control bit RGPIO_CTRL[ECLK] ...");`
841			`local_errs = 0;`
842			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
843			`test_eclk;`
844			`if (local_errs == 0)`
845			`$display(" OK");`
846			`else`
847			`failed;`
848
849
850			`$write(" Testing control bit RGPIO_CTRL[NEC] ...");`
851			`local_errs = 0;`
852			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
853			`test_nec;`
854			`if (local_errs == 0)`
855			`$display(" OK");`
856			`else`
857			`failed;`
858
859			`test_ints;`
860
861			`$display;`
862			`$display("II. Testing modes of operation ...");`
863			`$display;`
864
865			`test_simple;`
866			`test_ptrig;`
867
868			`$display;`
869			`$display("###");`
870			`$display("### FAILED TESTS: %d ###", nr_failed);`
871			`$display("###");`
872			`$display;`
873			`$finish;`
874			`end`
875
876			`endmodule`