URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  GPIO Testbench Tasks                                        ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Testbench tasks.                                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/09/18 16:37:55  lampret
// Changed VCD output location.
//
// Revision 1.2  2001/09/18 15:43:27  lampret
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:27  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:37:23  lampret
// Test bench improvements.
//
// Revision 1.1  2001/06/05 07:45:22  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.v"
`include "gpio_defines.v"
`include "tb_defines.v"
 
module tb_tasks;
 
integer nr_failed;
integer ints_disabled;
integer ints_working;
integer local_errs;
 
parameter sh_addr = `GPIO_ADDRLH+1;
 
//
// Count/report failed tests
//
task failed;
begin
        $display("FAILED !!!");
        nr_failed = nr_failed + 1;
end
endtask
 
//
// Set RGPIO_OUT register
//
task setout;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_OE register
//
task setoe;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_INTE register
//
task setinte;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_PTRIG register
//
task setptrig;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_AUX register
//
task setaux;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_CTRL register
//
task setctrl;
input   [31:0] val;
 
begin
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Display RGPIO_IN register
//
task showin;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
        $write(" RGPIO_IN: %h", tmp);
end
 
endtask
 
//
// Display RGPIO_OUT register
//
task showout;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
        $write(" RGPIO_OUT: %h", tmp);
end
 
endtask
 
 
//
// Display RGPIO_OE register
//
task showoe;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
        $write(" RGPIO_OE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_INTE register
//
task showinte;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
        $write(" RGPIO_INTE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_PTRIG register
//
task showptrig;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
        $write(" RGPIO_PTRIG:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_AUX register
//
task showaux;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
        $write(" RGPIO_AUX:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_CTRL register
//
task showctrl;
 
reg     [31:0] tmp;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
        $write(" RGPIO_CTRL: %h", tmp);
end
 
endtask
 
//
// Compare parameter with RGPIO_IN register
//
task comp_in;
input   [31:0]   val;
output          ret;
 
reg     [31:0]   tmp;
reg             ret;
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
 
        if (tmp == val)
                ret = 1;
        else
                ret = 0;
end
 
endtask
 
//
// Get RGPIO_IN register
//
task getin;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OUT register
//
task getout;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_OE register
//
task getoe;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_INTE register
//
task getinte;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_PTRIG register
//
task getptrig;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_AUX register
//
task getaux;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
end
 
endtask
 
//
// Get RGPIO_CTRL register
//
task getctrl;
output  [31:0]   tmp;
 
begin
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
end
 
endtask
 
//
// Calculate a random and make it narrow to fit on GPIO I/O pins
//
task random_gpio;
output  [31:0]   tmp;
 
begin
        tmp = $random & ((1<<`GPIO_IOS)-1);
end
 
endtask
 
//
// Test operation of control bit RGPIO_CTRL[ECLK]
//
task test_eclk;
integer         l1, l2, l3;
integer         r1, r2, r3;
begin
 
        // Set external clock to low state
        tb_top.gpio_mon.set_gpioeclk(0);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        //
        // Phase 1
        //
        // GPIO uses WISHBONE clock to latch gpio_in
        //
 
        // Put something on gpio_in pins
        random_gpio(r1);
        tb_top.gpio_mon.set_gpioin(r1);
 
        // Reset GPIO_CTRL
        setctrl(0);
 
        // Wait for time to advance
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Read GPIO_RGPIO_IN
        getin(l1);
 
        //
        // Phase 2
        //
        // GPIO uses external clock to latch gpio_in
        //
 
        // Set GPIO to use external clock, NEC bit cleared
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
 
        // Put something else on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Make an external posedge clock pulse
        tb_top.gpio_mon.set_gpioeclk(0);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
        tb_top.gpio_mon.set_gpioeclk(1);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Read RGPIO_IN
        getin(l2);
 
        //
        // Phase 3
        //
        // Change GPIO inputs and WB clock but not external clock.
        // RGPIO_IN should not change.
        //
 
        // Put something else on gpio_in pins
        random_gpio(r3);
        tb_top.gpio_mon.set_gpioin(r3);
 
        // Wait for WB clock
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Read RGPIO_IN
        getin(l3);
 
        //
        // Phase 4
        //
        // Compare phases
        //
        if (l1 == r1 && l2 == r2 && l2 == l3)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test operation of control bit RGPIO_CTRL[NEC]
//
task test_nec;
integer         l1, l2;
integer         r1, r2;
begin
        //
        // Phase 1
        //
        // Compare RGPIO_IN before and after negative edge
        //
 
        // Set external clock to low state
        tb_top.gpio_mon.set_gpioeclk(0);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Set GPIO to use external clock and set RGPIO_CTRL[NEC]
        setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
 
        // Put random on gpio inputs
        random_gpio(r1);
        tb_top.gpio_mon.set_gpioin(r1);
 
        // Advance time by making an external negedge clock pulse
        tb_top.gpio_mon.set_gpioeclk(1);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
        tb_top.gpio_mon.set_gpioeclk(0);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Put something on gpio_in pins
        random_gpio(r2);
        tb_top.gpio_mon.set_gpioin(r2);
 
        // Make an external posedge clock pulse
        tb_top.gpio_mon.set_gpioeclk(0);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
        tb_top.gpio_mon.set_gpioeclk(1);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Read RGPIO_IN (should be the same as r1)
        getin(l1);
 
        // Make an external negedge clock pulse
        tb_top.gpio_mon.set_gpioeclk(1);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
        tb_top.gpio_mon.set_gpioeclk(0);
        @(posedge tb_top.clk);
        @(posedge tb_top.clk);
 
        // Read RGPIO_IN (should be the same as r2)
        getin(l2);
 
        //
        // Phase 2
        //
        // Compare phases
        //
//      $display("l1 %h  l2 %h  r1 %h  r2 %h", l1, l2, r1, r2);
        if (l1 == r1 && l2 == r2)
                $write(".");
        else
                local_errs = local_errs + 1;
end
endtask
 
//
// Test input polled mode, output mode and bidirectional
//
task test_simple;
integer         l1, l2, l3, l4;
integer         i, err;
begin
        $write("  Testing input mode ...");
 
        //
        // Phase 1
        //
        // Compare RGPIO_IN and gpio_in
        //
 
        // Set GPIO to use WB clock
        setctrl(0);
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_in pins
                random_gpio(l1);
                tb_top.gpio_mon.set_gpioin(l1);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Read GPIO_RGPIO_IN
                getin(l2);
 
                // Compare gpio_in and RGPIO_IN. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 2
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing output mode ...");
 
        //
        // Phase 3
        //
        // Compare RGPIO_OUT and gpio_out
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OUT pins
                l1 = $random;
                setout(l1);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l2);
 
                // Compare gpio_out and RGPIO_OUT. Should be equal.
                if (l1 != l2)
                        err = err + 1;
        end
 
        // Phase 4
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing bidirectional I/O ...");
 
        //
        // Phase 5
        //
        // Compare RGPIO_OE and gpio_oen
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something in RGPIO_OE pins
                l1 = $random;
                setoe(l1);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Read gpio_oen
                tb_top.gpio_mon.get_gpiooen(l2);
 
                // Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
                if (l1 != ~l2)
                        err = err + 1;
        end
 
        // Phase 6
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
        $write("  Testing auxiliary feature ...");
 
        //
        // Phase 7
        //
        // Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
        //
 
        err = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
                // Put something on gpio_aux pins
                l1 = $random;
                tb_top.gpio_mon.set_gpioaux(l1);
 
                // Put something in RGPIO_AUX pins
                l2 = $random;
                setaux(l2);
 
                // Put something in RGPIO_OUT pins
                l3 = $random;
                setout(l3);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Read gpio_out
                tb_top.gpio_mon.get_gpioout(l4);
 
                // Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
                // RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT 
                // bits are present on gpio_out and where
                if ((l1 & l2 | l3 & ~l2) != l4)
                        err = err + 1;
        end
 
        // Phase 8
        //
        // Output result for previous test
        //
        if (!err)
                $display(" OK");
        else
                failed;
 
end
endtask
 
//
// Test interrupts
//
task test_ints;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
 
        $write("  Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set gpio_in pins
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
                tb_top.gpio_mon.set_gpioin(r1);
 
                // Low level triggering
                setptrig(0);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio_top.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin(0);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio_top.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio_top.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Test ptrig
//
task test_ptrig;
integer         l1, l2, l3;
integer         i, rnd, err;
integer         r1;
begin
        $write("  Testing ptrig features ...");
 
        //
        // Phase 1
        //
        // Generate patterns on inputs in interrupt mode
        //
 
        // Disable spurious interrupt monitor
        ints_disabled = 0;
 
        err = 0;
        for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
 
                // Set bits to one
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
                // Set gpio_in pins
                tb_top.gpio_mon.set_gpioin('h00000000);
 
                // High level triggering
                setptrig('hffffffff);
 
                // Enable interrupts in RGPIO_CTRL
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                // Enable interrupts in RGPIO_INTE
                setinte(r1);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Sample interrupt request. Should be zero.
                l1 = tb_top.gpio_top.wb_inta_o;
 
                // Clear gpio_in pins
                tb_top.gpio_mon.set_gpioin('hffffffff);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Sample interrupt request. Should be one.
                l2 = tb_top.gpio_top.wb_inta_o;
 
                // Clear interrupt request
                setctrl(0);
 
                // Advance time
                @(posedge tb_top.clk);
                @(posedge tb_top.clk);
 
                // Sample interrupt request. Should be zero.
                l3 = tb_top.gpio_top.wb_inta_o;
 
                // Check for errors
                if (l1 || !l2 || l3)
                        err = err +1;
        end
 
        // Enable spurious interrupt monitor
        ints_disabled = 1;
 
        // Phase 2
        //
        // Check results
        //
        if (!err)
                $display(" OK");
        else
                failed;
end
endtask
 
//
// Do continues check for interrupts
//
always @(posedge tb_top.gpio_top.wb_inta_o)
        if (ints_disabled) begin
                $display("Spurious interrupt detected. ");
                failed;
                ints_working = 9876;
                $display;
        end
 
//
// Start of testbench test tasks
//
integer         i;
initial begin
`ifdef DUMP_VCD
        $dumpfile("../out/tb_top.vcd");
        $dumpvars(0);
`endif
        nr_failed = 0;
        ints_disabled = 1;
        ints_working = 0;
        tb_top.gpio_mon.set_gpioin(0);
        tb_top.gpio_mon.set_gpioaux(0);
        tb_top.gpio_mon.set_gpioeclk(0);
        $display;
        $display("###");
        $display("### GPIO IP Core Verification ###");
        $display("###");
        $display;
        $display("I. Testing correct operation of RGPIO_CTRL control bits");
        $display;
 
 
        $write("  Testing control bit RGPIO_CTRL[ECLK] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_eclk;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
 
        $write("  Testing control bit RGPIO_CTRL[NEC] ...");
        local_errs = 0;
        for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
                test_nec;
        if (local_errs == 0)
                $display(" OK");
        else
                failed;
 
        test_ints;
 
        $display;
        $display("II. Testing modes of operation ...");
        $display;
 
        test_simple;
        test_ptrig;
 
        $display;
        $display("###");
        $display("### FAILED TESTS: %d ###", nr_failed);
        $display("###");
        $display;
        $finish;
end
 
endmodule

Browse

Tools

Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Blame information for rev 18

Line No.	Rev	Author	Line
1	8	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// GPIO Testbench Tasks ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Testbench tasks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	18	lampret	`// Revision 1.3 2001/09/18 16:37:55 lampret`
48			`// Changed VCD output location.`
49			`//`
50	13	lampret	`// Revision 1.2 2001/09/18 15:43:27 lampret`
51			`// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.`
52			`//`
53	12	lampret	`// Revision 1.1 2001/08/21 21:39:27 lampret`
54			`// Changed directory structure, port names and drfines.`
55			`//`
56	8	lampret	`// Revision 1.2 2001/07/14 20:37:23 lampret`
57			`// Test bench improvements.`
58			`//`
59			`// Revision 1.1 2001/06/05 07:45:22 lampret`
60			`// Added initial RTL and test benches. There are still some issues with these files.`
61			`//`
62			`//`
63
64			`include "timescale.v"
65	12	lampret	`include "gpio_defines.v"
66	8	lampret	`include "tb_defines.v"
67
68			`module tb_tasks;`
69
70			`integer nr_failed;`
71			`integer ints_disabled;`
72			`integer ints_working;`
73			`integer local_errs;`
74
75			parameter sh_addr = `GPIO_ADDRLH+1;
76
77			`//`
78			`// Count/report failed tests`
79			`//`
80			`task failed;`
81			`begin`
82			`$display("FAILED !!!");`
83			`nr_failed = nr_failed + 1;`
84			`end`
85			`endtask`
86
87			`//`
88			`// Set RGPIO_OUT register`
89			`//`
90			`task setout;`
91			`input [31:0] val;`
92
93			`begin`
94			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
95			`end`
96
97			`endtask`
98
99			`//`
100			`// Set RGPIO_OE register`
101			`//`
102			`task setoe;`
103			`input [31:0] val;`
104
105			`begin`
106			#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
107			`end`
108
109			`endtask`
110
111			`//`
112			`// Set RGPIO_INTE register`
113			`//`
114			`task setinte;`
115			`input [31:0] val;`
116
117			`begin`
118			#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
119			`end`
120
121			`endtask`
122
123			`//`
124			`// Set RGPIO_PTRIG register`
125			`//`
126			`task setptrig;`
127			`input [31:0] val;`
128
129			`begin`
130			#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
131			`end`
132
133			`endtask`
134
135			`//`
136			`// Set RGPIO_AUX register`
137			`//`
138			`task setaux;`
139			`input [31:0] val;`
140
141			`begin`
142			#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
143			`end`
144
145			`endtask`
146
147			`//`
148			`// Set RGPIO_CTRL register`
149			`//`
150			`task setctrl;`
151			`input [31:0] val;`
152
153			`begin`
154			#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
155			`end`
156
157			`endtask`
158
159			`//`
160			`// Display RGPIO_IN register`
161			`//`
162			`task showin;`
163
164			`reg [31:0] tmp;`
165			`begin`
166			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
167			`$write(" RGPIO_IN: %h", tmp);`
168			`end`
169
170			`endtask`
171
172			`//`
173			`// Display RGPIO_OUT register`
174			`//`
175			`task showout;`
176
177			`reg [31:0] tmp;`
178			`begin`
179			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
180			`$write(" RGPIO_OUT: %h", tmp);`
181			`end`
182
183			`endtask`
184
185
186			`//`
187			`// Display RGPIO_OE register`
188			`//`
189			`task showoe;`
190
191			`reg [31:0] tmp;`
192			`begin`
193			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
194			`$write(" RGPIO_OE:%h", tmp);`
195			`end`
196
197			`endtask`
198
199			`//`
200			`// Display RGPIO_INTE register`
201			`//`
202			`task showinte;`
203
204			`reg [31:0] tmp;`
205			`begin`
206			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
207			`$write(" RGPIO_INTE:%h", tmp);`
208			`end`
209
210			`endtask`
211
212			`//`
213			`// Display RGPIO_PTRIG register`
214			`//`
215			`task showptrig;`
216
217			`reg [31:0] tmp;`
218			`begin`
219			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
220			`$write(" RGPIO_PTRIG:%h", tmp);`
221			`end`
222
223			`endtask`
224
225			`//`
226			`// Display RGPIO_AUX register`
227			`//`
228			`task showaux;`
229
230			`reg [31:0] tmp;`
231			`begin`
232			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
233			`$write(" RGPIO_AUX:%h", tmp);`
234			`end`
235
236			`endtask`
237
238			`//`
239			`// Display RGPIO_CTRL register`
240			`//`
241			`task showctrl;`
242
243			`reg [31:0] tmp;`
244			`begin`
245			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
246			`$write(" RGPIO_CTRL: %h", tmp);`
247			`end`
248
249			`endtask`
250
251			`//`
252			`// Compare parameter with RGPIO_IN register`
253			`//`
254			`task comp_in;`
255			`input [31:0] val;`
256			`output ret;`
257
258			`reg [31:0] tmp;`
259			`reg ret;`
260			`begin`
261			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
262
263			`if (tmp == val)`
264			`ret = 1;`
265			`else`
266			`ret = 0;`
267			`end`
268
269			`endtask`
270
271			`//`
272			`// Get RGPIO_IN register`
273			`//`
274			`task getin;`
275			`output [31:0] tmp;`
276
277			`begin`
278			#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
279			`end`
280
281			`endtask`
282
283			`//`
284			`// Get RGPIO_OUT register`
285			`//`
286			`task getout;`
287			`output [31:0] tmp;`
288
289			`begin`
290			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
291			`end`
292
293			`endtask`
294
295			`//`
296			`// Get RGPIO_OE register`
297			`//`
298			`task getoe;`
299			`output [31:0] tmp;`
300
301			`begin`
302			#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
303			`end`
304
305			`endtask`
306
307			`//`
308			`// Get RGPIO_INTE register`
309			`//`
310			`task getinte;`
311			`output [31:0] tmp;`
312
313			`begin`
314			#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
315			`end`
316
317			`endtask`
318
319			`//`
320			`// Get RGPIO_PTRIG register`
321			`//`
322			`task getptrig;`
323			`output [31:0] tmp;`
324
325			`begin`
326			#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
327			`end`
328
329			`endtask`
330
331			`//`
332			`// Get RGPIO_AUX register`
333			`//`
334			`task getaux;`
335			`output [31:0] tmp;`
336
337			`begin`
338			#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
339			`end`
340
341			`endtask`
342
343			`//`
344			`// Get RGPIO_CTRL register`
345			`//`
346			`task getctrl;`
347			`output [31:0] tmp;`
348
349			`begin`
350			#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
351			`end`
352
353			`endtask`
354
355			`//`
356			`// Calculate a random and make it narrow to fit on GPIO I/O pins`
357			`//`
358			`task random_gpio;`
359			`output [31:0] tmp;`
360
361			`begin`
362			tmp = $random & ((1<<`GPIO_IOS)-1);
363			`end`
364
365			`endtask`
366
367			`//`
368			`// Test operation of control bit RGPIO_CTRL[ECLK]`
369			`//`
370			`task test_eclk;`
371			`integer l1, l2, l3;`
372	18	lampret	`integer r1, r2, r3;`
373	8	lampret	`begin`
374
375	18	lampret	`// Set external clock to low state`
376			`tb_top.gpio_mon.set_gpioeclk(0);`
377			`@(posedge tb_top.clk);`
378			`@(posedge tb_top.clk);`
379
380	8	lampret	`//`
381			`// Phase 1`
382			`//`
383			`// GPIO uses WISHBONE clock to latch gpio_in`
384			`//`
385
386			`// Put something on gpio_in pins`
387			`random_gpio(r1);`
388			`tb_top.gpio_mon.set_gpioin(r1);`
389
390			`// Reset GPIO_CTRL`
391			`setctrl(0);`
392
393			`// Wait for time to advance`
394	18	lampret	`@(posedge tb_top.clk);`
395			`@(posedge tb_top.clk);`
396	8	lampret
397			`// Read GPIO_RGPIO_IN`
398			`getin(l1);`
399
400			`//`
401			`// Phase 2`
402			`//`
403			`// GPIO uses external clock to latch gpio_in`
404			`//`
405
406	18	lampret	`// Set GPIO to use external clock, NEC bit cleared`
407	8	lampret	setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
408
409			`// Put something else on gpio_in pins`
410			`random_gpio(r2);`
411			`tb_top.gpio_mon.set_gpioin(r2);`
412
413	18	lampret	`// Make an external posedge clock pulse`
414			`tb_top.gpio_mon.set_gpioeclk(0);`
415			`@(posedge tb_top.clk);`
416			`@(posedge tb_top.clk);`
417			`tb_top.gpio_mon.set_gpioeclk(1);`
418			`@(posedge tb_top.clk);`
419			`@(posedge tb_top.clk);`
420	8	lampret
421	18	lampret	`// Read RGPIO_IN`
422	8	lampret	`getin(l2);`
423
424	18	lampret	`//`
425			`// Phase 3`
426			`//`
427			`// Change GPIO inputs and WB clock but not external clock.`
428			`// RGPIO_IN should not change.`
429			`//`
430	8	lampret
431	18	lampret	`// Put something else on gpio_in pins`
432			`random_gpio(r3);`
433			`tb_top.gpio_mon.set_gpioin(r3);`
434
435			`// Wait for WB clock`
436			`@(posedge tb_top.clk);`
437			`@(posedge tb_top.clk);`
438
439			`// Read RGPIO_IN`
440	8	lampret	`getin(l3);`
441
442			`//`
443	18	lampret	`// Phase 4`
444	8	lampret	`//`
445			`// Compare phases`
446			`//`
447	18	lampret	`if (l1 == r1 && l2 == r2 && l2 == l3)`
448	8	lampret	`$write(".");`
449			`else`
450			`local_errs = local_errs + 1;`
451			`end`
452			`endtask`
453
454			`//`
455			`// Test operation of control bit RGPIO_CTRL[NEC]`
456			`//`
457			`task test_nec;`
458			`integer l1, l2;`
459	18	lampret	`integer r1, r2;`
460	8	lampret	`begin`
461			`//`
462			`// Phase 1`
463			`//`
464			`// Compare RGPIO_IN before and after negative edge`
465			`//`
466
467	18	lampret	`// Set external clock to low state`
468			`tb_top.gpio_mon.set_gpioeclk(0);`
469			`@(posedge tb_top.clk);`
470			`@(posedge tb_top.clk);`
471	8	lampret
472			`// Set GPIO to use external clock and set RGPIO_CTRL[NEC]`
473			setctrl(1 << `GPIO_RGPIO_CTRL_ECLK \| 1 << `GPIO_RGPIO_CTRL_NEC);
474
475	18	lampret	`// Put random on gpio inputs`
476			`random_gpio(r1);`
477			`tb_top.gpio_mon.set_gpioin(r1);`
478
479			`// Advance time by making an external negedge clock pulse`
480			`tb_top.gpio_mon.set_gpioeclk(1);`
481			`@(posedge tb_top.clk);`
482			`@(posedge tb_top.clk);`
483			`tb_top.gpio_mon.set_gpioeclk(0);`
484			`@(posedge tb_top.clk);`
485			`@(posedge tb_top.clk);`
486
487	8	lampret	`// Put something on gpio_in pins`
488			`random_gpio(r2);`
489			`tb_top.gpio_mon.set_gpioin(r2);`
490
491	18	lampret	`// Make an external posedge clock pulse`
492			`tb_top.gpio_mon.set_gpioeclk(0);`
493			`@(posedge tb_top.clk);`
494			`@(posedge tb_top.clk);`
495			`tb_top.gpio_mon.set_gpioeclk(1);`
496			`@(posedge tb_top.clk);`
497			`@(posedge tb_top.clk);`
498	8	lampret
499	18	lampret	`// Read RGPIO_IN (should be the same as r1)`
500	8	lampret	`getin(l1);`
501
502	18	lampret	`// Make an external negedge clock pulse`
503	8	lampret	`tb_top.gpio_mon.set_gpioeclk(1);`
504	18	lampret	`@(posedge tb_top.clk);`
505			`@(posedge tb_top.clk);`
506	8	lampret	`tb_top.gpio_mon.set_gpioeclk(0);`
507	18	lampret	`@(posedge tb_top.clk);`
508			`@(posedge tb_top.clk);`
509	8	lampret
510	18	lampret	`// Read RGPIO_IN (should be the same as r2)`
511	8	lampret	`getin(l2);`
512
513			`//`
514			`// Phase 2`
515			`//`
516			`// Compare phases`
517			`//`
518	18	lampret	`// $display("l1 %h l2 %h r1 %h r2 %h", l1, l2, r1, r2);`
519			`if (l1 == r1 && l2 == r2)`
520	8	lampret	`$write(".");`
521			`else`
522			`local_errs = local_errs + 1;`
523			`end`
524			`endtask`
525
526			`//`
527			`// Test input polled mode, output mode and bidirectional`
528			`//`
529			`task test_simple;`
530			`integer l1, l2, l3, l4;`
531			`integer i, err;`
532			`begin`
533			`$write(" Testing input mode ...");`
534
535			`//`
536			`// Phase 1`
537			`//`
538			`// Compare RGPIO_IN and gpio_in`
539			`//`
540
541			`// Set GPIO to use WB clock`
542			`setctrl(0);`
543
544			`err = 0;`
545			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
546			`// Put something on gpio_in pins`
547			`random_gpio(l1);`
548			`tb_top.gpio_mon.set_gpioin(l1);`
549
550			`// Advance time`
551	18	lampret	`@(posedge tb_top.clk);`
552			`@(posedge tb_top.clk);`
553	8	lampret
554			`// Read GPIO_RGPIO_IN`
555			`getin(l2);`
556
557			`// Compare gpio_in and RGPIO_IN. Should be equal.`
558			`if (l1 != l2)`
559			`err = err + 1;`
560			`end`
561
562			`// Phase 2`
563			`//`
564			`// Output result for previous test`
565			`//`
566			`if (!err)`
567			`$display(" OK");`
568			`else`
569			`failed;`
570
571			`$write(" Testing output mode ...");`
572
573			`//`
574			`// Phase 3`
575			`//`
576			`// Compare RGPIO_OUT and gpio_out`
577			`//`
578
579			`err = 0;`
580			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
581			`// Put something in RGPIO_OUT pins`
582			`l1 = $random;`
583			`setout(l1);`
584
585			`// Advance time`
586	18	lampret	`@(posedge tb_top.clk);`
587			`@(posedge tb_top.clk);`
588	8	lampret
589			`// Read gpio_out`
590			`tb_top.gpio_mon.get_gpioout(l2);`
591
592			`// Compare gpio_out and RGPIO_OUT. Should be equal.`
593			`if (l1 != l2)`
594			`err = err + 1;`
595			`end`
596
597			`// Phase 4`
598			`//`
599			`// Output result for previous test`
600			`//`
601			`if (!err)`
602			`$display(" OK");`
603			`else`
604			`failed;`
605
606			`$write(" Testing bidirectional I/O ...");`
607
608			`//`
609			`// Phase 5`
610			`//`
611			`// Compare RGPIO_OE and gpio_oen`
612			`//`
613
614			`err = 0;`
615			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
616			`// Put something in RGPIO_OE pins`
617			`l1 = $random;`
618			`setoe(l1);`
619
620			`// Advance time`
621	18	lampret	`@(posedge tb_top.clk);`
622			`@(posedge tb_top.clk);`
623	8	lampret
624			`// Read gpio_oen`
625			`tb_top.gpio_mon.get_gpiooen(l2);`
626
627			`// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.`
628			`if (l1 != ~l2)`
629			`err = err + 1;`
630			`end`
631
632			`// Phase 6`
633			`//`
634			`// Output result for previous test`
635			`//`
636			`if (!err)`
637			`$display(" OK");`
638			`else`
639			`failed;`
640
641			`$write(" Testing auxiliary feature ...");`
642
643			`//`
644			`// Phase 7`
645			`//`
646			`// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux`
647			`//`
648
649			`err = 0;`
650			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
651			`// Put something on gpio_aux pins`
652			`l1 = $random;`
653			`tb_top.gpio_mon.set_gpioaux(l1);`
654
655			`// Put something in RGPIO_AUX pins`
656			`l2 = $random;`
657			`setaux(l2);`
658
659			`// Put something in RGPIO_OUT pins`
660			`l3 = $random;`
661			`setout(l3);`
662
663			`// Advance time`
664	18	lampret	`@(posedge tb_top.clk);`
665			`@(posedge tb_top.clk);`
666	8	lampret
667			`// Read gpio_out`
668			`tb_top.gpio_mon.get_gpioout(l4);`
669
670			`// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.`
671			`// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT`
672			`// bits are present on gpio_out and where`
673			`if ((l1 & l2 \| l3 & ~l2) != l4)`
674			`err = err + 1;`
675			`end`
676
677			`// Phase 8`
678			`//`
679			`// Output result for previous test`
680			`//`
681			`if (!err)`
682			`$display(" OK");`
683			`else`
684			`failed;`
685
686			`end`
687			`endtask`
688
689			`//`
690			`// Test interrupts`
691			`//`
692			`task test_ints;`
693			`integer l1, l2, l3;`
694			`integer i, rnd, err;`
695			`integer r1;`
696			`begin`
697
698	18	lampret	`$write(" Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");`
699	8	lampret
700			`//`
701			`// Phase 1`
702			`//`
703			`// Generate patterns on inputs in interrupt mode`
704			`//`
705
706			`// Disable spurious interrupt monitor`
707			`ints_disabled = 0;`
708
709			`err = 0;`
710			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
711
712			`// Set gpio_in pins`
713			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
714			`tb_top.gpio_mon.set_gpioin(r1);`
715
716			`// Low level triggering`
717			`setptrig(0);`
718
719			`// Enable interrupts in RGPIO_CTRL`
720			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
721
722			`// Enable interrupts in RGPIO_INTE`
723			`setinte(r1);`
724
725			`// Advance time`
726	18	lampret	`@(posedge tb_top.clk);`
727			`@(posedge tb_top.clk);`
728	8	lampret
729			`// Sample interrupt request. Should be zero.`
730	12	lampret	`l1 = tb_top.gpio_top.wb_inta_o;`
731	8	lampret
732			`// Clear gpio_in pins`
733			`tb_top.gpio_mon.set_gpioin(0);`
734
735			`// Advance time`
736	18	lampret	`@(posedge tb_top.clk);`
737			`@(posedge tb_top.clk);`
738	8	lampret
739			`// Sample interrupt request. Should be one.`
740	12	lampret	`l2 = tb_top.gpio_top.wb_inta_o;`
741	8	lampret
742			`// Clear interrupt request`
743			`setctrl(0);`
744
745			`// Advance time`
746	18	lampret	`@(posedge tb_top.clk);`
747			`@(posedge tb_top.clk);`
748	8	lampret
749			`// Sample interrupt request. Should be zero.`
750	12	lampret	`l3 = tb_top.gpio_top.wb_inta_o;`
751	8	lampret
752			`// Check for errors`
753			`if (l1 \|\| !l2 \|\| l3)`
754			`err = err +1;`
755			`end`
756
757			`// Enable spurious interrupt monitor`
758			`ints_disabled = 1;`
759
760			`// Phase 2`
761			`//`
762			`// Check results`
763			`//`
764			`if (!err)`
765			`$display(" OK");`
766			`else`
767			`failed;`
768			`end`
769			`endtask`
770
771			`//`
772			`// Test ptrig`
773			`//`
774			`task test_ptrig;`
775			`integer l1, l2, l3;`
776			`integer i, rnd, err;`
777			`integer r1;`
778			`begin`
779			`$write(" Testing ptrig features ...");`
780
781			`//`
782			`// Phase 1`
783			`//`
784			`// Generate patterns on inputs in interrupt mode`
785			`//`
786
787			`// Disable spurious interrupt monitor`
788			`ints_disabled = 0;`
789
790			`err = 0;`
791			for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
792
793			`// Set bits to one`
794			r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
795
796			`// Set gpio_in pins`
797			`tb_top.gpio_mon.set_gpioin('h00000000);`
798
799			`// High level triggering`
800			`setptrig('hffffffff);`
801
802			`// Enable interrupts in RGPIO_CTRL`
803			setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
804
805			`// Enable interrupts in RGPIO_INTE`
806			`setinte(r1);`
807
808			`// Advance time`
809	18	lampret	`@(posedge tb_top.clk);`
810			`@(posedge tb_top.clk);`
811	8	lampret
812			`// Sample interrupt request. Should be zero.`
813	12	lampret	`l1 = tb_top.gpio_top.wb_inta_o;`
814	8	lampret
815			`// Clear gpio_in pins`
816			`tb_top.gpio_mon.set_gpioin('hffffffff);`
817
818			`// Advance time`
819	18	lampret	`@(posedge tb_top.clk);`
820			`@(posedge tb_top.clk);`
821	8	lampret
822			`// Sample interrupt request. Should be one.`
823	12	lampret	`l2 = tb_top.gpio_top.wb_inta_o;`
824	8	lampret
825			`// Clear interrupt request`
826			`setctrl(0);`
827
828			`// Advance time`
829	18	lampret	`@(posedge tb_top.clk);`
830			`@(posedge tb_top.clk);`
831	8	lampret
832			`// Sample interrupt request. Should be zero.`
833	12	lampret	`l3 = tb_top.gpio_top.wb_inta_o;`
834	8	lampret
835			`// Check for errors`
836			`if (l1 \|\| !l2 \|\| l3)`
837			`err = err +1;`
838			`end`
839
840			`// Enable spurious interrupt monitor`
841			`ints_disabled = 1;`
842
843			`// Phase 2`
844			`//`
845			`// Check results`
846			`//`
847			`if (!err)`
848			`$display(" OK");`
849			`else`
850			`failed;`
851			`end`
852			`endtask`
853
854			`//`
855			`// Do continues check for interrupts`
856			`//`
857	12	lampret	`always @(posedge tb_top.gpio_top.wb_inta_o)`
858	8	lampret	`if (ints_disabled) begin`
859			`$display("Spurious interrupt detected. ");`
860			`failed;`
861			`ints_working = 9876;`
862			`$display;`
863			`end`
864
865			`//`
866			`// Start of testbench test tasks`
867			`//`
868			`integer i;`
869			`initial begin`
870			`ifdef DUMP_VCD
871	13	lampret	`$dumpfile("../out/tb_top.vcd");`
872	8	lampret	`$dumpvars(0);`
873			`endif
874			`nr_failed = 0;`
875			`ints_disabled = 1;`
876			`ints_working = 0;`
877			`tb_top.gpio_mon.set_gpioin(0);`
878			`tb_top.gpio_mon.set_gpioaux(0);`
879			`tb_top.gpio_mon.set_gpioeclk(0);`
880			`$display;`
881			`$display("###");`
882			`$display("### GPIO IP Core Verification ###");`
883			`$display("###");`
884			`$display;`
885			`$display("I. Testing correct operation of RGPIO_CTRL control bits");`
886			`$display;`
887
888
889			`$write(" Testing control bit RGPIO_CTRL[ECLK] ...");`
890			`local_errs = 0;`
891			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
892			`test_eclk;`
893			`if (local_errs == 0)`
894			`$display(" OK");`
895			`else`
896			`failed;`
897
898
899			`$write(" Testing control bit RGPIO_CTRL[NEC] ...");`
900			`local_errs = 0;`
901			for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
902			`test_nec;`
903			`if (local_errs == 0)`
904			`$display(" OK");`
905			`else`
906			`failed;`
907
908			`test_ints;`
909
910			`$display;`
911			`$display("II. Testing modes of operation ...");`
912			`$display;`
913
914			`test_simple;`
915			`test_ptrig;`
916
917			`$display;`
918			`$display("###");`
919			`$display("### FAILED TESTS: %d ###", nr_failed);`
920			`$display("###");`
921			`$display;`
922			`$finish;`
923			`end`
924
925			`endmodule`