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[/] [gpio/] [trunk/] [rtl/] [verilog/] [gpio_defines.v] - Blame information for rev 17

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE GPIO Definitions                                   ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  GPIO IP Definitions.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.3  2001/07/15 00:21:10  lampret
// Registers can be omitted and will have certain default values
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
//
// Number of GPIO I/O signals
//
// This is the most important parameter of the GPIO IP core. It defines how many
// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are
// required, use several instances of GPIO IP core.
//
// Default is 16.
//
`define GPIO_IOS 16
 
//
// Undefine this one if you don't want to remove GPIO block from your design
// but you also don't need it. When it is undefined, all GPIO ports still
// remain valid and the core can be synthesized however internally there is
// no GPIO funationality.
//
// Defined by default (duhh !).
//
`define GPIO_IMPLEMENTED
 
//
// Define to register all WISHBONE outputs.
//
// Register outputs if you are using GPIO core as a block and synthesizing
// and place&routing it separately from the rest of the system.
//
// If you do not need registered outputs, you can save some area by not defining
// this macro. By default it is defined.
//
`define GPIO_REGISTERED_WB_OUTPUTS
 
//
// Define to register all GPIO pad outputs.
//
// Register outputs if you are using GPIO core as a block and synthesizing
// and place&routing it separately from the rest of the system.
//
// If you do not need registered outputs, you can save some area by not defining
// this macro. By default it is defined.
//
`define GPIO_REGISTERED_IO_OUTPUTS
 
//
// Define to avoid using negative edge clock flip-flops for external clock
// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with
// positive edge clock flip-flops will be used.
//
// By default it is defined.
//
`define GPIO_NO_NEGEDGE_FLOPS
 
// 
// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
// is usually useful if you want really small area (for example when implemented in
// FPGA).
//
// To follow GPIO IP core specification document this one must be defined. Also to
// successfully run the test bench it must be defined. By default it is defined.
//
`define GPIO_READREGS
 
//
// Full WISHBONE address decoding
//
// It is is undefined, partial WISHBONE address decoding is performed.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define GPIO_FULL_DECODE
 
//
// Strict 32-bit WISHBONE access
//
// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
// not defined, err_o is asserted whenever 8- or 16-bit access is made.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define GPIO_STRICT_32BIT_ACCESS
 
//
// WISHBONE address bits used for full decoding of GPIO registers.
//
`define GPIO_ADDRHH 6
`define GPIO_ADDRHL 5
`define GPIO_ADDRLH 1
`define GPIO_ADDRLL 0
 
//
// Bits of WISHBONE address used for partial decoding of GPIO registers.
//
// Default 4:2.
//
`define GPIO_OFS_BITS   `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
 
//
// Addresses of GPIO registers
//
// To comply with GPIO IP core specification document they must go from
// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,
// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL
//
// If particular register is not needed, it's address definition can be omitted
// and the register will not be implemented. Instead a fixed default value will
// be used.
//
`define GPIO_RGPIO_IN           3'h0    // Address 0x00
`define GPIO_RGPIO_OUT          3'h1    // Address 0x04
`define GPIO_RGPIO_OE           3'h2    // Address 0x08
`define GPIO_RGPIO_INTE         3'h3    // Address 0x0c
`define GPIO_RGPIO_PTRIG        3'h4    // Address 0x10
`define GPIO_RGPIO_AUX          3'h5    // Address 0x14
`define GPIO_RGPIO_CTRL         3'h6    // Address 0x18
 
//
// Default values for unimplemented GPIO registers
//
`define GPIO_DEF_RGPIO_IN       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_OUT      `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_OE       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_INTE     `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_PTRIG    `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_AUX      `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_CTRL     `GPIO_IOS'h0
 
//
// RGPIO_CTRL bits
//
// To comply with the GPIO IP core specification document they must go from
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
//
`define GPIO_RGPIO_CTRL_ECLK            0
`define GPIO_RGPIO_CTRL_NEC             1
`define GPIO_RGPIO_CTRL_INTE            2
`define GPIO_RGPIO_CTRL_INT             3

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE GPIO Definitions ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// GPIO IP Definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	17	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
48			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
49			`//`
50	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
51			`// Changed directory structure, port names and drfines.`
52			`//`
53			`// Revision 1.3 2001/07/15 00:21:10 lampret`
54			`// Registers can be omitted and will have certain default values`
55			`//`
56			`// Revision 1.2 2001/07/14 20:39:26 lampret`
57			`// Better configurability.`
58			`//`
59			`// Revision 1.1 2001/06/05 07:45:26 lampret`
60			`// Added initial RTL and test benches. There are still some issues with these files.`
61			`//`
62			`//`
63
64			`//`
65			`// Number of GPIO I/O signals`
66			`//`
67			`// This is the most important parameter of the GPIO IP core. It defines how many`
68			`// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are`
69			`// required, use several instances of GPIO IP core.`
70			`//`
71			`// Default is 16.`
72			`//`
73			`define GPIO_IOS 16
74
75			`//`
76			`// Undefine this one if you don't want to remove GPIO block from your design`
77			`// but you also don't need it. When it is undefined, all GPIO ports still`
78			`// remain valid and the core can be synthesized however internally there is`
79			`// no GPIO funationality.`
80			`//`
81			`// Defined by default (duhh !).`
82			`//`
83			`define GPIO_IMPLEMENTED
84
85	17	lampret	`//`
86			`// Define to register all WISHBONE outputs.`
87			`//`
88			`// Register outputs if you are using GPIO core as a block and synthesizing`
89			`// and place&routing it separately from the rest of the system.`
90			`//`
91			`// If you do not need registered outputs, you can save some area by not defining`
92			`// this macro. By default it is defined.`
93			`//`
94			`define GPIO_REGISTERED_WB_OUTPUTS
95
96			`//`
97			`// Define to register all GPIO pad outputs.`
98			`//`
99			`// Register outputs if you are using GPIO core as a block and synthesizing`
100			`// and place&routing it separately from the rest of the system.`
101			`//`
102			`// If you do not need registered outputs, you can save some area by not defining`
103			`// this macro. By default it is defined.`
104			`//`
105			`define GPIO_REGISTERED_IO_OUTPUTS
106
107			`//`
108			`// Define to avoid using negative edge clock flip-flops for external clock`
109			`// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with`
110			`// positive edge clock flip-flops will be used.`
111			`//`
112			`// By default it is defined.`
113			`//`
114			`define GPIO_NO_NEGEDGE_FLOPS
115
116	14	lampret	`//`
117			`// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.`
118			`// When it is undefined all reads of GPIO registers return RGPIO_IN register. This`
119			`// is usually useful if you want really small area (for example when implemented in`
120			`// FPGA).`
121			`//`
122			`// To follow GPIO IP core specification document this one must be defined. Also to`
123			`// successfully run the test bench it must be defined. By default it is defined.`
124			`//`
125			`define GPIO_READREGS
126
127			`//`
128			`// Full WISHBONE address decoding`
129			`//`
130			`// It is is undefined, partial WISHBONE address decoding is performed.`
131			`// Undefine it if you need to save some area.`
132			`//`
133			`// By default it is defined.`
134			`//`
135			`define GPIO_FULL_DECODE
136
137			`//`
138			`// Strict 32-bit WISHBONE access`
139			`//`
140			`// If this one is defined, all WISHBONE accesses must be 32-bit. If it is`
141			`// not defined, err_o is asserted whenever 8- or 16-bit access is made.`
142			`// Undefine it if you need to save some area.`
143			`//`
144			`// By default it is defined.`
145			`//`
146			`define GPIO_STRICT_32BIT_ACCESS
147
148			`//`
149			`// WISHBONE address bits used for full decoding of GPIO registers.`
150			`//`
151	17	lampret	`define GPIO_ADDRHH 6
152	14	lampret	`define GPIO_ADDRHL 5
153			`define GPIO_ADDRLH 1
154			`define GPIO_ADDRLL 0
155
156			`//`
157			`// Bits of WISHBONE address used for partial decoding of GPIO registers.`
158			`//`
159			`// Default 4:2.`
160			`//`
161			`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
162
163			`//`
164			`// Addresses of GPIO registers`
165			`//`
166			`// To comply with GPIO IP core specification document they must go from`
167			`// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,`
168			`// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL`
169			`//`
170			`// If particular register is not needed, it's address definition can be omitted`
171			`// and the register will not be implemented. Instead a fixed default value will`
172			`// be used.`
173			`//`
174			`define GPIO_RGPIO_IN 3'h0 // Address 0x00
175			`define GPIO_RGPIO_OUT 3'h1 // Address 0x04
176			`define GPIO_RGPIO_OE 3'h2 // Address 0x08
177			`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c
178			`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
179			`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
180			`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
181
182			`//`
183			`// Default values for unimplemented GPIO registers`
184			`//`
185			`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
186			`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0
187			`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0
188			`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0
189			`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0
190			`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0
191			`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0
192
193			`//`
194			`// RGPIO_CTRL bits`
195			`//`
196			`// To comply with the GPIO IP core specification document they must go from`
197			`// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT`
198			`//`
199			`define GPIO_RGPIO_CTRL_ECLK 0
200			`define GPIO_RGPIO_CTRL_NEC 1
201			`define GPIO_RGPIO_CTRL_INTE 2
202			`define GPIO_RGPIO_CTRL_INT 3

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[/] [gpio/] [trunk/] [rtl/] [verilog/] [gpio_defines.v] - Blame information for rev 17