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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE General-Purpose I/O                                ////
////                                                              ////
////  This file is part of the GPIO project                       ////
////  http://www.opencores.org/cores/gpio/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of GPIO IP core according to                 ////
////  GPIO IP core specification document.                        ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/12/25 17:21:21  lampret
// Fixed two typos.
//
// Revision 1.6  2001/12/25 17:12:35  lampret
// Added RGPIO_INTS.
//
// Revision 1.5  2001/12/12 20:35:53  lampret
// Fixing style.
//
// Revision 1.4  2001/12/12 07:12:58  lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
// Revision 1.3  2001/11/15 02:24:37  lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.2  2001/10/31 02:26:51  lampret
// Fixed wb_err_o.
//
// Revision 1.1  2001/09/18 18:49:07  lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1  2001/08/21 21:39:28  lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2  2001/07/14 20:39:26  lampret
// Better configurability.
//
// Revision 1.1  2001/06/05 07:45:26  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
 
module gpio_top(
        // WISHBONE Interface
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
        // Auxiliary inputs interface
        aux_i,
 
        // External GPIO Interface
        in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
);
 
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
input                   wb_clk_i;       // Clock
input                   wb_rst_i;       // Reset
input                   wb_cyc_i;       // cycle valid input
input   [aw-1:0] wb_adr_i;       // address bus inputs
input   [dw-1:0] wb_dat_i;       // input data bus
input   [3:0]            wb_sel_i;       // byte select inputs
input                   wb_we_i;        // indicates write transfer
input                   wb_stb_i;       // strobe input
output  [dw-1:0] wb_dat_o;       // output data bus
output                  wb_ack_o;       // normal termination
output                  wb_err_o;       // termination w/ error
output                  wb_inta_o;      // Interrupt request output
 
// Auxiliary Inputs Interface
input   [gw-1:0] aux_i;          // Auxiliary inputs
 
//
// External GPIO Interface
//
input   [gw-1:0] in_pad_i;       // GPIO Inputs
input                   ext_clk_pad_i;  // GPIO Eclk
output  [gw-1:0] out_pad_o;      // GPIO Outputs
output  [gw-1:0] oen_padoen_o;   // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
`else
wire    [gw-1:0] rgpio_in;       // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
`else
wire    [gw-1:0] rgpio_out;      // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
`else
wire    [gw-1:0] rgpio_oe;       // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
`else
wire    [gw-1:0] rgpio_inte;     // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
`else
wire    [gw-1:0] rgpio_ptrig;    // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
`else
wire    [gw-1:0] rgpio_aux;      // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register
`else
wire    [3:0]            rgpio_ctrl;     // No register
`endif
 
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
`else
wire    [gw-1:0] rgpio_ints;     // No register
`endif
 
//
// Internal wires & regs
//
wire                    rgpio_out_sel;  // RGPIO_OUT select
wire                    rgpio_oe_sel;   // RGPIO_OE select
wire                    rgpio_inte_sel; // RGPIO_INTE select
wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select
wire                    rgpio_aux_sel;  // RGPIO_AUX select
wire                    rgpio_ctrl_sel; // RGPIO_CTRL select
wire                    rgpio_ints_sel; // RGPIO_INTS select
wire                    latch_clk;      // Latch clock
wire                    full_decoding;  // Full address decoding qualification
wire    [gw-1:0] in_muxed;       // Muxed inputs
wire                    wb_ack;         // WB Acknowledge
wire                    wb_err;         // WB Error
wire                    wb_inta;        // WB Interrupt
reg     [dw-1:0] wb_dat;         // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg                     wb_ack_o;       // WB Acknowledge
reg                     wb_err_o;       // WB Error
reg                     wb_inta_o;      // WB Interrupt
reg     [dw-1:0] wb_dat_o;       // WB Data out
`endif
wire    [gw-1:0] out_pad;        // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg     [gw-1:0] out_pad_o;      // GPIO Outputs
`endif
wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock
wire                    pext_clk;       // External clock for posedge flops
reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs
`endif
 
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
//    any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
 
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
 
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_ack & ~wb_ack_o;
`else
assign wb_ack_o = wb_ack;
`endif
 
//
// WB Error
//
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
`endif
`endif
 
//
// Optional registration of WB error
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & ~wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
 
//
// GPIO registers address decoder
//
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ctrl <= #1 4'b0;
        else if (rgpio_ctrl_sel && wb_we_i)
                rgpio_ctrl <= #1 wb_dat_i[3:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_out <= #1 {gw{1'b0}};
        else if (rgpio_out_sel && wb_we_i)
                rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_oe <= #1 {gw{1'b0}};
        else if (rgpio_oe_sel && wb_we_i)
                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_inte <= #1 {gw{1'b0}};
        else if (rgpio_inte_sel && wb_we_i)
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ptrig <= #1 {gw{1'b0}};
        else if (rgpio_ptrig_sel && wb_we_i)
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_aux <= #1 {gw{1'b0}};
        else if (rgpio_aux_sel && wb_we_i)
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_in <= #1 {gw{1'b0}};
        else
                rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
`else
assign pext_clk = ext_clk_pad_i;
`endif
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
`endif
 
//
// Latch using posedge external clock
//
always @(posedge pext_clk or posedge wb_rst_i)
        if (wb_rst_i)
                pextc_sampled <= #1 {gw{1'b0}};
        else
                pextc_sampled <= #1 in_pad_i;
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge ext_clk_pad_i or posedge wb_rst_i)
        if (wb_rst_i)
                nextc_sampled <= #1 {gw{1'b0}};
        else
                nextc_sampled <= #1 in_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
                `GPIO_RGPIO_OUT: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};
                end
                `GPIO_RGPIO_OE: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};
                end
                `GPIO_RGPIO_INTE: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};
                end
                `GPIO_RGPIO_PTRIG: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};
                end
                `GPIO_RGPIO_AUX: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};
                end
                `GPIO_RGPIO_CTRL: begin
                        wb_dat[3:0] = rgpio_ctrl;
                        wb_dat[dw-1:4] = {dw-4{1'b0}};
                end
`endif
                `GPIO_RGPIO_INTS: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};
                end
                default: begin
                        wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
                end
        endcase
 
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else
                wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
 
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                rgpio_ints <= #1 {gw{1'b0}};
        else if (rgpio_ints_sel && wb_we_i)
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
                rgpio_ints <= #1 rgpio_ints | (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`else
assign rgpio_ints = (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_inta_o <= #1 1'b0;
        else
                wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
 
//
// Output enables are RGPIO_OE bits
//
assign oen_padoen_o = rgpio_oe;
 
//
// Generate GPIO outputs
//
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                out_pad_o <= #1 {gw{1'b0}};
        else
                out_pad_o <= #1 out_pad;
`else
assign out_pad_o = out_pad;
`endif
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign oen_padoen_o = {gw{1'b1}};
assign out_pad_o = {gw{1'b0}};
 
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	14	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE General-Purpose I/O ////`
4			`//// ////`
5			`//// This file is part of the GPIO project ////`
6			`//// http://www.opencores.org/cores/gpio/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of GPIO IP core according to ////`
10			`//// GPIO IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	23	lampret	`// Revision 1.7 2001/12/25 17:21:21 lampret`
49			`// Fixed two typos.`
50			`//`
51	22	lampret	`// Revision 1.6 2001/12/25 17:12:35 lampret`
52			`// Added RGPIO_INTS.`
53			`//`
54	21	lampret	`// Revision 1.5 2001/12/12 20:35:53 lampret`
55			`// Fixing style.`
56			`//`
57	20	lampret	`// Revision 1.4 2001/12/12 07:12:58 lampret`
58			`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`
59			`//`
60	19	lampret	`// Revision 1.3 2001/11/15 02:24:37 lampret`
61			`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
62			`//`
63	17	lampret	`// Revision 1.2 2001/10/31 02:26:51 lampret`
64			`// Fixed wb_err_o.`
65			`//`
66	15	lampret	`// Revision 1.1 2001/09/18 18:49:07 lampret`
67			`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
68			`//`
69	14	lampret	`// Revision 1.1 2001/08/21 21:39:28 lampret`
70			`// Changed directory structure, port names and drfines.`
71			`//`
72			`// Revision 1.2 2001/07/14 20:39:26 lampret`
73			`// Better configurability.`
74			`//`
75			`// Revision 1.1 2001/06/05 07:45:26 lampret`
76			`// Added initial RTL and test benches. There are still some issues with these files.`
77			`//`
78			`//`
79
80			`// synopsys translate_off`
81			`include "timescale.v"
82			`// synopsys translate_on`
83			`include "gpio_defines.v"
84
85			`module gpio_top(`
86			`// WISHBONE Interface`
87			`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
88			`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`
89
90			`// Auxiliary inputs interface`
91			`aux_i,`
92
93			`// External GPIO Interface`
94			`in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o`
95			`);`
96
97			`parameter dw = 32;`
98			parameter aw = `GPIO_ADDRHH+1;
99			parameter gw = `GPIO_IOS;
100
101			`//`
102			`// WISHBONE Interface`
103			`//`
104			`input wb_clk_i; // Clock`
105			`input wb_rst_i; // Reset`
106			`input wb_cyc_i; // cycle valid input`
107			`input [aw-1:0] wb_adr_i; // address bus inputs`
108			`input [dw-1:0] wb_dat_i; // input data bus`
109			`input [3:0] wb_sel_i; // byte select inputs`
110			`input wb_we_i; // indicates write transfer`
111			`input wb_stb_i; // strobe input`
112			`output [dw-1:0] wb_dat_o; // output data bus`
113			`output wb_ack_o; // normal termination`
114			`output wb_err_o; // termination w/ error`
115			`output wb_inta_o; // Interrupt request output`
116
117			`// Auxiliary Inputs Interface`
118			`input [gw-1:0] aux_i; // Auxiliary inputs`
119
120			`//`
121			`// External GPIO Interface`
122			`//`
123			`input [gw-1:0] in_pad_i; // GPIO Inputs`
124			`input ext_clk_pad_i; // GPIO Eclk`
125			`output [gw-1:0] out_pad_o; // GPIO Outputs`
126			`output [gw-1:0] oen_padoen_o; // GPIO output drivers enables`
127
128			`ifdef GPIO_IMPLEMENTED
129
130			`//`
131			`// GPIO Input Register (or no register)`
132			`//`
133			`ifdef GPIO_RGPIO_IN
134			`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
135			`else
136			`wire [gw-1:0] rgpio_in; // No register`
137			`endif
138
139			`//`
140			`// GPIO Output Register (or no register)`
141			`//`
142			`ifdef GPIO_RGPIO_OUT
143			`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
144			`else
145			`wire [gw-1:0] rgpio_out; // No register`
146			`endif
147
148			`//`
149			`// GPIO Output Driver Enable Register (or no register)`
150			`//`
151			`ifdef GPIO_RGPIO_OE
152			`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
153			`else
154			`wire [gw-1:0] rgpio_oe; // No register`
155			`endif
156
157			`//`
158			`// GPIO Interrupt Enable Register (or no register)`
159			`//`
160			`ifdef GPIO_RGPIO_INTE
161			`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
162			`else
163			`wire [gw-1:0] rgpio_inte; // No register`
164			`endif
165
166			`//`
167			`// GPIO Positive edge Triggered Register (or no register)`
168			`//`
169			`ifdef GPIO_RGPIO_PTRIG
170			`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
171			`else
172			`wire [gw-1:0] rgpio_ptrig; // No register`
173			`endif
174
175			`//`
176			`// GPIO Auxiliary select Register (or no register)`
177			`//`
178			`ifdef GPIO_RGPIO_AUX
179			`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
180			`else
181			`wire [gw-1:0] rgpio_aux; // No register`
182			`endif
183
184			`//`
185			`// GPIO Control Register (or no register)`
186			`//`
187			`ifdef GPIO_RGPIO_CTRL
188			`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
189			`else
190			`wire [3:0] rgpio_ctrl; // No register`
191			`endif
192
193			`//`
194	21	lampret	`// GPIO Interrupt Status Register (or no register)`
195			`//`
196			`ifdef GPIO_RGPIO_INTS
197			`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`
198			`else
199			`wire [gw-1:0] rgpio_ints; // No register`
200			`endif
201
202			`//`
203	14	lampret	`// Internal wires & regs`
204			`//`
205			`wire rgpio_out_sel; // RGPIO_OUT select`
206			`wire rgpio_oe_sel; // RGPIO_OE select`
207			`wire rgpio_inte_sel; // RGPIO_INTE select`
208			`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
209			`wire rgpio_aux_sel; // RGPIO_AUX select`
210			`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
211	21	lampret	`wire rgpio_ints_sel; // RGPIO_INTS select`
212	14	lampret	`wire latch_clk; // Latch clock`
213			`wire full_decoding; // Full address decoding qualification`
214	17	lampret	`wire [gw-1:0] in_muxed; // Muxed inputs`
215			`wire wb_ack; // WB Acknowledge`
216			`wire wb_err; // WB Error`
217			`wire wb_inta; // WB Interrupt`
218			`reg [dw-1:0] wb_dat; // WB Data out`
219			`ifdef GPIO_REGISTERED_WB_OUTPUTS
220			`reg wb_ack_o; // WB Acknowledge`
221			`reg wb_err_o; // WB Error`
222			`reg wb_inta_o; // WB Interrupt`
223			`reg [dw-1:0] wb_dat_o; // WB Data out`
224			`endif
225			`wire [gw-1:0] out_pad; // GPIO Outputs`
226			`ifdef GPIO_REGISTERED_IO_OUTPUTS
227			`reg [gw-1:0] out_pad_o; // GPIO Outputs`
228			`endif
229			`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`
230			`wire pext_clk; // External clock for posedge flops`
231			`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`
232			`ifdef GPIO_NO_NEGEDGE_FLOPS
233			`else
234			`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`
235			`endif
236	14	lampret
237			`//`
238			`// All WISHBONE transfer terminations are successful except when:`
239			`// a) full address decoding is enabled and address doesn't match`
240			`// any of the GPIO registers`
241			`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
242			`//`
243	17	lampret
244			`//`
245			`// WB Acknowledge`
246			`//`
247			`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`
248
249			`//`
250			`// Optional registration of WB Ack`
251			`//`
252			`ifdef GPIO_REGISTERED_WB_OUTPUTS
253			`always @(posedge wb_clk_i or posedge wb_rst_i)`
254			`if (wb_rst_i)`
255			`wb_ack_o <= #1 1'b0;`
256			`else`
257	23	lampret	`wb_ack_o <= #1 wb_ack & ~wb_ack_o;`
258	17	lampret	`else
259			`assign wb_ack_o = wb_ack;`
260			`endif
261
262			`//`
263			`// WB Error`
264			`//`
265	14	lampret	`ifdef GPIO_FULL_DECODE
266			`ifdef GPIO_STRICT_32BIT_ACCESS
267	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
268	14	lampret	`else
269	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`
270	14	lampret	`endif
271			`else
272			`ifdef GPIO_STRICT_32BIT_ACCESS
273	17	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
274	14	lampret	`else
275	17	lampret	`assign wb_err = 1'b0;`
276	14	lampret	`endif
277			`endif
278
279			`//`
280	17	lampret	`// Optional registration of WB error`
281	14	lampret	`//`
282	17	lampret	`ifdef GPIO_REGISTERED_WB_OUTPUTS
283			`always @(posedge wb_clk_i or posedge wb_rst_i)`
284			`if (wb_rst_i)`
285			`wb_err_o <= #1 1'b0;`
286			`else`
287	23	lampret	`wb_err_o <= #1 wb_err & ~wb_err_o;`
288	17	lampret	`else
289			`assign wb_err_o = wb_err;`
290			`endif
291	14	lampret
292			`//`
293			`// Full address decoder`
294			`//`
295			`ifdef GPIO_FULL_DECODE
296			assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
297			(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
298			`else
299			`assign full_decoding = 1'b1;`
300			`endif
301
302			`//`
303			`// GPIO registers address decoder`
304			`//`
305			assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
306			assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
307			assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
308			assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
309			assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
310			assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
311	21	lampret	assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
312	14	lampret
313			`//`
314			`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
315			`//`
316			`ifdef GPIO_RGPIO_CTRL
317			`always @(posedge wb_clk_i or posedge wb_rst_i)`
318			`if (wb_rst_i)`
319			`rgpio_ctrl <= #1 4'b0;`
320			`else if (rgpio_ctrl_sel && wb_we_i)`
321			`rgpio_ctrl <= #1 wb_dat_i[3:0];`
322			else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
323	21	lampret	rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;
324	14	lampret	`else
325			`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
326			`endif
327
328			`//`
329			`// Write to RGPIO_OUT`
330			`//`
331			`ifdef GPIO_RGPIO_OUT
332			`always @(posedge wb_clk_i or posedge wb_rst_i)`
333			`if (wb_rst_i)`
334			`rgpio_out <= #1 {gw{1'b0}};`
335			`else if (rgpio_out_sel && wb_we_i)`
336			`rgpio_out <= #1 wb_dat_i[gw-1:0];`
337			`else
338	17	lampret	assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
339	14	lampret	`endif
340
341			`//`
342	17	lampret	`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`
343	14	lampret	`//`
344			`ifdef GPIO_RGPIO_OE
345			`always @(posedge wb_clk_i or posedge wb_rst_i)`
346			`if (wb_rst_i)`
347			`rgpio_oe <= #1 {gw{1'b0}};`
348			`else if (rgpio_oe_sel && wb_we_i)`
349	17	lampret	`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`
350	14	lampret	`else
351			assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
352			`endif
353
354			`//`
355			`// Write to RGPIO_INTE`
356			`//`
357			`ifdef GPIO_RGPIO_INTE
358			`always @(posedge wb_clk_i or posedge wb_rst_i)`
359			`if (wb_rst_i)`
360			`rgpio_inte <= #1 {gw{1'b0}};`
361			`else if (rgpio_inte_sel && wb_we_i)`
362			`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
363			`else
364			assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
365			`endif
366
367			`//`
368			`// Write to RGPIO_PTRIG`
369			`//`
370			`ifdef GPIO_RGPIO_PTRIG
371			`always @(posedge wb_clk_i or posedge wb_rst_i)`
372			`if (wb_rst_i)`
373			`rgpio_ptrig <= #1 {gw{1'b0}};`
374			`else if (rgpio_ptrig_sel && wb_we_i)`
375			`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`
376			`else
377			assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
378			`endif
379
380			`//`
381			`// Write to RGPIO_AUX`
382			`//`
383			`ifdef GPIO_RGPIO_AUX
384			`always @(posedge wb_clk_i or posedge wb_rst_i)`
385			`if (wb_rst_i)`
386			`rgpio_aux <= #1 {gw{1'b0}};`
387			`else if (rgpio_aux_sel && wb_we_i)`
388			`rgpio_aux <= #1 wb_dat_i[gw-1:0];`
389			`else
390			assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
391			`endif
392
393			`//`
394			`// Latch into RGPIO_IN`
395			`//`
396			`ifdef GPIO_RGPIO_IN
397	17	lampret	`always @(posedge wb_clk_i or posedge wb_rst_i)`
398	14	lampret	`if (wb_rst_i)`
399			`rgpio_in <= #1 {gw{1'b0}};`
400			`else`
401	17	lampret	`rgpio_in <= #1 in_muxed;`
402	14	lampret	`else
403	17	lampret	`assign rgpio_in = in_muxed;`
404	14	lampret	`endif
405
406			`//`
407	17	lampret	`// Mux inputs directly from input pads with inputs sampled by external clock`
408	14	lampret	`//`
409	17	lampret	assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
410
411			`//`
412			`// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.`
413			`// If negedge flops are allowed, pext_clk only clocks posedge flops.`
414			`//`
415			`ifdef GPIO_NO_NEGEDGE_FLOPS
416			assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
417			`else
418			`assign pext_clk = ext_clk_pad_i;`
419			`endif
420
421			`//`
422			`// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.`
423			`//`
424			`ifdef GPIO_NO_NEGEDGE_FLOPS
425			`assign extc_in = pextc_sampled;`
426			`else
427			assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
428			`endif
429
430			`//`
431			`// Latch using posedge external clock`
432			`//`
433			`always @(posedge pext_clk or posedge wb_rst_i)`
434			`if (wb_rst_i)`
435			`pextc_sampled <= #1 {gw{1'b0}};`
436			`else`
437			`pextc_sampled <= #1 in_pad_i;`
438
439			`//`
440			`// Latch using negedge external clock`
441			`//`
442			`ifdef GPIO_NO_NEGEDGE_FLOPS
443			`else
444			`always @(negedge ext_clk_pad_i or posedge wb_rst_i)`
445			`if (wb_rst_i)`
446			`nextc_sampled <= #1 {gw{1'b0}};`
447			`else`
448			`nextc_sampled <= #1 in_pad_i;`
449			`endif
450
451			`//`
452			`// Mux all registers when doing a read of GPIO registers`
453			`//`
454	14	lampret	`always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or`
455	22	lampret	`rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)`
456	14	lampret	case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
457			`ifdef GPIO_READREGS
458			`GPIO_RGPIO_OUT: begin
459	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};`
460	14	lampret	`end`
461			`GPIO_RGPIO_OE: begin
462	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};`
463	14	lampret	`end`
464			`GPIO_RGPIO_INTE: begin
465	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};`
466	14	lampret	`end`
467			`GPIO_RGPIO_PTRIG: begin
468	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};`
469	14	lampret	`end`
470			`GPIO_RGPIO_AUX: begin
471	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};`
472	14	lampret	`end`
473			`GPIO_RGPIO_CTRL: begin
474	20	lampret	`wb_dat[3:0] = rgpio_ctrl;`
475			`wb_dat[dw-1:4] = {dw-4{1'b0}};`
476	14	lampret	`end`
477			`endif
478	21	lampret	`GPIO_RGPIO_INTS: begin
479			`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};`
480			`end`
481	14	lampret	`default: begin`
482	20	lampret	`wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};`
483	14	lampret	`end`
484			`endcase`
485
486			`//`
487	17	lampret	`// WB data output`
488			`//`
489			`ifdef GPIO_REGISTERED_WB_OUTPUTS
490			`always @(posedge wb_clk_i or posedge wb_rst_i)`
491			`if (wb_rst_i)`
492			`wb_dat_o <= #1 {dw{1'b0}};`
493			`else`
494			`wb_dat_o <= #1 wb_dat;`
495			`else
496			`assign wb_dat_o = wb_dat;`
497			`endif
498
499			`//`
500	21	lampret	`// RGPIO_INTS`

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