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[/] [gpio/] [trunk/] [sim/] [rtl_sim/] [log/] [ncelab.log] - Blame information for rev 54
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Rev |
Author |
Line |
| 1 |
54 |
gorand |
TOOL: ncelab 04.10-b001: Started on Dec 09, 2003 at 12:18:09
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48 |
gorand |
ncelab
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-f ncelab.args
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-MESSAGES
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-NOCOPYRIGHT
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-CDSLIB ../bin/cds.lib
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-HDLVAR ../bin/hdl.var
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-LOGFILE ../log/ncelab.log
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-SNAPSHOT worklib.bench:rtl
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-NO_TCHK_MSG
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-ACCESS +RWC
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worklib.tb_tasks
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worklib.gpio_testbench
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Elaborating the design hierarchy:
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Caching library 'worklib' ....... Done
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Building instance overlay tables: .................... Done
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Generating native compiled code:
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worklib.clkrst:v <0x67faf15a>
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streams: 2, words: 1034
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worklib.gpio_mon:v <0x50b5485b>
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streams: 6, words: 1408
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worklib.gpio_testbench:v <0x2b2f512c>
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streams: 2, words: 300
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worklib.gpio_top:v <0x2a4cd65a>
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streams: 72, words: 55544
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worklib.tb_tasks:v <0x3e6d21f9>
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streams: 33, words: 52966
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worklib.wb_master:v <0x2119db6d>
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streams: 38, words: 21648
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Loading native compiled code: .................... Done
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Building instance specific data structures.
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Design hierarchy summary:
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Instances Unique
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Modules: 6 6
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Registers: 122 122
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Scalar wires: 23 -
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Vectored wires: 14 -
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Always blocks: 24 24
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Initial blocks: 3 3
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Cont. assignments: 10 17
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Pseudo assignments: 2 43
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Simulation timescale: 10ps
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Writing initial simulation snapshot: worklib.bench:rtl
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54 |
gorand |
TOOL: ncelab 04.10-b001: Exiting on Dec 09, 2003 at 12:18:10 (total: 00:00:01)
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