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https://opencores.org/ocsvn/gpio/gpio/trunk
[/] [gpio/] [trunk/] [sim/] [rtl_sim/] [log/] [ncelab.log] - Blame information for rev 65
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Rev |
Author |
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56 |
gorand |
TOOL: ncelab 04.10-b001: Started on Dec 17, 2003 at 12:34:14
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48 |
gorand |
ncelab
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-f ncelab.args
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-MESSAGES
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-NOCOPYRIGHT
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-CDSLIB ../bin/cds.lib
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-HDLVAR ../bin/hdl.var
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-LOGFILE ../log/ncelab.log
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-SNAPSHOT worklib.bench:rtl
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-NO_TCHK_MSG
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-ACCESS +RWC
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worklib.tb_tasks
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worklib.gpio_testbench
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Elaborating the design hierarchy:
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Caching library 'worklib' ....... Done
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Building instance overlay tables: .................... Done
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Generating native compiled code:
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worklib.clkrst:v <0x67faf15a>
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streams: 2, words: 1034
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worklib.gpio_mon:v <0x50b5485b>
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streams: 6, words: 1408
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56 |
gorand |
worklib.gpio_testbench:v <0x26ac113d>
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48 |
gorand |
streams: 2, words: 300
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56 |
gorand |
worklib.gpio_top:v <0x566f67ec>
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streams: 205, words: 164573
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worklib.tb_tasks:v <0x0ae72b6b>
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streams: 39, words: 57166
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worklib.wb_master:v <0x008f4b18>
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streams: 38, words: 21666
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48 |
gorand |
Loading native compiled code: .................... Done
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Building instance specific data structures.
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Design hierarchy summary:
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Instances Unique
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Modules: 6 6
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56 |
gorand |
Registers: 130 130
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Scalar wires: 85 -
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Vectored wires: 13 -
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Always blocks: 56 56
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48 |
gorand |
Initial blocks: 3 3
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56 |
gorand |
Cont. assignments: 40 79
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Pseudo assignments: 2 49
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48 |
gorand |
Simulation timescale: 10ps
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Writing initial simulation snapshot: worklib.bench:rtl
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56 |
gorand |
TOOL: ncelab 04.10-b001: Exiting on Dec 17, 2003 at 12:34:15 (total: 00:00:01)
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