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[/] [graphicsaccelerator/] [trunk/] [Bresenhamer.syr] - Blame information for rev 2

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Release 12.3 - xst M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.11 secs
 
-->
Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.11 secs
 
-->
Reading design: Bresenhamer.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Bresenhamer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "Bresenhamer"
Output Format                      : NGC
Target Device                      : xa3s200-4-ftg256
 
---- Source Options
Top Module Name                    : Bresenhamer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/omar/LineFPGA/Bresenhamer.vhd" in Library work.
Architecture behavioral of Entity bresenhamer is up to date.
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity  in library  (architecture ).
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity  in library  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "/home/omar/LineFPGA/Bresenhamer.vhd".
    Using one-hot encoding for signal .
INFO:Xst:2117 - HDL ADVISOR - Mux Selector  of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal  (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector  of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal  (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found 11-bit comparator less for signal  created at line 27.
    Found 11-bit comparator less for signal  created at line 30.
    Found 11-bit subtractor for signal .
    Found 11-bit subtractor for signal .
    Found 11-bit up counter for signal .
    Found 11-bit register for signal .
    Found 11-bit up counter for signal .
    Found 11-bit register for signal .
    Found 11-bit adder for signal .
    Found 11-bit adder for signal .
    Found 11-bit adder for signal .
    Found 11-bit adder for signal  created at line 44.
    Found 11-bit adder for signal .
    Found 11-bit adder for signal  created at line 43.
    Found 11-bit register for signal .
    Found 11-bit adder for signal .
    Found 11-bit adder for signal .
    Found 3-bit register for signal .
    Found 11-bit comparator equal for signal  created at line 70.
    Found 11-bit comparator equal for signal  created at line 79.
    Found 11-bit comparator greater for signal  created at line 57.
    Summary:
        inferred   2 Counter(s).
        inferred  36 D-type flip-flop(s).
        inferred  10 Adder/Subtractor(s).
        inferred   5 Comparator(s).
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Adders/Subtractors                                   : 4
 11-bit adder                                          : 2
 11-bit subtractor                                     : 2
# Counters                                             : 2
 11-bit up counter                                     : 2
# Registers                                            : 3
 11-bit register                                       : 2
 3-bit register                                        : 1
# Comparators                                          : 5
 11-bit comparator equal                               : 2
 11-bit comparator greater                             : 1
 11-bit comparator less                                : 2
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2404 -  FFs/Latches > (without init value) have a constant value of 0 in block .
WARNING:Xst:2404 -  FFs/Latches > (without init value) have a constant value of 0 in block .
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# Adders/Subtractors                                   : 2
 11-bit subtractor                                     : 2
# Counters                                             : 2
 11-bit up counter                                     : 2
# Registers                                            : 22
 Flip-Flops                                            : 22
# Comparators                                          : 5
 11-bit comparator equal                               : 2
 11-bit comparator greater                             : 1
 11-bit comparator less                                : 2
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Bresenhamer, actual ratio is 3.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 44
 Flip-Flops                                            : 44
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : Bresenhamer.ngr
Top Level Output File Name         : Bresenhamer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
 
Design Statistics
# IOs                              : 60
 
Cell Usage :
# BELS                             : 262
#      GND                         : 1
#      INV                         : 5
#      LUT2                        : 52
#      LUT3                        : 60
#      LUT3_L                      : 2
#      LUT4                        : 14
#      MUXCY                       : 82
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 44
# FlipFlops/Latches                : 44
#      FD                          : 3
#      FDE                         : 41
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 59
#      IBUF                        : 39
#      OBUF                        : 20
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : xa3s200ftg256-4
 
 Number of Slices:                       72  out of   1920     3%
 Number of Slice Flip Flops:             44  out of   3840     1%
 Number of 4 input LUTs:                133  out of   3840     3%
 Number of IOs:                          60
 Number of bonded IOBs:                  60  out of    173    34%
 Number of GCLKs:                         1  out of      8    12%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 44    |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -4
 
   Minimum period: 8.554ns (Maximum Frequency: 116.904MHz)
   Minimum input arrival time before clock: 9.971ns
   Maximum output required time after clock: 9.658ns
   Maximum combinational path delay: No path found
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 8.554ns (frequency: 116.904MHz)
  Total number of paths / destination ports: 1630 / 66
-------------------------------------------------------------------------
Delay:               8.554ns (Levels of Logic = 15)
  Source:            myY2_0 (FF)
  Destination:       State_1 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising
 
  Data Path: myY2_0 to State_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.720   1.216  myY2_0 (myY2_0)
     LUT2:I0->O            1   0.551   0.000  Msub_dy_lut<0> (Msub_dy_lut<0>)
     MUXCY:S->O            1   0.500   0.000  Msub_dy_cy<0> (Msub_dy_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<1> (Msub_dy_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<2> (Msub_dy_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<3> (Msub_dy_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<4> (Msub_dy_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<5> (Msub_dy_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<6> (Msub_dy_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<7> (Msub_dy_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  Msub_dy_cy<8> (Msub_dy_cy<8>)
     MUXCY:CI->O           0   0.064   0.000  Msub_dy_cy<9> (Msub_dy_cy<9>)
     XORCY:CI->O           1   0.904   1.140  Msub_dy_xor<10> (dy<10>)
     LUT2:I0->O            1   0.551   0.000  Mcompar_State_cmp_gt0001_lut<10> (Mcompar_State_cmp_gt0001_lut<10>)
     MUXCY:S->O            2   0.739   0.903  Mcompar_State_cmp_gt0001_cy<10> (Mcompar_State_cmp_gt0001_cy<10>)
     LUT4:I3->O            1   0.551   0.000  State_mux0001<1> (State_mux0001<1>)
     FD:D                      0.203          State_1
    ----------------------------------------
    Total                      8.554ns (5.295ns logic, 3.259ns route)
                                       (61.9% logic, 38.1% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
  Total number of paths / destination ports: 4529 / 82
-------------------------------------------------------------------------
Offset:              9.971ns (Levels of Logic = 25)
  Source:            X1<0> (PAD)
  Destination:       myX1_10 (FF)
  Destination Clock: Clk rising
 
  Data Path: X1<0> to myX1_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.821   1.246  X1_0_IBUF (X1_0_IBUF)
     LUT2:I0->O            1   0.551   0.000  Mcompar_condX1X2_cmp_lt0000_lut<0> (Mcompar_condX1X2_cmp_lt0000_lut<0>)
     MUXCY:S->O            1   0.500   0.000  Mcompar_condX1X2_cmp_lt0000_cy<0> (Mcompar_condX1X2_cmp_lt0000_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<1> (Mcompar_condX1X2_cmp_lt0000_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<2> (Mcompar_condX1X2_cmp_lt0000_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<3> (Mcompar_condX1X2_cmp_lt0000_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<4> (Mcompar_condX1X2_cmp_lt0000_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<5> (Mcompar_condX1X2_cmp_lt0000_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<6> (Mcompar_condX1X2_cmp_lt0000_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<7> (Mcompar_condX1X2_cmp_lt0000_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_condX1X2_cmp_lt0000_cy<8> (Mcompar_condX1X2_cmp_lt0000_cy<8>)
     MUXCY:CI->O          20   0.303   1.884  Mcompar_condX1X2_cmp_lt0000_cy<9> (Mcompar_condX1X2_cmp_lt0000_cy<9>)
     LUT3:I0->O            1   0.551   0.869  nextMyX1<0>1 (nextMyX1<0>)
     LUT3:I2->O            1   0.551   0.000  Mcount_myX1_lut<0> (Mcount_myX1_lut<0>)
     MUXCY:S->O            1   0.500   0.000  Mcount_myX1_cy<0> (Mcount_myX1_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<1> (Mcount_myX1_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<2> (Mcount_myX1_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<3> (Mcount_myX1_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<4> (Mcount_myX1_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<5> (Mcount_myX1_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<6> (Mcount_myX1_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<7> (Mcount_myX1_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_myX1_cy<8> (Mcount_myX1_cy<8>)
     MUXCY:CI->O           0   0.064   0.000  Mcount_myX1_cy<9> (Mcount_myX1_cy<9>)
     XORCY:CI->O           1   0.904   0.000  Mcount_myX1_xor<10> (Mcount_myX110)
     FDE:D                     0.203          myX1_10
    ----------------------------------------
    Total                      9.971ns (5.972ns logic, 3.999ns route)
                                       (59.9% logic, 40.1% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 20 / 20
-------------------------------------------------------------------------
Offset:              9.658ns (Levels of Logic = 2)
  Source:            State_0 (FF)
  Destination:       WriteEnable (PAD)
  Source Clock:      Clk rising
 
  Data Path: State_0 to WriteEnable
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              29   0.720   1.836  State_0 (State_0)
     INV:I->O              3   0.551   0.907  State<0>_inv11_INV_0 (State<0>_inv1)
     OBUF:I->O                 5.644          WriteEnable_OBUF (WriteEnable)
    ----------------------------------------
    Total                      9.658ns (6.915ns logic, 2.743ns route)
                                       (71.6% logic, 28.4% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 3.95 secs
 
-->
 
 
Total memory usage is 148732 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    2 (   0 filtered)
 

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Subversion Repositories graphicsaccelerator

[/] [graphicsaccelerator/] [trunk/] [Bresenhamer.syr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	OmarMokhta	`Release 12.3 - xst M.70d (lin)`
2			`Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.`
3			`-->`
4			`Parameter TMPDIR set to xst/projnav.tmp`
5
6
7			`Total REAL time to Xst completion: 1.00 secs`
8			`Total CPU time to Xst completion: 0.11 secs`
9
10			`-->`
11			`Parameter xsthdpdir set to xst`
12
13
14			`Total REAL time to Xst completion: 1.00 secs`
15			`Total CPU time to Xst completion: 0.11 secs`
16
17			`-->`
18			`Reading design: Bresenhamer.prj`
19
20			`TABLE OF CONTENTS`
21			`1) Synthesis Options Summary`
22			`2) HDL Compilation`
23			`3) Design Hierarchy Analysis`
24			`4) HDL Analysis`
25			`5) HDL Synthesis`
26			`5.1) HDL Synthesis Report`
27			`6) Advanced HDL Synthesis`
28			`6.1) Advanced HDL Synthesis Report`
29			`7) Low Level Synthesis`
30			`8) Partition Report`
31			`9) Final Report`
32			`9.1) Device utilization summary`
33			`9.2) Partition Resource Summary`
34			`9.3) TIMING REPORT`
35
36
37			`=========================================================================`
38			`* Synthesis Options Summary *`
39			`=========================================================================`
40			`---- Source Parameters`
41			`Input File Name : "Bresenhamer.prj"`
42			`Input Format : mixed`
43			`Ignore Synthesis Constraint File : NO`
44
45			`---- Target Parameters`
46			`Output File Name : "Bresenhamer"`
47			`Output Format : NGC`
48			`Target Device : xa3s200-4-ftg256`
49
50			`---- Source Options`
51			`Top Module Name : Bresenhamer`
52			`Automatic FSM Extraction : YES`
53			`FSM Encoding Algorithm : Auto`
54			`Safe Implementation : No`
55			`FSM Style : LUT`
56			`RAM Extraction : Yes`
57			`RAM Style : Auto`
58			`ROM Extraction : Yes`
59			`Mux Style : Auto`
60			`Decoder Extraction : YES`
61			`Priority Encoder Extraction : Yes`
62			`Shift Register Extraction : YES`
63			`Logical Shifter Extraction : YES`
64			`XOR Collapsing : YES`
65			`ROM Style : Auto`
66			`Mux Extraction : Yes`
67			`Resource Sharing : YES`
68			`Asynchronous To Synchronous : NO`
69			`Multiplier Style : Auto`
70			`Automatic Register Balancing : No`
71
72			`---- Target Options`
73			`Add IO Buffers : YES`
74			`Global Maximum Fanout : 500`
75			`Add Generic Clock Buffer(BUFG) : 8`
76			`Register Duplication : YES`
77			`Slice Packing : YES`
78			`Optimize Instantiated Primitives : NO`
79			`Use Clock Enable : Yes`
80			`Use Synchronous Set : Yes`
81			`Use Synchronous Reset : Yes`
82			`Pack IO Registers into IOBs : Auto`
83			`Equivalent register Removal : YES`
84
85			`---- General Options`
86			`Optimization Goal : Speed`
87			`Optimization Effort : 1`
88			`Keep Hierarchy : No`
89			`Netlist Hierarchy : As_Optimized`
90			`RTL Output : Yes`
91			`Global Optimization : AllClockNets`
92			`Read Cores : YES`
93			`Write Timing Constraints : NO`
94			`Cross Clock Analysis : NO`
95			`Hierarchy Separator : /`
96			`Bus Delimiter : <>`
97			`Case Specifier : Maintain`
98			`Slice Utilization Ratio : 100`
99			`BRAM Utilization Ratio : 100`
100			`Verilog 2001 : YES`
101			`Auto BRAM Packing : NO`
102			`Slice Utilization Ratio Delta : 5`
103
104			`=========================================================================`
105
106
107			`=========================================================================`
108			`* HDL Compilation *`
109			`=========================================================================`
110			`Compiling vhdl file "/home/omar/LineFPGA/Bresenhamer.vhd" in Library work.`
111			`Architecture behavioral of Entity bresenhamer is up to date.`
112
113			`=========================================================================`
114			`* Design Hierarchy Analysis *`
115			`=========================================================================`
116			`Analyzing hierarchy for entity in library (architecture ).`
117
118
119			`=========================================================================`
120			`* HDL Analysis *`
121			`=========================================================================`
122			`Analyzing Entity in library (Architecture ).`
123			`Entity analyzed. Unit generated.`
124
125
126			`=========================================================================`
127			`* HDL Synthesis *`
128			`=========================================================================`
129
130			`Performing bidirectional port resolution...`
131
132			`Synthesizing Unit .`
133			`Related source file is "/home/omar/LineFPGA/Bresenhamer.vhd".`
134			`Using one-hot encoding for signal .`
135			`INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:`
136			`- add an 'INIT' attribute on signal (optimization is then done without any risk)`
137			`- use the attribute 'signal_encoding user' to avoid onehot optimization`
138			`- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization`
139			`INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:`
140			`- add an 'INIT' attribute on signal (optimization is then done without any risk)`
141			`- use the attribute 'signal_encoding user' to avoid onehot optimization`
142			`- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization`
143			`Found 11-bit comparator less for signal created at line 27.`
144			`Found 11-bit comparator less for signal created at line 30.`
145			`Found 11-bit subtractor for signal .`
146			`Found 11-bit subtractor for signal .`
147			`Found 11-bit up counter for signal .`
148			`Found 11-bit register for signal .`
149			`Found 11-bit up counter for signal .`
150			`Found 11-bit register for signal .`
151			`Found 11-bit adder for signal .`
152			`Found 11-bit adder for signal .`
153			`Found 11-bit adder for signal .`
154			`Found 11-bit adder for signal created at line 44.`
155			`Found 11-bit adder for signal .`
156			`Found 11-bit adder for signal created at line 43.`
157			`Found 11-bit register for signal` `.`
158			`Found 11-bit adder for signal .`
159			`Found 11-bit adder for signal .`
160			`Found 3-bit register for signal .`
161			`Found 11-bit comparator equal for signal created at line 70.`
162			`Found 11-bit comparator equal for signal created at line 79.`
163			`Found 11-bit comparator greater for signal created at line 57.`
164			`Summary:`
165			`inferred 2 Counter(s).`
166			`inferred 36 D-type flip-flop(s).`
167			`inferred 10 Adder/Subtractor(s).`
168			`inferred 5 Comparator(s).`
169			`Unit synthesized.`
170
171
172			`=========================================================================`
173			`HDL Synthesis Report`
174
175			`Macro Statistics`
176			`# Adders/Subtractors : 4`
177			`11-bit adder : 2`
178			`11-bit subtractor : 2`
179			`# Counters : 2`
180			`11-bit up counter : 2`
181			`# Registers : 3`
182			`11-bit register : 2`
183			`3-bit register : 1`
184			`# Comparators : 5`
185			`11-bit comparator equal : 2`
186			`11-bit comparator greater : 1`
187			`11-bit comparator less : 2`
188
189			`=========================================================================`
190
191			`=========================================================================`
192			`* Advanced HDL Synthesis *`
193			`=========================================================================`
194
195			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
196			`WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
197			`WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
198			`WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .`
199			`WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .`
200
201			`=========================================================================`
202			`Advanced HDL Synthesis Report`
203
204			`Macro Statistics`
205			`# Adders/Subtractors : 2`
206			`11-bit subtractor : 2`
207			`# Counters : 2`
208			`11-bit up counter : 2`
209			`# Registers : 22`
210			`Flip-Flops : 22`
211			`# Comparators : 5`
212			`11-bit comparator equal : 2`
213			`11-bit comparator greater : 1`
214			`11-bit comparator less : 2`
215
216			`=========================================================================`
217
218			`=========================================================================`
219			`* Low Level Synthesis *`
220			`=========================================================================`
221
222			`Optimizing unit ...`
223
224			`Mapping all equations...`
225			`Building and optimizing final netlist ...`
226			`Found area constraint ratio of 100 (+ 5) on block Bresenhamer, actual ratio is 3.`
227
228			`Final Macro Processing ...`
229
230			`=========================================================================`
231			`Final Register Report`
232
233			`Macro Statistics`
234			`# Registers : 44`
235			`Flip-Flops : 44`
236
237			`=========================================================================`
238
239			`=========================================================================`
240			`* Partition Report *`
241			`=========================================================================`
242
243			`Partition Implementation Status`
244			`-------------------------------`
245
246			`No Partitions were found in this design.`
247
248			`-------------------------------`
249
250			`=========================================================================`
251			`* Final Report *`
252			`=========================================================================`
253			`Final Results`
254			`RTL Top Level Output File Name : Bresenhamer.ngr`
255			`Top Level Output File Name : Bresenhamer`
256			`Output Format : NGC`
257			`Optimization Goal : Speed`
258			`Keep Hierarchy : No`
259
260			`Design Statistics`
261			`# IOs : 60`
262
263			`Cell Usage :`
264			`# BELS : 262`
265			`# GND : 1`
266			`# INV : 5`
267			`# LUT2 : 52`
268			`# LUT3 : 60`
269			`# LUT3_L : 2`
270			`# LUT4 : 14`
271			`# MUXCY : 82`
272			`# MUXF5 : 1`
273			`# VCC : 1`
274			`# XORCY : 44`
275			`# FlipFlops/Latches : 44`
276			`# FD : 3`
277			`# FDE : 41`
278			`# Clock Buffers : 1`
279			`# BUFGP : 1`
280			`# IO Buffers : 59`
281			`# IBUF : 39`
282			`# OBUF : 20`
283			`=========================================================================`
284
285			`Device utilization summary:`
286			`---------------------------`
287
288			`Selected Device : xa3s200ftg256-4`
289
290			`Number of Slices: 72 out of 1920 3%`
291			`Number of Slice Flip Flops: 44 out of 3840 1%`
292			`Number of 4 input LUTs: 133 out of 3840 3%`
293			`Number of IOs: 60`
294			`Number of bonded IOBs: 60 out of 173 34%`
295			`Number of GCLKs: 1 out of 8 12%`
296
297			`---------------------------`
298			`Partition Resource Summary:`
299			`---------------------------`
300
301			`No Partitions were found in this design.`
302
303			`---------------------------`
304
305
306			`=========================================================================`
307			`TIMING REPORT`
308
309			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
310			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
311			`GENERATED AFTER PLACE-and-ROUTE.`
312
313			`Clock Information:`
314			`------------------`
315			`-----------------------------------+------------------------+-------+`
316			`Clock Signal \| Clock buffer(FF name) \| Load \|`
317			`-----------------------------------+------------------------+-------+`
318			`Clk \| BUFGP \| 44 \|`
319			`-----------------------------------+------------------------+-------+`
320
321			`Asynchronous Control Signals Information:`
322			`----------------------------------------`
323			`No asynchronous control signals found in this design`
324
325			`Timing Summary:`
326			`---------------`
327			`Speed Grade: -4`
328
329			`Minimum period: 8.554ns (Maximum Frequency: 116.904MHz)`
330			`Minimum input arrival time before clock: 9.971ns`
331			`Maximum output required time after clock: 9.658ns`
332			`Maximum combinational path delay: No path found`
333
334			`Timing Detail:`
335			`--------------`
336			`All values displayed in nanoseconds (ns)`
337
338			`=========================================================================`
339			`Timing constraint: Default period analysis for Clock 'Clk'`
340			`Clock period: 8.554ns (frequency: 116.904MHz)`
341			`Total number of paths / destination ports: 1630 / 66`
342			`-------------------------------------------------------------------------`
343			`Delay: 8.554ns (Levels of Logic = 15)`
344			`Source: myY2_0 (FF)`
345			`Destination: State_1 (FF)`
346			`Source Clock: Clk rising`
347			`Destination Clock: Clk rising`
348
349			`Data Path: myY2_0 to State_1`
350			`Gate Net`
351			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
352			`---------------------------------------- ------------`
353			`FDE:C->Q 2 0.720 1.216 myY2_0 (myY2_0)`
354			`LUT2:I0->O 1 0.551 0.000 Msub_dy_lut<0> (Msub_dy_lut<0>)`
355			`MUXCY:S->O 1 0.500 0.000 Msub_dy_cy<0> (Msub_dy_cy<0>)`
356			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<1> (Msub_dy_cy<1>)`
357			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<2> (Msub_dy_cy<2>)`
358			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<3> (Msub_dy_cy<3>)`
359			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<4> (Msub_dy_cy<4>)`
360			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<5> (Msub_dy_cy<5>)`
361			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<6> (Msub_dy_cy<6>)`
362			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<7> (Msub_dy_cy<7>)`
363			`MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<8> (Msub_dy_cy<8>)`
364			`MUXCY:CI->O 0 0.064 0.000 Msub_dy_cy<9> (Msub_dy_cy<9>)`
365			`XORCY:CI->O 1 0.904 1.140 Msub_dy_xor<10> (dy<10>)`
366			`LUT2:I0->O 1 0.551 0.000 Mcompar_State_cmp_gt0001_lut<10> (Mcompar_State_cmp_gt0001_lut<10>)`
367			`MUXCY:S->O 2 0.739 0.903 Mcompar_State_cmp_gt0001_cy<10> (Mcompar_State_cmp_gt0001_cy<10>)`
368			`LUT4:I3->O 1 0.551 0.000 State_mux0001<1> (State_mux0001<1>)`
369			`FD:D 0.203 State_1`
370			`----------------------------------------`
371			`Total 8.554ns (5.295ns logic, 3.259ns route)`
372			`(61.9% logic, 38.1% route)`
373
374			`=========================================================================`
375			`Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'`
376			`Total number of paths / destination ports: 4529 / 82`
377			`-------------------------------------------------------------------------`
378			`Offset: 9.971ns (Levels of Logic = 25)`
379			`Source: X1<0> (PAD)`
380			`Destination: myX1_10 (FF)`
381			`Destination Clock: Clk rising`
382
383			`Data Path: X1<0> to myX1_10`
384			`Gate Net`
385			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
386			`---------------------------------------- ------------`
387			`IBUF:I->O 3 0.821 1.246 X1_0_IBUF (X1_0_IBUF)`
388			`LUT2:I0->O 1 0.551 0.000 Mcompar_condX1X2_cmp_lt0000_lut<0> (Mcompar_condX1X2_cmp_lt0000_lut<0>)`
389			`MUXCY:S->O 1 0.500 0.000 Mcompar_condX1X2_cmp_lt0000_cy<0> (Mcompar_condX1X2_cmp_lt0000_cy<0>)`
390			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<1> (Mcompar_condX1X2_cmp_lt0000_cy<1>)`
391			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<2> (Mcompar_condX1X2_cmp_lt0000_cy<2>)`
392			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<3> (Mcompar_condX1X2_cmp_lt0000_cy<3>)`
393			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<4> (Mcompar_condX1X2_cmp_lt0000_cy<4>)`
394			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<5> (Mcompar_condX1X2_cmp_lt0000_cy<5>)`
395			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<6> (Mcompar_condX1X2_cmp_lt0000_cy<6>)`
396			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<7> (Mcompar_condX1X2_cmp_lt0000_cy<7>)`
397			`MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<8> (Mcompar_condX1X2_cmp_lt0000_cy<8>)`
398			`MUXCY:CI->O 20 0.303 1.884 Mcompar_condX1X2_cmp_lt0000_cy<9> (Mcompar_condX1X2_cmp_lt0000_cy<9>)`
399			`LUT3:I0->O 1 0.551 0.869 nextMyX1<0>1 (nextMyX1<0>)`
400			`LUT3:I2->O 1 0.551 0.000 Mcount_myX1_lut<0> (Mcount_myX1_lut<0>)`
401			`MUXCY:S->O 1 0.500 0.000 Mcount_myX1_cy<0> (Mcount_myX1_cy<0>)`
402			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<1> (Mcount_myX1_cy<1>)`
403			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<2> (Mcount_myX1_cy<2>)`
404			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<3> (Mcount_myX1_cy<3>)`
405			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<4> (Mcount_myX1_cy<4>)`
406			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<5> (Mcount_myX1_cy<5>)`
407			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<6> (Mcount_myX1_cy<6>)`
408			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<7> (Mcount_myX1_cy<7>)`
409			`MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<8> (Mcount_myX1_cy<8>)`
410			`MUXCY:CI->O 0 0.064 0.000 Mcount_myX1_cy<9> (Mcount_myX1_cy<9>)`
411			`XORCY:CI->O 1 0.904 0.000 Mcount_myX1_xor<10> (Mcount_myX110)`
412			`FDE:D 0.203 myX1_10`
413			`----------------------------------------`
414			`Total 9.971ns (5.972ns logic, 3.999ns route)`
415			`(59.9% logic, 40.1% route)`
416
417			`=========================================================================`
418			`Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'`
419			`Total number of paths / destination ports: 20 / 20`
420			`-------------------------------------------------------------------------`
421			`Offset: 9.658ns (Levels of Logic = 2)`
422			`Source: State_0 (FF)`
423			`Destination: WriteEnable (PAD)`
424			`Source Clock: Clk rising`
425
426			`Data Path: State_0 to WriteEnable`
427			`Gate Net`
428			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
429			`---------------------------------------- ------------`
430			`FD:C->Q 29 0.720 1.836 State_0 (State_0)`
431			`INV:I->O 3 0.551 0.907 State<0>_inv11_INV_0 (State<0>_inv1)`
432			`OBUF:I->O 5.644 WriteEnable_OBUF (WriteEnable)`
433			`----------------------------------------`
434			`Total 9.658ns (6.915ns logic, 2.743ns route)`
435			`(71.6% logic, 28.4% route)`
436
437			`=========================================================================`
438
439
440			`Total REAL time to Xst completion: 6.00 secs`
441			`Total CPU time to Xst completion: 3.95 secs`
442
443			`-->`
444
445
446			`Total memory usage is 148732 kilobytes`
447
448			`Number of errors : 0 ( 0 filtered)`
449			`Number of warnings : 5 ( 0 filtered)`
450			`Number of infos : 2 ( 0 filtered)`
451