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OmarMokhta |
Release 12.3 - xst M.70d (lin)
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Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.11 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.11 secs
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-->
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Reading design: Bresenhamer.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "Bresenhamer.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "Bresenhamer"
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Output Format : NGC
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Target Device : xa3s200-4-ftg256
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---- Source Options
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Top Module Name : Bresenhamer
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/omar/LineFPGA/Bresenhamer.vhd" in Library work.
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Architecture behavioral of Entity bresenhamer is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity in library (architecture ).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/Bresenhamer.vhd".
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Using one-hot encoding for signal .
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INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
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- add an 'INIT' attribute on signal (optimization is then done without any risk)
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- use the attribute 'signal_encoding user' to avoid onehot optimization
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- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
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INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
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- add an 'INIT' attribute on signal (optimization is then done without any risk)
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- use the attribute 'signal_encoding user' to avoid onehot optimization
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- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
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Found 11-bit comparator less for signal created at line 27.
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Found 11-bit comparator less for signal created at line 30.
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Found 11-bit subtractor for signal .
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Found 11-bit subtractor for signal .
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Found 11-bit up counter for signal .
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Found 11-bit register for signal .
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Found 11-bit up counter for signal .
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Found 11-bit register for signal .
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Found 11-bit adder for signal .
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Found 11-bit adder for signal .
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Found 11-bit adder for signal .
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Found 11-bit adder for signal created at line 44.
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Found 11-bit adder for signal .
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Found 11-bit adder for signal created at line 43.
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Found 11-bit register for signal .
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Found 11-bit adder for signal .
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Found 11-bit adder for signal .
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Found 3-bit register for signal .
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Found 11-bit comparator equal for signal created at line 70.
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Found 11-bit comparator equal for signal created at line 79.
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Found 11-bit comparator greater for signal created at line 57.
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Summary:
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inferred 2 Counter(s).
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inferred 36 D-type flip-flop(s).
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inferred 10 Adder/Subtractor(s).
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inferred 5 Comparator(s).
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Unit synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 4
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11-bit adder : 2
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11-bit subtractor : 2
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# Counters : 2
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11-bit up counter : 2
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# Registers : 3
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11-bit register : 2
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3-bit register : 1
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# Comparators : 5
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11-bit comparator equal : 2
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11-bit comparator greater : 1
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11-bit comparator less : 2
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
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WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 2
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11-bit subtractor : 2
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# Counters : 2
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11-bit up counter : 2
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# Registers : 22
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Flip-Flops : 22
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# Comparators : 5
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11-bit comparator equal : 2
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11-bit comparator greater : 1
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11-bit comparator less : 2
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block Bresenhamer, actual ratio is 3.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 44
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Flip-Flops : 44
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : Bresenhamer.ngr
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Top Level Output File Name : Bresenhamer
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 60
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Cell Usage :
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# BELS : 262
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# GND : 1
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# INV : 5
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# LUT2 : 52
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# LUT3 : 60
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# LUT3_L : 2
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# LUT4 : 14
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# MUXCY : 82
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# MUXF5 : 1
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# VCC : 1
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# XORCY : 44
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# FlipFlops/Latches : 44
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# FD : 3
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# FDE : 41
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# Clock Buffers : 1
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# BUFGP : 1
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# IO Buffers : 59
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# IBUF : 39
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# OBUF : 20
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : xa3s200ftg256-4
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Number of Slices: 72 out of 1920 3%
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Number of Slice Flip Flops: 44 out of 3840 1%
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Number of 4 input LUTs: 133 out of 3840 3%
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Number of IOs: 60
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Number of bonded IOBs: 60 out of 173 34%
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Number of GCLKs: 1 out of 8 12%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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Clk | BUFGP | 44 |
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-----------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -4
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Minimum period: 8.554ns (Maximum Frequency: 116.904MHz)
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Minimum input arrival time before clock: 9.971ns
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Maximum output required time after clock: 9.658ns
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Maximum combinational path delay: No path found
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'Clk'
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Clock period: 8.554ns (frequency: 116.904MHz)
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Total number of paths / destination ports: 1630 / 66
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-------------------------------------------------------------------------
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Delay: 8.554ns (Levels of Logic = 15)
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Source: myY2_0 (FF)
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Destination: State_1 (FF)
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Source Clock: Clk rising
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Destination Clock: Clk rising
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Data Path: myY2_0 to State_1
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDE:C->Q 2 0.720 1.216 myY2_0 (myY2_0)
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LUT2:I0->O 1 0.551 0.000 Msub_dy_lut<0> (Msub_dy_lut<0>)
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MUXCY:S->O 1 0.500 0.000 Msub_dy_cy<0> (Msub_dy_cy<0>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<1> (Msub_dy_cy<1>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<2> (Msub_dy_cy<2>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<3> (Msub_dy_cy<3>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<4> (Msub_dy_cy<4>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<5> (Msub_dy_cy<5>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<6> (Msub_dy_cy<6>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<7> (Msub_dy_cy<7>)
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MUXCY:CI->O 1 0.064 0.000 Msub_dy_cy<8> (Msub_dy_cy<8>)
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MUXCY:CI->O 0 0.064 0.000 Msub_dy_cy<9> (Msub_dy_cy<9>)
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XORCY:CI->O 1 0.904 1.140 Msub_dy_xor<10> (dy<10>)
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LUT2:I0->O 1 0.551 0.000 Mcompar_State_cmp_gt0001_lut<10> (Mcompar_State_cmp_gt0001_lut<10>)
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MUXCY:S->O 2 0.739 0.903 Mcompar_State_cmp_gt0001_cy<10> (Mcompar_State_cmp_gt0001_cy<10>)
|
368 |
|
|
LUT4:I3->O 1 0.551 0.000 State_mux0001<1> (State_mux0001<1>)
|
369 |
|
|
FD:D 0.203 State_1
|
370 |
|
|
----------------------------------------
|
371 |
|
|
Total 8.554ns (5.295ns logic, 3.259ns route)
|
372 |
|
|
(61.9% logic, 38.1% route)
|
373 |
|
|
|
374 |
|
|
=========================================================================
|
375 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
|
376 |
|
|
Total number of paths / destination ports: 4529 / 82
|
377 |
|
|
-------------------------------------------------------------------------
|
378 |
|
|
Offset: 9.971ns (Levels of Logic = 25)
|
379 |
|
|
Source: X1<0> (PAD)
|
380 |
|
|
Destination: myX1_10 (FF)
|
381 |
|
|
Destination Clock: Clk rising
|
382 |
|
|
|
383 |
|
|
Data Path: X1<0> to myX1_10
|
384 |
|
|
Gate Net
|
385 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
386 |
|
|
---------------------------------------- ------------
|
387 |
|
|
IBUF:I->O 3 0.821 1.246 X1_0_IBUF (X1_0_IBUF)
|
388 |
|
|
LUT2:I0->O 1 0.551 0.000 Mcompar_condX1X2_cmp_lt0000_lut<0> (Mcompar_condX1X2_cmp_lt0000_lut<0>)
|
389 |
|
|
MUXCY:S->O 1 0.500 0.000 Mcompar_condX1X2_cmp_lt0000_cy<0> (Mcompar_condX1X2_cmp_lt0000_cy<0>)
|
390 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<1> (Mcompar_condX1X2_cmp_lt0000_cy<1>)
|
391 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<2> (Mcompar_condX1X2_cmp_lt0000_cy<2>)
|
392 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<3> (Mcompar_condX1X2_cmp_lt0000_cy<3>)
|
393 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<4> (Mcompar_condX1X2_cmp_lt0000_cy<4>)
|
394 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<5> (Mcompar_condX1X2_cmp_lt0000_cy<5>)
|
395 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<6> (Mcompar_condX1X2_cmp_lt0000_cy<6>)
|
396 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<7> (Mcompar_condX1X2_cmp_lt0000_cy<7>)
|
397 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcompar_condX1X2_cmp_lt0000_cy<8> (Mcompar_condX1X2_cmp_lt0000_cy<8>)
|
398 |
|
|
MUXCY:CI->O 20 0.303 1.884 Mcompar_condX1X2_cmp_lt0000_cy<9> (Mcompar_condX1X2_cmp_lt0000_cy<9>)
|
399 |
|
|
LUT3:I0->O 1 0.551 0.869 nextMyX1<0>1 (nextMyX1<0>)
|
400 |
|
|
LUT3:I2->O 1 0.551 0.000 Mcount_myX1_lut<0> (Mcount_myX1_lut<0>)
|
401 |
|
|
MUXCY:S->O 1 0.500 0.000 Mcount_myX1_cy<0> (Mcount_myX1_cy<0>)
|
402 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<1> (Mcount_myX1_cy<1>)
|
403 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<2> (Mcount_myX1_cy<2>)
|
404 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<3> (Mcount_myX1_cy<3>)
|
405 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<4> (Mcount_myX1_cy<4>)
|
406 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<5> (Mcount_myX1_cy<5>)
|
407 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<6> (Mcount_myX1_cy<6>)
|
408 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<7> (Mcount_myX1_cy<7>)
|
409 |
|
|
MUXCY:CI->O 1 0.064 0.000 Mcount_myX1_cy<8> (Mcount_myX1_cy<8>)
|
410 |
|
|
MUXCY:CI->O 0 0.064 0.000 Mcount_myX1_cy<9> (Mcount_myX1_cy<9>)
|
411 |
|
|
XORCY:CI->O 1 0.904 0.000 Mcount_myX1_xor<10> (Mcount_myX110)
|
412 |
|
|
FDE:D 0.203 myX1_10
|
413 |
|
|
----------------------------------------
|
414 |
|
|
Total 9.971ns (5.972ns logic, 3.999ns route)
|
415 |
|
|
(59.9% logic, 40.1% route)
|
416 |
|
|
|
417 |
|
|
=========================================================================
|
418 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
|
419 |
|
|
Total number of paths / destination ports: 20 / 20
|
420 |
|
|
-------------------------------------------------------------------------
|
421 |
|
|
Offset: 9.658ns (Levels of Logic = 2)
|
422 |
|
|
Source: State_0 (FF)
|
423 |
|
|
Destination: WriteEnable (PAD)
|
424 |
|
|
Source Clock: Clk rising
|
425 |
|
|
|
426 |
|
|
Data Path: State_0 to WriteEnable
|
427 |
|
|
Gate Net
|
428 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
429 |
|
|
---------------------------------------- ------------
|
430 |
|
|
FD:C->Q 29 0.720 1.836 State_0 (State_0)
|
431 |
|
|
INV:I->O 3 0.551 0.907 State<0>_inv11_INV_0 (State<0>_inv1)
|
432 |
|
|
OBUF:I->O 5.644 WriteEnable_OBUF (WriteEnable)
|
433 |
|
|
----------------------------------------
|
434 |
|
|
Total 9.658ns (6.915ns logic, 2.743ns route)
|
435 |
|
|
(71.6% logic, 28.4% route)
|
436 |
|
|
|
437 |
|
|
=========================================================================
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
Total REAL time to Xst completion: 6.00 secs
|
441 |
|
|
Total CPU time to Xst completion: 3.95 secs
|
442 |
|
|
|
443 |
|
|
-->
|
444 |
|
|
|
445 |
|
|
|
446 |
|
|
Total memory usage is 148732 kilobytes
|
447 |
|
|
|
448 |
|
|
Number of errors : 0 ( 0 filtered)
|
449 |
|
|
Number of warnings : 5 ( 0 filtered)
|
450 |
|
|
Number of infos : 2 ( 0 filtered)
|
451 |
|
|
|