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OmarMokhta |
Release 12.3 - xst M.70d (lin)
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Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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-->
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Reading design: Synchronizer.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "Synchronizer.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "Synchronizer"
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Output Format : NGC
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Target Device : xa3s200-4-ftg256
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---- Source Options
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Top Module Name : Synchronizer
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/omar/LineFPGA/Synchronizer.vhd" in Library work.
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Architecture behavioral of Entity synchronizer is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity in library (architecture ).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/Synchronizer.vhd".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 43 |
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| Inputs | 5 |
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| Outputs | 8 |
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| Clock | Clk (rising_edge) |
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| Reset | YState$and0000 (positive) |
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| Reset type | synchronous |
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| Reset State | 01 |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 48364 |
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| Inputs | 23 |
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| Outputs | 5 |
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| Clock | Clk (rising_edge) |
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| Clock enable | XState$not0000 (positive) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 9-bit subtractor for signal .
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Found 9-bit register for signal .
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Found 9-bit adder for signal .
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Found 11-bit adder for signal .
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Found 11-bit register for signal .
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Found 21-bit up counter for signal .
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 20 D-type flip-flop(s).
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inferred 3 Adder/Subtractor(s).
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Unit synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 3
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11-bit adder : 1
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9-bit adder : 1
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9-bit subtractor : 1
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# Counters : 1
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21-bit up counter : 1
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# Registers : 2
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11-bit register : 1
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9-bit register : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with gray encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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01 | 01
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10 | 11
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11 | 10
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-------------------
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with gray encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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01 | 01
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10 | 11
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11 | 10
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-------------------
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 2
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# Adders/Subtractors : 3
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11-bit adder : 1
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9-bit adder : 1
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9-bit subtractor : 1
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# Counters : 1
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21-bit up counter : 1
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# Registers : 20
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Flip-Flops : 20
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block Synchronizer, actual ratio is 3.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 45
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Flip-Flops : 45
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : Synchronizer.ngr
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Top Level Output File Name : Synchronizer
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 28
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Cell Usage :
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# BELS : 164
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# GND : 1
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# INV : 3
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# LUT1 : 20
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# LUT2 : 15
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# LUT2_L : 5
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# LUT3 : 17
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# LUT3_L : 4
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# LUT4 : 40
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# LUT4_D : 10
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# LUT4_L : 4
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# MUXCY : 20
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# MUXF5 : 3
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# VCC : 1
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# XORCY : 21
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# FlipFlops/Latches : 45
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# FD : 10
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# FDE : 2
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# FDR : 23
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# FDRE : 9
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# FDS : 1
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# Clock Buffers : 1
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# BUFGP : 1
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# IO Buffers : 27
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# IBUF : 3
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# OBUF : 24
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : xa3s200ftg256-4
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Number of Slices: 62 out of 1920 3%
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Number of Slice Flip Flops: 45 out of 3840 1%
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Number of 4 input LUTs: 118 out of 3840 3%
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Number of IOs: 28
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Number of bonded IOBs: 28 out of 173 16%
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Number of GCLKs: 1 out of 8 12%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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Clk | BUFGP | 45 |
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-----------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -4
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Minimum period: 9.732ns (Maximum Frequency: 102.754MHz)
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: 10.918ns
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Maximum combinational path delay: 8.957ns
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'Clk'
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Clock period: 9.732ns (frequency: 102.754MHz)
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Total number of paths / destination ports: 3100 / 89
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-------------------------------------------------------------------------
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Delay: 9.732ns (Levels of Logic = 5)
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Source: Y_3 (FF)
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Destination: Y_0 (FF)
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Source Clock: Clk rising
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Destination Clock: Clk rising
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Data Path: Y_3 to Y_0
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDR:C->Q 2 0.720 1.216 Y_3 (Y_3)
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LUT2_L:I0->LO 1 0.551 0.126 YState_cmp_eq00001_SW0 (N201)
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LUT4:I3->O 5 0.551 0.989 YState_cmp_eq00001 (N29)
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LUT4:I2->O 16 0.551 1.576 XState_FSM_FFd1-In15 (N2)
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LUT3:I0->O 1 0.551 0.000 Y_or0000_G (N51)
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MUXF5:I1->O 21 0.360 1.515 Y_or0000 (Y_or0000)
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FDR:R 1.026 Y_0
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----------------------------------------
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Total 9.732ns (4.310ns logic, 5.422ns route)
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(44.3% logic, 55.7% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
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Total number of paths / destination ports: 64 / 24
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-------------------------------------------------------------------------
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Offset: 10.918ns (Levels of Logic = 3)
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389 |
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Source: AddressOfY_4 (FF)
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Destination: AddressY<7> (PAD)
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Source Clock: Clk rising
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Data Path: AddressOfY_4 to AddressY<7>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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397 |
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FDRE:C->Q 3 0.720 1.246 AddressOfY_4 (AddressOfY_4)
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398 |
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LUT4:I0->O 7 0.551 1.405 Madd_nAddressOfY_xor<5>1_SW0 (N01)
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|
|
LUT4:I0->O 1 0.551 0.801 Msub_AddressY_xor<7>11 (AddressY_7_OBUF)
|
400 |
|
|
OBUF:I->O 5.644 AddressY_7_OBUF (AddressY<7>)
|
401 |
|
|
----------------------------------------
|
402 |
|
|
Total 10.918ns (7.466ns logic, 3.452ns route)
|
403 |
|
|
(68.4% logic, 31.6% route)
|
404 |
|
|
|
405 |
|
|
=========================================================================
|
406 |
|
|
Timing constraint: Default path analysis
|
407 |
|
|
Total number of paths / destination ports: 3 / 3
|
408 |
|
|
-------------------------------------------------------------------------
|
409 |
|
|
Delay: 8.957ns (Levels of Logic = 3)
|
410 |
|
|
Source: dataIn<1> (PAD)
|
411 |
|
|
Destination: B (PAD)
|
412 |
|
|
|
413 |
|
|
Data Path: dataIn<1> to B
|
414 |
|
|
Gate Net
|
415 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
416 |
|
|
---------------------------------------- ------------
|
417 |
|
|
IBUF:I->O 1 0.821 1.140 dataIn_1_IBUF (dataIn_1_IBUF)
|
418 |
|
|
LUT2:I0->O 1 0.551 0.801 B2 (B_OBUF)
|
419 |
|
|
OBUF:I->O 5.644 B_OBUF (B)
|
420 |
|
|
----------------------------------------
|
421 |
|
|
Total 8.957ns (7.016ns logic, 1.941ns route)
|
422 |
|
|
(78.3% logic, 21.7% route)
|
423 |
|
|
|
424 |
|
|
=========================================================================
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
Total REAL time to Xst completion: 7.00 secs
|
428 |
|
|
Total CPU time to Xst completion: 6.43 secs
|
429 |
|
|
|
430 |
|
|
-->
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
Total memory usage is 150684 kilobytes
|
434 |
|
|
|
435 |
|
|
Number of errors : 0 ( 0 filtered)
|
436 |
|
|
Number of warnings : 0 ( 0 filtered)
|
437 |
|
|
Number of infos : 0 ( 0 filtered)
|
438 |
|
|
|