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OmarMokhta |
Release 13.1 - xst O.40d (lin)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.07 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.07 secs
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-->
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Reading design: VGA_Top.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "VGA_Top.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "VGA_Top"
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Output Format : NGC
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Target Device : xc3s200-5-ft256
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---- Source Options
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Top Module Name : VGA_Top
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/omar/LineFPGA/FrameBuffer2.vhd" in Library work.
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Architecture behavioral of Entity framebuffer is up to date.
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Compiling vhdl file "/home/omar/LineFPGA/Synchronizer.vhd" in Library work.
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Architecture behavioral of Entity synchronizer is up to date.
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Compiling vhdl file "/home/omar/LineFPGA/Debouncer.vhd" in Library work.
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Architecture behavioral of Entity debouncer is up to date.
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Compiling vhdl file "/home/omar/LineFPGA/Bresenhamer.vhd" in Library work.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file "/home/omar/LineFPGA/SevenSegment.vhd" in Library work.
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Architecture behavioral of Entity sevensegment is up to date.
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Compiling vhdl file "/home/omar/LineFPGA/Pointer.vhd" in Library work.
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Architecture behavioral of Entity pointer is up to date.
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Compiling vhdl file "/home/omar/LineFPGA/FreqDiv.vhd" in Library work.
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Architecture behavioral of Entity freqdiv is up to date.
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Compiling vhdl file "/home/omar/LineFPGA/VGA_Top.vhd" in Library work.
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Architecture behavioral of Entity vga_top is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ) with generics.
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initX = "0000000100"
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initY = "011110000"
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ) with generics.
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initX = "1001111000"
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initY = "011110000"
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity in library (Architecture ).
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WARNING:Xst:753 - "/home/omar/LineFPGA/VGA_Top.vhd" line 127: Unconnected output port 'dbg' of component 'Bresenhamer'.
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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initX = "0000000100"
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initY = "011110000"
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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initX = "1001111000"
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initY = "011110000"
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Entity analyzed. Unit generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/FrameBuffer2.vhd".
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 32768x3-bit dual-port RAM for signal .
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Found 3-bit register for signal .
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Summary:
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inferred 1 RAM(s).
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inferred 3 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/Synchronizer.vhd".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 43 |
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| Inputs | 5 |
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| Outputs | 8 |
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| Clock | Clk (rising_edge) |
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| Reset | YState$and0000 (positive) |
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| Reset type | synchronous |
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| Reset State | 01 |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 48364 |
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| Inputs | 23 |
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| Outputs | 5 |
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| Clock | Clk (rising_edge) |
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| Clock enable | XState$not0000 (positive) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 9-bit subtractor for signal .
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Found 9-bit register for signal .
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Found 9-bit adder for signal .
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Found 11-bit adder for signal .
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Found 11-bit register for signal .
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Found 21-bit up counter for signal .
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 20 D-type flip-flop(s).
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inferred 3 Adder/Subtractor(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/Debouncer.vhd".
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Found 2-bit register for signal .
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Found 24-bit register for signal .
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Found 24-bit addsub for signal .
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Summary:
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inferred 26 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/Bresenhamer.vhd".
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 11 |
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| Transitions | 29 |
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| Inputs | 11 |
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| Outputs | 14 |
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| Clock | Clk (rising_edge) |
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| Power Up State | 0000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 19-bit up counter for signal .
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Found 12-bit register for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal .
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Found 12-bit register for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal .
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Found 12-bit register for signal .
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Found 12-bit adder for signal created at line 127.
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Found 12-bit subtractor for signal created at line 150.
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Found 10-bit register for signal >.
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Found 12-bit register for signal .
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Found 12-bit adder for signal created at line 130.
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Found 12-bit subtractor for signal created at line 170.
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Found 9-bit register for signal >.
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Found 12-bit subtractor for signal .
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Found 12-bit subtractor for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal .
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Found 12-bit register for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal .
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Found 12-bit adder for signal created at line 66.
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Found 12-bit adder for signal created at line 67.
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Found 12-bit adder for signal created at line 68.
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Found 12-bit adder for signal created at line 69.
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Found 12-bit adder for signal created at line 69.
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Found 12-bit adder for signal created at line 70.
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Found 12-bit adder for signal created at line 71.
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Found 12-bit adder for signal created at line 71.
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Found 12-bit adder for signal created at line 72.
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Found 12-bit adder for signal created at line 72.
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Found 12-bit adder for signal created at line 73.
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Found 12-bit adder for signal created at line 73.
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Found 12-bit comparator equal for signal created at line 124.
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Found 12-bit comparator equal for signal created at line 134.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 79 D-type flip-flop(s).
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inferred 28 Adder/Subtractor(s).
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inferred 2 Comparator(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/omar/LineFPGA/SevenSegment.vhd".
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Found 16x7-bit ROM for signal .
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Found 1-of-4 decoder for signal .
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Found 4-bit 4-to-1 multiplexer for signal .
|
| 339 |
|
|
Found 17-bit up counter for signal .
|
| 340 |
|
|
Summary:
|
| 341 |
|
|
inferred 1 ROM(s).
|
| 342 |
|
|
inferred 1 Counter(s).
|
| 343 |
|
|
inferred 4 Multiplexer(s).
|
| 344 |
|
|
inferred 1 Decoder(s).
|
| 345 |
|
|
Unit synthesized.
|
| 346 |
|
|
|
| 347 |
|
|
|
| 348 |
|
|
Synthesizing Unit .
|
| 349 |
|
|
Related source file is "/home/omar/LineFPGA/Pointer.vhd".
|
| 350 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 351 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 352 |
|
|
Found 7-bit comparator equal for signal created at line 24.
|
| 353 |
|
|
Found 6-bit comparator equal for signal created at line 24.
|
| 354 |
|
|
Found 10-bit updown counter for signal .
|
| 355 |
|
|
Found 9-bit updown counter for signal .
|
| 356 |
|
|
Summary:
|
| 357 |
|
|
inferred 2 Counter(s).
|
| 358 |
|
|
inferred 2 Comparator(s).
|
| 359 |
|
|
Unit synthesized.
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
Synthesizing Unit .
|
| 363 |
|
|
Related source file is "/home/omar/LineFPGA/FreqDiv.vhd".
|
| 364 |
|
|
Found 20-bit up counter for signal .
|
| 365 |
|
|
Summary:
|
| 366 |
|
|
inferred 1 Counter(s).
|
| 367 |
|
|
Unit synthesized.
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
Synthesizing Unit .
|
| 371 |
|
|
Related source file is "/home/omar/LineFPGA/Pointer.vhd".
|
| 372 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 373 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 374 |
|
|
Found 7-bit comparator equal for signal created at line 24.
|
| 375 |
|
|
Found 6-bit comparator equal for signal created at line 24.
|
| 376 |
|
|
Found 10-bit updown counter for signal .
|
| 377 |
|
|
Found 9-bit updown counter for signal .
|
| 378 |
|
|
Summary:
|
| 379 |
|
|
inferred 2 Counter(s).
|
| 380 |
|
|
inferred 2 Comparator(s).
|
| 381 |
|
|
Unit synthesized.
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
Synthesizing Unit .
|
| 385 |
|
|
Related source file is "/home/omar/LineFPGA/VGA_Top.vhd".
|
| 386 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
| 387 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
| 388 |
|
|
Unit synthesized.
|
| 389 |
|
|
|
| 390 |
|
|
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
| 391 |
|
|
|
| 392 |
|
|
=========================================================================
|
| 393 |
|
|
HDL Synthesis Report
|
| 394 |
|
|
|
| 395 |
|
|
Macro Statistics
|
| 396 |
|
|
# RAMs : 1
|
| 397 |
|
|
32768x3-bit dual-port RAM : 1
|
| 398 |
|
|
# ROMs : 1
|
| 399 |
|
|
16x7-bit ROM : 1
|
| 400 |
|
|
# Adders/Subtractors : 32
|
| 401 |
|
|
11-bit adder : 1
|
| 402 |
|
|
12-bit adder : 24
|
| 403 |
|
|
12-bit subtractor : 4
|
| 404 |
|
|
24-bit addsub : 1
|
| 405 |
|
|
9-bit adder : 1
|
| 406 |
|
|
9-bit subtractor : 1
|
| 407 |
|
|
# Counters : 8
|
| 408 |
|
|
10-bit updown counter : 2
|
| 409 |
|
|
17-bit up counter : 1
|
| 410 |
|
|
19-bit up counter : 1
|
| 411 |
|
|
20-bit up counter : 1
|
| 412 |
|
|
21-bit up counter : 1
|
| 413 |
|
|
9-bit updown counter : 2
|
| 414 |
|
|
# Registers : 51
|
| 415 |
|
|
1-bit register : 43
|
| 416 |
|
|
11-bit register : 1
|
| 417 |
|
|
12-bit register : 3
|
| 418 |
|
|
2-bit register : 1
|
| 419 |
|
|
24-bit register : 1
|
| 420 |
|
|
3-bit register : 1
|
| 421 |
|
|
9-bit register : 1
|
| 422 |
|
|
# Comparators : 6
|
| 423 |
|
|
12-bit comparator equal : 2
|
| 424 |
|
|
6-bit comparator equal : 2
|
| 425 |
|
|
7-bit comparator equal : 2
|
| 426 |
|
|
# Multiplexers : 1
|
| 427 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 428 |
|
|
# Decoders : 1
|
| 429 |
|
|
1-of-4 decoder : 1
|
| 430 |
|
|
|
| 431 |
|
|
=========================================================================
|
| 432 |
|
|
|
| 433 |
|
|
=========================================================================
|
| 434 |
|
|
* Advanced HDL Synthesis *
|
| 435 |
|
|
=========================================================================
|
| 436 |
|
|
|
| 437 |
|
|
Analyzing FSM for best encoding.
|
| 438 |
|
|
Optimizing FSM on signal with one-hot encoding.
|
| 439 |
|
|
----------------------
|
| 440 |
|
|
State | Encoding
|
| 441 |
|
|
----------------------
|
| 442 |
|
|
0000 | 00000000001
|
| 443 |
|
|
1010 | 00000000010
|
| 444 |
|
|
0001 | 00000000100
|
| 445 |
|
|
0010 | 00000001000
|
| 446 |
|
|
0011 | 00000010000
|
| 447 |
|
|
0100 | 00000100000
|
| 448 |
|
|
0101 | 00001000000
|
| 449 |
|
|
0110 | 00010000000
|
| 450 |
|
|
0111 | 00100000000
|
| 451 |
|
|
1000 | 01000000000
|
| 452 |
|
|
1001 | 10000000000
|
| 453 |
|
|
----------------------
|
| 454 |
|
|
Analyzing FSM for best encoding.
|
| 455 |
|
|
Optimizing FSM on signal with gray encoding.
|
| 456 |
|
|
-------------------
|
| 457 |
|
|
State | Encoding
|
| 458 |
|
|
-------------------
|
| 459 |
|
|
00 | 00
|
| 460 |
|
|
01 | 01
|
| 461 |
|
|
10 | 11
|
| 462 |
|
|
11 | 10
|
| 463 |
|
|
-------------------
|
| 464 |
|
|
Analyzing FSM for best encoding.
|
| 465 |
|
|
Optimizing FSM on signal with gray encoding.
|
| 466 |
|
|
-------------------
|
| 467 |
|
|
State | Encoding
|
| 468 |
|
|
-------------------
|
| 469 |
|
|
00 | 00
|
| 470 |
|
|
01 | 01
|
| 471 |
|
|
10 | 11
|
| 472 |
|
|
11 | 10
|
| 473 |
|
|
-------------------
|
| 474 |
|
|
|
| 475 |
|
|
Synthesizing (advanced) Unit .
|
| 476 |
|
|
INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 477 |
|
|
-----------------------------------------------------------------------
|
| 478 |
|
|
| ram_type | Block | |
|
| 479 |
|
|
-----------------------------------------------------------------------
|
| 480 |
|
|
| Port A |
|
| 481 |
|
|
| aspect ratio | 32768-word x 3-bit | |
|
| 482 |
|
|
| mode | read-first | |
|
| 483 |
|
|
| clkA | connected to signal | rise |
|
| 484 |
|
|
| weA | connected to signal | high |
|
| 485 |
|
|
| addrA | connected to signal | |
|
| 486 |
|
|
| diA | connected to signal | |
|
| 487 |
|
|
-----------------------------------------------------------------------
|
| 488 |
|
|
| optimization | speed | |
|
| 489 |
|
|
-----------------------------------------------------------------------
|
| 490 |
|
|
| Port B |
|
| 491 |
|
|
| aspect ratio | 32768-word x 3-bit | |
|
| 492 |
|
|
| mode | write-first | |
|
| 493 |
|
|
| clkB | connected to signal | rise |
|
| 494 |
|
|
| addrB | connected to signal | |
|
| 495 |
|
|
| doB | connected to signal | |
|
| 496 |
|
|
-----------------------------------------------------------------------
|
| 497 |
|
|
| optimization | speed | |
|
| 498 |
|
|
-----------------------------------------------------------------------
|
| 499 |
|
|
Unit synthesized (advanced).
|
| 500 |
|
|
|
| 501 |
|
|
=========================================================================
|
| 502 |
|
|
Advanced HDL Synthesis Report
|
| 503 |
|
|
|
| 504 |
|
|
Macro Statistics
|
| 505 |
|
|
# FSMs : 3
|
| 506 |
|
|
# RAMs : 1
|
| 507 |
|
|
32768x3-bit dual-port block RAM : 1
|
| 508 |
|
|
# ROMs : 1
|
| 509 |
|
|
16x7-bit ROM : 1
|
| 510 |
|
|
# Adders/Subtractors : 32
|
| 511 |
|
|
11-bit adder : 1
|
| 512 |
|
|
12-bit adder : 24
|
| 513 |
|
|
12-bit subtractor : 4
|
| 514 |
|
|
24-bit addsub : 1
|
| 515 |
|
|
9-bit adder : 1
|
| 516 |
|
|
9-bit subtractor : 1
|
| 517 |
|
|
# Counters : 8
|
| 518 |
|
|
10-bit updown counter : 2
|
| 519 |
|
|
17-bit up counter : 1
|
| 520 |
|
|
19-bit up counter : 1
|
| 521 |
|
|
20-bit up counter : 1
|
| 522 |
|
|
21-bit up counter : 1
|
| 523 |
|
|
9-bit updown counter : 2
|
| 524 |
|
|
# Registers : 125
|
| 525 |
|
|
Flip-Flops : 125
|
| 526 |
|
|
# Comparators : 6
|
| 527 |
|
|
12-bit comparator equal : 2
|
| 528 |
|
|
6-bit comparator equal : 2
|
| 529 |
|
|
7-bit comparator equal : 2
|
| 530 |
|
|
# Multiplexers : 1
|
| 531 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 532 |
|
|
# Decoders : 1
|
| 533 |
|
|
1-of-4 decoder : 1
|
| 534 |
|
|
|
| 535 |
|
|
=========================================================================
|
| 536 |
|
|
|
| 537 |
|
|
=========================================================================
|
| 538 |
|
|
* Low Level Synthesis *
|
| 539 |
|
|
=========================================================================
|
| 540 |
|
|
INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only .
|
| 541 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
| 542 |
|
|
|
| 543 |
|
|
Optimizing unit ...
|
| 544 |
|
|
|
| 545 |
|
|
Optimizing unit ...
|
| 546 |
|
|
|
| 547 |
|
|
Optimizing unit ...
|
| 548 |
|
|
|
| 549 |
|
|
Optimizing unit ...
|
| 550 |
|
|
|
| 551 |
|
|
Optimizing unit ...
|
| 552 |
|
|
|
| 553 |
|
|
Optimizing unit ...
|
| 554 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 555 |
|
|
|
| 556 |
|
|
Mapping all equations...
|
| 557 |
|
|
Building and optimizing final netlist ...
|
| 558 |
|
|
Found area constraint ratio of 100 (+ 5) on block VGA_Top, actual ratio is 28.
|
| 559 |
|
|
|
| 560 |
|
|
Final Macro Processing ...
|
| 561 |
|
|
|
| 562 |
|
|
=========================================================================
|
| 563 |
|
|
Final Register Report
|
| 564 |
|
|
|
| 565 |
|
|
Macro Statistics
|
| 566 |
|
|
# Registers : 237
|
| 567 |
|
|
Flip-Flops : 237
|
| 568 |
|
|
|
| 569 |
|
|
=========================================================================
|
| 570 |
|
|
|
| 571 |
|
|
=========================================================================
|
| 572 |
|
|
* Partition Report *
|
| 573 |
|
|
=========================================================================
|
| 574 |
|
|
|
| 575 |
|
|
Partition Implementation Status
|
| 576 |
|
|
-------------------------------
|
| 577 |
|
|
|
| 578 |
|
|
No Partitions were found in this design.
|
| 579 |
|
|
|
| 580 |
|
|
-------------------------------
|
| 581 |
|
|
|
| 582 |
|
|
=========================================================================
|
| 583 |
|
|
* Final Report *
|
| 584 |
|
|
=========================================================================
|
| 585 |
|
|
Final Results
|
| 586 |
|
|
RTL Top Level Output File Name : VGA_Top.ngr
|
| 587 |
|
|
Top Level Output File Name : VGA_Top
|
| 588 |
|
|
Output Format : NGC
|
| 589 |
|
|
Optimization Goal : Speed
|
| 590 |
|
|
Keep Hierarchy : No
|
| 591 |
|
|
|
| 592 |
|
|
Design Statistics
|
| 593 |
|
|
# IOs : 29
|
| 594 |
|
|
|
| 595 |
|
|
Cell Usage :
|
| 596 |
|
|
# BELS : 1785
|
| 597 |
|
|
# GND : 7
|
| 598 |
|
|
# INV : 51
|
| 599 |
|
|
# LUT1 : 84
|
| 600 |
|
|
# LUT2 : 316
|
| 601 |
|
|
# LUT2_D : 3
|
| 602 |
|
|
# LUT2_L : 23
|
| 603 |
|
|
# LUT3 : 117
|
| 604 |
|
|
# LUT3_D : 2
|
| 605 |
|
|
# LUT3_L : 2
|
| 606 |
|
|
# LUT4 : 282
|
| 607 |
|
|
# LUT4_D : 18
|
| 608 |
|
|
# LUT4_L : 30
|
| 609 |
|
|
# MUXCY : 435
|
| 610 |
|
|
# MUXF5 : 17
|
| 611 |
|
|
# VCC : 1
|
| 612 |
|
|
# XORCY : 397
|
| 613 |
|
|
# FlipFlops/Latches : 237
|
| 614 |
|
|
# FD : 34
|
| 615 |
|
|
# FDE : 82
|
| 616 |
|
|
# FDR : 24
|
| 617 |
|
|
# FDRE : 28
|
| 618 |
|
|
# FDS : 69
|
| 619 |
|
|
# RAMS : 6
|
| 620 |
|
|
# RAMB16 : 6
|
| 621 |
|
|
# Clock Buffers : 2
|
| 622 |
|
|
# BUFG : 1
|
| 623 |
|
|
# BUFGP : 1
|
| 624 |
|
|
# IO Buffers : 28
|
| 625 |
|
|
# IBUF : 11
|
| 626 |
|
|
# OBUF : 17
|
| 627 |
|
|
=========================================================================
|
| 628 |
|
|
|
| 629 |
|
|
Device utilization summary:
|
| 630 |
|
|
---------------------------
|
| 631 |
|
|
|
| 632 |
|
|
Selected Device : 3s200ft256-5
|
| 633 |
|
|
|
| 634 |
|
|
Number of Slices: 498 out of 1920 25%
|
| 635 |
|
|
Number of Slice Flip Flops: 237 out of 3840 6%
|
| 636 |
|
|
Number of 4 input LUTs: 928 out of 3840 24%
|
| 637 |
|
|
Number of IOs: 29
|
| 638 |
|
|
Number of bonded IOBs: 29 out of 173 16%
|
| 639 |
|
|
Number of BRAMs: 6 out of 12 50%
|
| 640 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 641 |
|
|
|
| 642 |
|
|
---------------------------
|
| 643 |
|
|
Partition Resource Summary:
|
| 644 |
|
|
---------------------------
|
| 645 |
|
|
|
| 646 |
|
|
No Partitions were found in this design.
|
| 647 |
|
|
|
| 648 |
|
|
---------------------------
|
| 649 |
|
|
|
| 650 |
|
|
|
| 651 |
|
|
=========================================================================
|
| 652 |
|
|
TIMING REPORT
|
| 653 |
|
|
|
| 654 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
| 655 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
| 656 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
| 657 |
|
|
|
| 658 |
|
|
Clock Information:
|
| 659 |
|
|
------------------
|
| 660 |
|
|
-----------------------------------+------------------------+-------+
|
| 661 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 662 |
|
|
-----------------------------------+------------------------+-------+
|
| 663 |
|
|
Clk | BUFGP | 205 |
|
| 664 |
|
|
Inst_FreqDiv/counter_191 | BUFG | 38 |
|
| 665 |
|
|
-----------------------------------+------------------------+-------+
|
| 666 |
|
|
|
| 667 |
|
|
Asynchronous Control Signals Information:
|
| 668 |
|
|
----------------------------------------
|
| 669 |
|
|
No asynchronous control signals found in this design
|
| 670 |
|
|
|
| 671 |
|
|
Timing Summary:
|
| 672 |
|
|
---------------
|
| 673 |
|
|
Speed Grade: -5
|
| 674 |
|
|
|
| 675 |
|
|
Minimum period: 12.431ns (Maximum Frequency: 80.446MHz)
|
| 676 |
|
|
Minimum input arrival time before clock: 7.231ns
|
| 677 |
|
|
Maximum output required time after clock: 15.490ns
|
| 678 |
|
|
Maximum combinational path delay: No path found
|
| 679 |
|
|
|
| 680 |
|
|
Timing Detail:
|
| 681 |
|
|
--------------
|
| 682 |
|
|
All values displayed in nanoseconds (ns)
|
| 683 |
|
|
|
| 684 |
|
|
=========================================================================
|
| 685 |
|
|
Timing constraint: Default period analysis for Clock 'Clk'
|
| 686 |
|
|
Clock period: 12.431ns (frequency: 80.446MHz)
|
| 687 |
|
|
Total number of paths / destination ports: 47319 / 517
|
| 688 |
|
|
-------------------------------------------------------------------------
|
| 689 |
|
|
Delay: 12.431ns (Levels of Logic = 18)
|
| 690 |
|
|
Source: Inst_Bresenhamer/dx_0 (FF)
|
| 691 |
|
|
Destination: Inst_Bresenhamer/p_8 (FF)
|
| 692 |
|
|
Source Clock: Clk rising
|
| 693 |
|
|
Destination Clock: Clk rising
|
| 694 |
|
|
|
| 695 |
|
|
Data Path: Inst_Bresenhamer/dx_0 to Inst_Bresenhamer/p_8
|
| 696 |
|
|
Gate Net
|
| 697 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 698 |
|
|
---------------------------------------- ------------
|
| 699 |
|
|
FDE:C->Q 7 0.626 1.201 Inst_Bresenhamer/dx_0 (Inst_Bresenhamer/dx_0)
|
| 700 |
|
|
LUT1:I0->O 1 0.479 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<0>_rt (Inst_Bresenhamer/Madd_neg_dx_cy<0>_rt)
|
| 701 |
|
|
MUXCY:S->O 1 0.435 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<0> (Inst_Bresenhamer/Madd_neg_dx_cy<0>)
|
| 702 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<1> (Inst_Bresenhamer/Madd_neg_dx_cy<1>)
|
| 703 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<2> (Inst_Bresenhamer/Madd_neg_dx_cy<2>)
|
| 704 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<3> (Inst_Bresenhamer/Madd_neg_dx_cy<3>)
|
| 705 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<4> (Inst_Bresenhamer/Madd_neg_dx_cy<4>)
|
| 706 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<5> (Inst_Bresenhamer/Madd_neg_dx_cy<5>)
|
| 707 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<6> (Inst_Bresenhamer/Madd_neg_dx_cy<6>)
|
| 708 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<7> (Inst_Bresenhamer/Madd_neg_dx_cy<7>)
|
| 709 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<8> (Inst_Bresenhamer/Madd_neg_dx_cy<8>)
|
| 710 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<9> (Inst_Bresenhamer/Madd_neg_dx_cy<9>)
|
| 711 |
|
|
XORCY:CI->O 7 0.786 1.201 Inst_Bresenhamer/Madd_neg_dx_xor<10> (Inst_Bresenhamer/neg_dx<10>)
|
| 712 |
|
|
LUT2:I0->O 1 0.479 0.000 Inst_Bresenhamer/Madd_minus_dx_minus_dy_lut<10> (Inst_Bresenhamer/Madd_minus_dx_minus_dy_lut<10>)
|
| 713 |
|
|
MUXCY:S->O 0 0.435 0.000 Inst_Bresenhamer/Madd_minus_dx_minus_dy_cy<10> (Inst_Bresenhamer/Madd_minus_dx_minus_dy_cy<10>)
|
| 714 |
|
|
XORCY:CI->O 4 0.786 0.802 Inst_Bresenhamer/Madd_minus_dx_minus_dy_xor<11> (Inst_Bresenhamer/minus_dx_minus_dy<11>)
|
| 715 |
|
|
LUT4_D:I3->O 10 0.479 0.987 Inst_Bresenhamer/p_mux0007<10>13 (Inst_Bresenhamer/N34)
|
| 716 |
|
|
LUT4:I3->O 1 0.479 0.704 Inst_Bresenhamer/p_mux0007<8>32_SW0 (N145)
|
| 717 |
|
|
LUT4:I3->O 1 0.479 0.681 Inst_Bresenhamer/p_mux0007<8>59 (Inst_Bresenhamer/p_mux0007<8>59)
|
| 718 |
|
|
FDS:S 0.892 Inst_Bresenhamer/p_8
|
| 719 |
|
|
----------------------------------------
|
| 720 |
|
|
Total 12.431ns (6.855ns logic, 5.576ns route)
|
| 721 |
|
|
(55.1% logic, 44.9% route)
|
| 722 |
|
|
|
| 723 |
|
|
=========================================================================
|
| 724 |
|
|
Timing constraint: Default period analysis for Clock 'Inst_FreqDiv/counter_191'
|
| 725 |
|
|
Clock period: 6.964ns (frequency: 143.593MHz)
|
| 726 |
|
|
Total number of paths / destination ports: 1086 / 76
|
| 727 |
|
|
-------------------------------------------------------------------------
|
| 728 |
|
|
Delay: 6.964ns (Levels of Logic = 4)
|
| 729 |
|
|
Source: Inst_Pointer1/rX_5 (FF)
|
| 730 |
|
|
Destination: Inst_Pointer1/rX_9 (FF)
|
| 731 |
|
|
Source Clock: Inst_FreqDiv/counter_191 rising
|
| 732 |
|
|
Destination Clock: Inst_FreqDiv/counter_191 rising
|
| 733 |
|
|
|
| 734 |
|
|
Data Path: Inst_Pointer1/rX_5 to Inst_Pointer1/rX_9
|
| 735 |
|
|
Gate Net
|
| 736 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 737 |
|
|
---------------------------------------- ------------
|
| 738 |
|
|
FDE:C->Q 6 0.626 1.148 Inst_Pointer1/rX_5 (Inst_Pointer1/rX_5)
|
| 739 |
|
|
LUT4:I0->O 1 0.479 0.976 Inst_Pointer1/rX_not000272 (Inst_Pointer1/rX_not000272)
|
| 740 |
|
|
LUT3:I0->O 1 0.479 0.976 Inst_Pointer1/rX_not000291_SW0 (N224)
|
| 741 |
|
|
LUT4:I0->O 1 0.479 0.000 Inst_Pointer1/rX_not0002117_G (N241)
|
| 742 |
|
|
MUXF5:I1->O 10 0.314 0.964 Inst_Pointer1/rX_not0002117 (Inst_Pointer1/rX_not0002)
|
| 743 |
|
|
FDE:CE 0.524 Inst_Pointer1/rX_0
|
| 744 |
|
|
----------------------------------------
|
| 745 |
|
|
Total 6.964ns (2.901ns logic, 4.063ns route)
|
| 746 |
|
|
(41.7% logic, 58.3% route)
|
| 747 |
|
|
|
| 748 |
|
|
=========================================================================
|
| 749 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
|
| 750 |
|
|
Total number of paths / destination ports: 485 / 161
|
| 751 |
|
|
-------------------------------------------------------------------------
|
| 752 |
|
|
Offset: 7.231ns (Levels of Logic = 27)
|
| 753 |
|
|
Source: button (PAD)
|
| 754 |
|
|
Destination: Inst_Debouncer/Counter_23 (FF)
|
| 755 |
|
|
Destination Clock: Clk rising
|
| 756 |
|
|
|
| 757 |
|
|
Data Path: button to Inst_Debouncer/Counter_23
|
| 758 |
|
|
Gate Net
|
| 759 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 760 |
|
|
---------------------------------------- ------------
|
| 761 |
|
|
IBUF:I->O 50 0.715 1.663 button_IBUF (button_IBUF)
|
| 762 |
|
|
INV:I->O 1 0.479 0.681 Inst_Debouncer/nCounter_mux00012_INV_0 (Inst_Debouncer/nCounter_mux0001)
|
| 763 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<0> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<0>)
|
| 764 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<1> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<1>)
|
| 765 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<2> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<2>)
|
| 766 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<3> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<3>)
|
| 767 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<4> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<4>)
|
| 768 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<5> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<5>)
|
| 769 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<6> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<6>)
|
| 770 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<7> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<7>)
|
| 771 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<8> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<8>)
|
| 772 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<9> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<9>)
|
| 773 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<10> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<10>)
|
| 774 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<11> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<11>)
|
| 775 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<12> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<12>)
|
| 776 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<13> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<13>)
|
| 777 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<14> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<14>)
|
| 778 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<15> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<15>)
|
| 779 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<16> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<16>)
|
| 780 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<17> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<17>)
|
| 781 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<18> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<18>)
|
| 782 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<19> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<19>)
|
| 783 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<20> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<20>)
|
| 784 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<21> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<21>)
|
| 785 |
|
|
MUXCY:CI->O 0 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<22> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<22>)
|
| 786 |
|
|
XORCY:CI->O 1 0.786 0.976 Inst_Debouncer/Maddsub_nCounter_mux0000_xor<23> (Inst_Debouncer/nCounter_mux0000<23>)
|
| 787 |
|
|
LUT3:I0->O 1 0.479 0.000 Inst_Debouncer/nCounter<23>11 (Inst_Debouncer/nCounter<23>1)
|
| 788 |
|
|
FDS:D 0.176 Inst_Debouncer/Counter_23
|
| 789 |
|
|
----------------------------------------
|
| 790 |
|
|
Total 7.231ns (3.912ns logic, 3.319ns route)
|
| 791 |
|
|
(54.1% logic, 45.9% route)
|
| 792 |
|
|
|
| 793 |
|
|
=========================================================================
|
| 794 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_FreqDiv/counter_191'
|
| 795 |
|
|
Total number of paths / destination ports: 666 / 76
|
| 796 |
|
|
-------------------------------------------------------------------------
|
| 797 |
|
|
Offset: 5.177ns (Levels of Logic = 12)
|
| 798 |
|
|
Source: MoveLeft (PAD)
|
| 799 |
|
|
Destination: Inst_Pointer1/rX_9 (FF)
|
| 800 |
|
|
Destination Clock: Inst_FreqDiv/counter_191 rising
|
| 801 |
|
|
|
| 802 |
|
|
Data Path: MoveLeft to Inst_Pointer1/rX_9
|
| 803 |
|
|
Gate Net
|
| 804 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 805 |
|
|
---------------------------------------- ------------
|
| 806 |
|
|
IBUF:I->O 26 0.715 1.841 MoveLeft_IBUF (MoveLeft_IBUF)
|
| 807 |
|
|
LUT2:I0->O 1 0.479 0.681 Inst_Pointer2/rX_not0003_inv2 (Inst_Pointer1/rX_not000227)
|
| 808 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<0> (Inst_Pointer2/Mcount_rX_cy<0>)
|
| 809 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<1> (Inst_Pointer2/Mcount_rX_cy<1>)
|
| 810 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<2> (Inst_Pointer2/Mcount_rX_cy<2>)
|
| 811 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<3> (Inst_Pointer2/Mcount_rX_cy<3>)
|
| 812 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<4> (Inst_Pointer2/Mcount_rX_cy<4>)
|
| 813 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<5> (Inst_Pointer2/Mcount_rX_cy<5>)
|
| 814 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<6> (Inst_Pointer2/Mcount_rX_cy<6>)
|
| 815 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<7> (Inst_Pointer2/Mcount_rX_cy<7>)
|
| 816 |
|
|
MUXCY:CI->O 0 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<8> (Inst_Pointer2/Mcount_rX_cy<8>)
|
| 817 |
|
|
XORCY:CI->O 1 0.786 0.000 Inst_Pointer2/Mcount_rX_xor<9> (Inst_Pointer2/Result<9>)
|
| 818 |
|
|
FDE:D 0.176 Inst_Pointer2/rX_9
|
| 819 |
|
|
----------------------------------------
|
| 820 |
|
|
Total 5.177ns (2.656ns logic, 2.522ns route)
|
| 821 |
|
|
(51.3% logic, 48.7% route)
|
| 822 |
|
|
|
| 823 |
|
|
=========================================================================
|
| 824 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
|
| 825 |
|
|
Total number of paths / destination ports: 654 / 17
|
| 826 |
|
|
-------------------------------------------------------------------------
|
| 827 |
|
|
Offset: 15.490ns (Levels of Logic = 8)
|
| 828 |
|
|
Source: ins_Synchronizer/AddressOfY_1 (FF)
|
| 829 |
|
|
Destination: B (PAD)
|
| 830 |
|
|
Source Clock: Clk rising
|
| 831 |
|
|
|
| 832 |
|
|
Data Path: ins_Synchronizer/AddressOfY_1 to B
|
| 833 |
|
|
Gate Net
|
| 834 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 835 |
|
|
---------------------------------------- ------------
|
| 836 |
|
|
FDRE:C->Q 8 0.626 1.216 ins_Synchronizer/AddressOfY_1 (ins_Synchronizer/AddressOfY_1)
|
| 837 |
|
|
LUT4:I0->O 5 0.479 1.078 ins_Synchronizer/Madd_nAddressOfY_xor<5>1_SW0 (N111)
|
| 838 |
|
|
LUT4:I0->O 8 0.479 1.091 ins_Synchronizer/Msub_AddressY_xor<7>11 (Ady<7>)
|
| 839 |
|
|
LUT4:I1->O 1 0.479 0.704 Inst_Pointer2/Here_and0000231_SW0 (N184)
|
| 840 |
|
|
LUT4:I3->O 1 0.479 0.976 Inst_Pointer2/Here_and0000231 (Inst_Pointer2/Here_and0000231)
|
| 841 |
|
|
LUT4:I0->O 6 0.479 1.023 Inst_Pointer2/Here_and0000244 (p2Region)
|
| 842 |
|
|
LUT4:I1->O 1 0.479 0.000 R11 (R1)
|
| 843 |
|
|
MUXF5:I1->O 1 0.314 0.681 R1_f5 (R_OBUF)
|
| 844 |
|
|
OBUF:I->O 4.909 R_OBUF (R)
|
| 845 |
|
|
----------------------------------------
|
| 846 |
|
|
Total 15.490ns (8.723ns logic, 6.767ns route)
|
| 847 |
|
|
(56.3% logic, 43.7% route)
|
| 848 |
|
|
|
| 849 |
|
|
=========================================================================
|
| 850 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_FreqDiv/counter_191'
|
| 851 |
|
|
Total number of paths / destination ports: 156 / 3
|
| 852 |
|
|
-------------------------------------------------------------------------
|
| 853 |
|
|
Offset: 13.773ns (Levels of Logic = 7)
|
| 854 |
|
|
Source: Inst_Pointer1/rX_5 (FF)
|
| 855 |
|
|
Destination: B (PAD)
|
| 856 |
|
|
Source Clock: Inst_FreqDiv/counter_191 rising
|
| 857 |
|
|
|
| 858 |
|
|
Data Path: Inst_Pointer1/rX_5 to B
|
| 859 |
|
|
Gate Net
|
| 860 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 861 |
|
|
---------------------------------------- ------------
|
| 862 |
|
|
FDE:C->Q 6 0.626 1.023 Inst_Pointer1/rX_5 (Inst_Pointer1/rX_5)
|
| 863 |
|
|
LUT2:I1->O 1 0.479 0.976 Inst_Pointer1/Here_and000085 (Inst_Pointer1/Here_and000085)
|
| 864 |
|
|
LUT4:I0->O 1 0.479 0.851 Inst_Pointer1/Here_and0000196 (Inst_Pointer1/Here_and0000196)
|
| 865 |
|
|
LUT4:I1->O 1 0.479 0.976 Inst_Pointer1/Here_and0000231 (Inst_Pointer1/Here_and0000231)
|
| 866 |
|
|
LUT4:I0->O 6 0.479 1.023 Inst_Pointer1/Here_and0000244 (P1Region)
|
| 867 |
|
|
LUT4:I1->O 1 0.479 0.000 G11 (G1)
|
| 868 |
|
|
MUXF5:I1->O 1 0.314 0.681 G1_f5 (G_OBUF)
|
| 869 |
|
|
OBUF:I->O 4.909 G_OBUF (G)
|
| 870 |
|
|
----------------------------------------
|
| 871 |
|
|
Total 13.773ns (8.244ns logic, 5.529ns route)
|
| 872 |
|
|
(59.9% logic, 40.1% route)
|
| 873 |
|
|
|
| 874 |
|
|
=========================================================================
|
| 875 |
|
|
|
| 876 |
|
|
|
| 877 |
|
|
Total REAL time to Xst completion: 28.00 secs
|
| 878 |
|
|
Total CPU time to Xst completion: 25.69 secs
|
| 879 |
|
|
|
| 880 |
|
|
-->
|
| 881 |
|
|
|
| 882 |
|
|
|
| 883 |
|
|
Total memory usage is 184200 kilobytes
|
| 884 |
|
|
|
| 885 |
|
|
Number of errors : 0 ( 0 filtered)
|
| 886 |
|
|
Number of warnings : 18 ( 0 filtered)
|
| 887 |
|
|
Number of infos : 9 ( 0 filtered)
|
| 888 |
|
|
|
