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Release 13.1 Trace (lin)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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/media/sda9/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3
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-fastpaths -xml VGA_Top.twx VGA_Top.ncd -o VGA_Top.twr VGA_Top.pcf -ucf
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VGA_Top.ucf
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Design file: VGA_Top.ncd
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Physical constraint file: VGA_Top.pcf
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Device,package,speed: xc3s200,ft256,-5 (PRODUCTION 1.39 2011-02-03)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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INFO:Timing:3390 - This architecture does not support a default System Jitter
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value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
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Uncertainty calculation.
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INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
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'Phase Error' calculations, these terms will be zero in the Clock
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Uncertainty calculation. Please make appropriate modification to
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SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
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Error.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock Clk
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------------+------------+------------+------------------+--------+
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|Max Setup to|Max Hold to | | Clock |
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Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
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------------+------------+------------+------------------+--------+
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button | 5.893(R)| -0.176(R)|Clk_BUFGP | 0.000|
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inColor<0> | 3.235(R)| -0.422(R)|Clk_BUFGP | 0.000|
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inColor<1> | 3.864(R)| -0.926(R)|Clk_BUFGP | 0.000|
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inColor<2> | 3.952(R)| -1.232(R)|Clk_BUFGP | 0.000|
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reset | 6.858(R)| -0.299(R)|Clk_BUFGP | 0.000|
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------------+------------+------------+------------------+--------+
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Clock Clk to Pad
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------------+------------+------------------+--------+
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| clk (edge) | | Clock |
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Destination | to PAD |Internal Clock(s) | Phase |
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------------+------------+------------------+--------+
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B | 17.781(R)|Clk_BUFGP | 0.000|
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Enables<0> | 10.183(R)|Clk_BUFGP | 0.000|
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Enables<1> | 10.623(R)|Clk_BUFGP | 0.000|
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Enables<2> | 9.844(R)|Clk_BUFGP | 0.000|
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Enables<3> | 10.854(R)|Clk_BUFGP | 0.000|
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G | 17.810(R)|Clk_BUFGP | 0.000|
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HS | 9.257(R)|Clk_BUFGP | 0.000|
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LED | 11.064(R)|Clk_BUFGP | 0.000|
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R | 17.734(R)|Clk_BUFGP | 0.000|
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Segments<0> | 14.713(R)|Clk_BUFGP | 0.000|
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Segments<1> | 14.558(R)|Clk_BUFGP | 0.000|
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Segments<2> | 15.194(R)|Clk_BUFGP | 0.000|
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Segments<3> | 15.041(R)|Clk_BUFGP | 0.000|
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Segments<4> | 14.937(R)|Clk_BUFGP | 0.000|
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Segments<5> | 14.673(R)|Clk_BUFGP | 0.000|
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Segments<6> | 15.467(R)|Clk_BUFGP | 0.000|
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VS | 10.350(R)|Clk_BUFGP | 0.000|
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------------+------------+------------------+--------+
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Clock to Setup on destination clock Clk
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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Clk | 12.182| | | |
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---------------+---------+---------+---------+---------+
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Analysis completed Tue May 17 19:22:43 2011
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 83 MB
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