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edn_walter |
//megafunction wizard: %Altera SOPC Builder%
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//GENERATION: STANDARD
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//VERSION: WM1.0
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//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module ha1588_comp_avalon_slave_arbitrator (
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// inputs:
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clk,
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ha1588_comp_avalon_slave_readdata,
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master_bfm_latency_counter,
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master_bfm_m0_address_to_slave,
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master_bfm_m0_read,
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master_bfm_m0_write,
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master_bfm_m0_writedata,
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reset_n,
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// outputs:
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d1_ha1588_comp_avalon_slave_end_xfer,
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ha1588_comp_avalon_slave_address,
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ha1588_comp_avalon_slave_read,
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ha1588_comp_avalon_slave_readdata_from_sa,
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ha1588_comp_avalon_slave_reset,
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ha1588_comp_avalon_slave_write,
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ha1588_comp_avalon_slave_writedata,
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master_bfm_granted_ha1588_comp_avalon_slave,
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master_bfm_qualified_request_ha1588_comp_avalon_slave,
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master_bfm_read_data_valid_ha1588_comp_avalon_slave,
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master_bfm_requests_ha1588_comp_avalon_slave
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)
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;
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output d1_ha1588_comp_avalon_slave_end_xfer;
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output [ 7: 0] ha1588_comp_avalon_slave_address;
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output ha1588_comp_avalon_slave_read;
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output [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa;
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output ha1588_comp_avalon_slave_reset;
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output ha1588_comp_avalon_slave_write;
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output [ 31: 0] ha1588_comp_avalon_slave_writedata;
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output master_bfm_granted_ha1588_comp_avalon_slave;
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output master_bfm_qualified_request_ha1588_comp_avalon_slave;
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output master_bfm_read_data_valid_ha1588_comp_avalon_slave;
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output master_bfm_requests_ha1588_comp_avalon_slave;
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input clk;
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input [ 31: 0] ha1588_comp_avalon_slave_readdata;
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input master_bfm_latency_counter;
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input [ 15: 0] master_bfm_m0_address_to_slave;
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input master_bfm_m0_read;
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input master_bfm_m0_write;
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input [ 31: 0] master_bfm_m0_writedata;
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input reset_n;
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reg d1_ha1588_comp_avalon_slave_end_xfer;
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reg d1_reasons_to_wait;
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reg enable_nonzero_assertions;
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wire end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave;
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wire [ 7: 0] ha1588_comp_avalon_slave_address;
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wire ha1588_comp_avalon_slave_allgrants;
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wire ha1588_comp_avalon_slave_allow_new_arb_cycle;
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wire ha1588_comp_avalon_slave_any_bursting_master_saved_grant;
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wire ha1588_comp_avalon_slave_any_continuerequest;
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wire ha1588_comp_avalon_slave_arb_counter_enable;
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reg ha1588_comp_avalon_slave_arb_share_counter;
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wire ha1588_comp_avalon_slave_arb_share_counter_next_value;
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wire ha1588_comp_avalon_slave_arb_share_set_values;
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wire ha1588_comp_avalon_slave_beginbursttransfer_internal;
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wire ha1588_comp_avalon_slave_begins_xfer;
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wire ha1588_comp_avalon_slave_end_xfer;
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wire ha1588_comp_avalon_slave_firsttransfer;
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wire ha1588_comp_avalon_slave_grant_vector;
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wire ha1588_comp_avalon_slave_in_a_read_cycle;
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wire ha1588_comp_avalon_slave_in_a_write_cycle;
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wire ha1588_comp_avalon_slave_master_qreq_vector;
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wire ha1588_comp_avalon_slave_non_bursting_master_requests;
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wire ha1588_comp_avalon_slave_read;
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wire [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa;
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reg ha1588_comp_avalon_slave_reg_firsttransfer;
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wire ha1588_comp_avalon_slave_reset;
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reg ha1588_comp_avalon_slave_slavearbiterlockenable;
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wire ha1588_comp_avalon_slave_slavearbiterlockenable2;
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wire ha1588_comp_avalon_slave_unreg_firsttransfer;
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wire ha1588_comp_avalon_slave_waits_for_read;
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wire ha1588_comp_avalon_slave_waits_for_write;
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wire ha1588_comp_avalon_slave_write;
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wire [ 31: 0] ha1588_comp_avalon_slave_writedata;
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wire in_a_read_cycle;
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wire in_a_write_cycle;
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wire master_bfm_granted_ha1588_comp_avalon_slave;
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wire master_bfm_m0_arbiterlock;
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wire master_bfm_m0_arbiterlock2;
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wire master_bfm_m0_continuerequest;
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wire master_bfm_qualified_request_ha1588_comp_avalon_slave;
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wire master_bfm_read_data_valid_ha1588_comp_avalon_slave;
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wire master_bfm_requests_ha1588_comp_avalon_slave;
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wire master_bfm_saved_grant_ha1588_comp_avalon_slave;
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wire [ 15: 0] shifted_address_to_ha1588_comp_avalon_slave_from_master_bfm_m0;
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wire wait_for_ha1588_comp_avalon_slave_counter;
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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d1_reasons_to_wait <= 0;
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else
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d1_reasons_to_wait <= ~ha1588_comp_avalon_slave_end_xfer;
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end
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assign ha1588_comp_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((master_bfm_qualified_request_ha1588_comp_avalon_slave));
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//assign ha1588_comp_avalon_slave_readdata_from_sa = ha1588_comp_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
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assign ha1588_comp_avalon_slave_readdata_from_sa = ha1588_comp_avalon_slave_readdata;
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assign master_bfm_requests_ha1588_comp_avalon_slave = ({master_bfm_m0_address_to_slave[15 : 10] , 10'b0} == 16'h0) & (master_bfm_m0_read | master_bfm_m0_write);
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//ha1588_comp_avalon_slave_arb_share_counter set values, which is an e_mux
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assign ha1588_comp_avalon_slave_arb_share_set_values = 1;
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//ha1588_comp_avalon_slave_non_bursting_master_requests mux, which is an e_mux
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assign ha1588_comp_avalon_slave_non_bursting_master_requests = master_bfm_requests_ha1588_comp_avalon_slave;
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//ha1588_comp_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
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assign ha1588_comp_avalon_slave_any_bursting_master_saved_grant = 0;
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//ha1588_comp_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
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assign ha1588_comp_avalon_slave_arb_share_counter_next_value = ha1588_comp_avalon_slave_firsttransfer ? (ha1588_comp_avalon_slave_arb_share_set_values - 1) : |ha1588_comp_avalon_slave_arb_share_counter ? (ha1588_comp_avalon_slave_arb_share_counter - 1) : 0;
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//ha1588_comp_avalon_slave_allgrants all slave grants, which is an e_mux
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assign ha1588_comp_avalon_slave_allgrants = |ha1588_comp_avalon_slave_grant_vector;
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//ha1588_comp_avalon_slave_end_xfer assignment, which is an e_assign
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assign ha1588_comp_avalon_slave_end_xfer = ~(ha1588_comp_avalon_slave_waits_for_read | ha1588_comp_avalon_slave_waits_for_write);
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//end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave arb share counter enable term, which is an e_assign
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assign end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave = ha1588_comp_avalon_slave_end_xfer & (~ha1588_comp_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
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//ha1588_comp_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
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assign ha1588_comp_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave & ha1588_comp_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave & ~ha1588_comp_avalon_slave_non_bursting_master_requests);
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//ha1588_comp_avalon_slave_arb_share_counter counter, which is an e_register
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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ha1588_comp_avalon_slave_arb_share_counter <= 0;
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else if (ha1588_comp_avalon_slave_arb_counter_enable)
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ha1588_comp_avalon_slave_arb_share_counter <= ha1588_comp_avalon_slave_arb_share_counter_next_value;
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end
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//ha1588_comp_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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ha1588_comp_avalon_slave_slavearbiterlockenable <= 0;
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else if ((|ha1588_comp_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave) | (end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave & ~ha1588_comp_avalon_slave_non_bursting_master_requests))
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ha1588_comp_avalon_slave_slavearbiterlockenable <= |ha1588_comp_avalon_slave_arb_share_counter_next_value;
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end
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//master_bfm/m0 ha1588_comp/avalon_slave arbiterlock, which is an e_assign
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assign master_bfm_m0_arbiterlock = ha1588_comp_avalon_slave_slavearbiterlockenable & master_bfm_m0_continuerequest;
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//ha1588_comp_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
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assign ha1588_comp_avalon_slave_slavearbiterlockenable2 = |ha1588_comp_avalon_slave_arb_share_counter_next_value;
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//master_bfm/m0 ha1588_comp/avalon_slave arbiterlock2, which is an e_assign
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assign master_bfm_m0_arbiterlock2 = ha1588_comp_avalon_slave_slavearbiterlockenable2 & master_bfm_m0_continuerequest;
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//ha1588_comp_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_assign
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assign ha1588_comp_avalon_slave_any_continuerequest = 1;
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//master_bfm_m0_continuerequest continued request, which is an e_assign
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assign master_bfm_m0_continuerequest = 1;
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assign master_bfm_qualified_request_ha1588_comp_avalon_slave = master_bfm_requests_ha1588_comp_avalon_slave & ~((master_bfm_m0_read & ((master_bfm_latency_counter != 0))));
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//local readdatavalid master_bfm_read_data_valid_ha1588_comp_avalon_slave, which is an e_mux
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assign master_bfm_read_data_valid_ha1588_comp_avalon_slave = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_read & ~ha1588_comp_avalon_slave_waits_for_read;
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//ha1588_comp_avalon_slave_writedata mux, which is an e_mux
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assign ha1588_comp_avalon_slave_writedata = master_bfm_m0_writedata;
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//master is always granted when requested
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assign master_bfm_granted_ha1588_comp_avalon_slave = master_bfm_qualified_request_ha1588_comp_avalon_slave;
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//master_bfm/m0 saved-grant ha1588_comp/avalon_slave, which is an e_assign
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assign master_bfm_saved_grant_ha1588_comp_avalon_slave = master_bfm_requests_ha1588_comp_avalon_slave;
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//allow new arb cycle for ha1588_comp/avalon_slave, which is an e_assign
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assign ha1588_comp_avalon_slave_allow_new_arb_cycle = 1;
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//placeholder chosen master
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assign ha1588_comp_avalon_slave_grant_vector = 1;
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//placeholder vector of master qualified-requests
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assign ha1588_comp_avalon_slave_master_qreq_vector = 1;
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//~ha1588_comp_avalon_slave_reset assignment, which is an e_assign
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assign ha1588_comp_avalon_slave_reset = ~reset_n;
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//ha1588_comp_avalon_slave_firsttransfer first transaction, which is an e_assign
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assign ha1588_comp_avalon_slave_firsttransfer = ha1588_comp_avalon_slave_begins_xfer ? ha1588_comp_avalon_slave_unreg_firsttransfer : ha1588_comp_avalon_slave_reg_firsttransfer;
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//ha1588_comp_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
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assign ha1588_comp_avalon_slave_unreg_firsttransfer = ~(ha1588_comp_avalon_slave_slavearbiterlockenable & ha1588_comp_avalon_slave_any_continuerequest);
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//ha1588_comp_avalon_slave_reg_firsttransfer first transaction, which is an e_register
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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ha1588_comp_avalon_slave_reg_firsttransfer <= 1'b1;
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else if (ha1588_comp_avalon_slave_begins_xfer)
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ha1588_comp_avalon_slave_reg_firsttransfer <= ha1588_comp_avalon_slave_unreg_firsttransfer;
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end
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//ha1588_comp_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
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assign ha1588_comp_avalon_slave_beginbursttransfer_internal = ha1588_comp_avalon_slave_begins_xfer;
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//ha1588_comp_avalon_slave_read assignment, which is an e_mux
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assign ha1588_comp_avalon_slave_read = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_read;
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//ha1588_comp_avalon_slave_write assignment, which is an e_mux
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assign ha1588_comp_avalon_slave_write = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_write;
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assign shifted_address_to_ha1588_comp_avalon_slave_from_master_bfm_m0 = master_bfm_m0_address_to_slave;
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//ha1588_comp_avalon_slave_address mux, which is an e_mux
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assign ha1588_comp_avalon_slave_address = shifted_address_to_ha1588_comp_avalon_slave_from_master_bfm_m0 >> 2;
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//d1_ha1588_comp_avalon_slave_end_xfer register, which is an e_register
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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d1_ha1588_comp_avalon_slave_end_xfer <= 1;
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else
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d1_ha1588_comp_avalon_slave_end_xfer <= ha1588_comp_avalon_slave_end_xfer;
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end
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//ha1588_comp_avalon_slave_waits_for_read in a cycle, which is an e_mux
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assign ha1588_comp_avalon_slave_waits_for_read = ha1588_comp_avalon_slave_in_a_read_cycle & ha1588_comp_avalon_slave_begins_xfer;
|
256 |
|
|
|
257 |
|
|
//ha1588_comp_avalon_slave_in_a_read_cycle assignment, which is an e_assign
|
258 |
|
|
assign ha1588_comp_avalon_slave_in_a_read_cycle = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_read;
|
259 |
|
|
|
260 |
|
|
//in_a_read_cycle assignment, which is an e_mux
|
261 |
|
|
assign in_a_read_cycle = ha1588_comp_avalon_slave_in_a_read_cycle;
|
262 |
|
|
|
263 |
|
|
//ha1588_comp_avalon_slave_waits_for_write in a cycle, which is an e_mux
|
264 |
|
|
assign ha1588_comp_avalon_slave_waits_for_write = ha1588_comp_avalon_slave_in_a_write_cycle & 0;
|
265 |
|
|
|
266 |
|
|
//ha1588_comp_avalon_slave_in_a_write_cycle assignment, which is an e_assign
|
267 |
|
|
assign ha1588_comp_avalon_slave_in_a_write_cycle = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_write;
|
268 |
|
|
|
269 |
|
|
//in_a_write_cycle assignment, which is an e_mux
|
270 |
|
|
assign in_a_write_cycle = ha1588_comp_avalon_slave_in_a_write_cycle;
|
271 |
|
|
|
272 |
|
|
assign wait_for_ha1588_comp_avalon_slave_counter = 0;
|
273 |
|
|
|
274 |
|
|
//synthesis translate_off
|
275 |
|
|
//////////////// SIMULATION-ONLY CONTENTS
|
276 |
|
|
//ha1588_comp/avalon_slave enable non-zero assertions, which is an e_register
|
277 |
|
|
always @(posedge clk or negedge reset_n)
|
278 |
|
|
begin
|
279 |
|
|
if (reset_n == 0)
|
280 |
|
|
enable_nonzero_assertions <= 0;
|
281 |
|
|
else
|
282 |
|
|
enable_nonzero_assertions <= 1'b1;
|
283 |
|
|
end
|
284 |
|
|
|
285 |
|
|
|
286 |
|
|
|
287 |
|
|
//////////////// END SIMULATION-ONLY CONTENTS
|
288 |
|
|
|
289 |
|
|
//synthesis translate_on
|
290 |
|
|
|
291 |
|
|
endmodule
|
292 |
|
|
|
293 |
|
|
|
294 |
|
|
|
295 |
|
|
// turn off superfluous verilog processor warnings
|
296 |
|
|
// altera message_level Level1
|
297 |
|
|
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
298 |
|
|
|
299 |
|
|
module master_bfm_m0_arbitrator (
|
300 |
|
|
// inputs:
|
301 |
|
|
clk,
|
302 |
|
|
d1_ha1588_comp_avalon_slave_end_xfer,
|
303 |
|
|
ha1588_comp_avalon_slave_readdata_from_sa,
|
304 |
|
|
master_bfm_granted_ha1588_comp_avalon_slave,
|
305 |
|
|
master_bfm_m0_address,
|
306 |
|
|
master_bfm_m0_read,
|
307 |
|
|
master_bfm_m0_write,
|
308 |
|
|
master_bfm_m0_writedata,
|
309 |
|
|
master_bfm_qualified_request_ha1588_comp_avalon_slave,
|
310 |
|
|
master_bfm_read_data_valid_ha1588_comp_avalon_slave,
|
311 |
|
|
master_bfm_requests_ha1588_comp_avalon_slave,
|
312 |
|
|
reset_n,
|
313 |
|
|
|
314 |
|
|
// outputs:
|
315 |
|
|
master_bfm_latency_counter,
|
316 |
|
|
master_bfm_m0_address_to_slave,
|
317 |
|
|
master_bfm_m0_readdata,
|
318 |
|
|
master_bfm_m0_readdatavalid,
|
319 |
|
|
master_bfm_m0_reset,
|
320 |
|
|
master_bfm_m0_waitrequest
|
321 |
|
|
)
|
322 |
|
|
;
|
323 |
|
|
|
324 |
|
|
output master_bfm_latency_counter;
|
325 |
|
|
output [ 15: 0] master_bfm_m0_address_to_slave;
|
326 |
|
|
output [ 31: 0] master_bfm_m0_readdata;
|
327 |
|
|
output master_bfm_m0_readdatavalid;
|
328 |
|
|
output master_bfm_m0_reset;
|
329 |
|
|
output master_bfm_m0_waitrequest;
|
330 |
|
|
input clk;
|
331 |
|
|
input d1_ha1588_comp_avalon_slave_end_xfer;
|
332 |
|
|
input [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa;
|
333 |
|
|
input master_bfm_granted_ha1588_comp_avalon_slave;
|
334 |
|
|
input [ 15: 0] master_bfm_m0_address;
|
335 |
|
|
input master_bfm_m0_read;
|
336 |
|
|
input master_bfm_m0_write;
|
337 |
|
|
input [ 31: 0] master_bfm_m0_writedata;
|
338 |
|
|
input master_bfm_qualified_request_ha1588_comp_avalon_slave;
|
339 |
|
|
input master_bfm_read_data_valid_ha1588_comp_avalon_slave;
|
340 |
|
|
input master_bfm_requests_ha1588_comp_avalon_slave;
|
341 |
|
|
input reset_n;
|
342 |
|
|
|
343 |
|
|
reg active_and_waiting_last_time;
|
344 |
|
|
wire master_bfm_latency_counter;
|
345 |
|
|
reg [ 15: 0] master_bfm_m0_address_last_time;
|
346 |
|
|
wire [ 15: 0] master_bfm_m0_address_to_slave;
|
347 |
|
|
reg master_bfm_m0_read_last_time;
|
348 |
|
|
wire [ 31: 0] master_bfm_m0_readdata;
|
349 |
|
|
wire master_bfm_m0_readdatavalid;
|
350 |
|
|
wire master_bfm_m0_reset;
|
351 |
|
|
wire master_bfm_m0_run;
|
352 |
|
|
wire master_bfm_m0_waitrequest;
|
353 |
|
|
reg master_bfm_m0_write_last_time;
|
354 |
|
|
reg [ 31: 0] master_bfm_m0_writedata_last_time;
|
355 |
|
|
wire pre_flush_master_bfm_m0_readdatavalid;
|
356 |
|
|
wire r_0;
|
357 |
|
|
//r_0 master_run cascaded wait assignment, which is an e_assign
|
358 |
|
|
assign r_0 = 1 & (master_bfm_qualified_request_ha1588_comp_avalon_slave | ~master_bfm_requests_ha1588_comp_avalon_slave) & ((~master_bfm_qualified_request_ha1588_comp_avalon_slave | ~master_bfm_m0_read | (1 & ~d1_ha1588_comp_avalon_slave_end_xfer & master_bfm_m0_read))) & ((~master_bfm_qualified_request_ha1588_comp_avalon_slave | ~master_bfm_m0_write | (1 & master_bfm_m0_write)));
|
359 |
|
|
|
360 |
|
|
//cascaded wait assignment, which is an e_assign
|
361 |
|
|
assign master_bfm_m0_run = r_0;
|
362 |
|
|
|
363 |
|
|
//optimize select-logic by passing only those address bits which matter.
|
364 |
|
|
assign master_bfm_m0_address_to_slave = {6'b0,
|
365 |
|
|
master_bfm_m0_address[9 : 0]};
|
366 |
|
|
|
367 |
|
|
//latent slave read data valids which may be flushed, which is an e_mux
|
368 |
|
|
assign pre_flush_master_bfm_m0_readdatavalid = 0;
|
369 |
|
|
|
370 |
|
|
//latent slave read data valid which is not flushed, which is an e_mux
|
371 |
|
|
assign master_bfm_m0_readdatavalid = 0 |
|
372 |
|
|
pre_flush_master_bfm_m0_readdatavalid |
|
373 |
|
|
master_bfm_read_data_valid_ha1588_comp_avalon_slave;
|
374 |
|
|
|
375 |
|
|
//master_bfm/m0 readdata mux, which is an e_mux
|
376 |
|
|
assign master_bfm_m0_readdata = ha1588_comp_avalon_slave_readdata_from_sa;
|
377 |
|
|
|
378 |
|
|
//actual waitrequest port, which is an e_assign
|
379 |
|
|
assign master_bfm_m0_waitrequest = ~master_bfm_m0_run;
|
380 |
|
|
|
381 |
|
|
//latent max counter, which is an e_assign
|
382 |
|
|
assign master_bfm_latency_counter = 0;
|
383 |
|
|
|
384 |
|
|
//~master_bfm_m0_reset assignment, which is an e_assign
|
385 |
|
|
assign master_bfm_m0_reset = ~reset_n;
|
386 |
|
|
|
387 |
|
|
|
388 |
|
|
//synthesis translate_off
|
389 |
|
|
//////////////// SIMULATION-ONLY CONTENTS
|
390 |
|
|
//master_bfm_m0_address check against wait, which is an e_register
|
391 |
|
|
always @(posedge clk or negedge reset_n)
|
392 |
|
|
begin
|
393 |
|
|
if (reset_n == 0)
|
394 |
|
|
master_bfm_m0_address_last_time <= 0;
|
395 |
|
|
else
|
396 |
|
|
master_bfm_m0_address_last_time <= master_bfm_m0_address;
|
397 |
|
|
end
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
//master_bfm/m0 waited last time, which is an e_register
|
401 |
|
|
always @(posedge clk or negedge reset_n)
|
402 |
|
|
begin
|
403 |
|
|
if (reset_n == 0)
|
404 |
|
|
active_and_waiting_last_time <= 0;
|
405 |
|
|
else
|
406 |
|
|
active_and_waiting_last_time <= master_bfm_m0_waitrequest & (master_bfm_m0_read | master_bfm_m0_write);
|
407 |
|
|
end
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
//master_bfm_m0_address matches last port_name, which is an e_process
|
411 |
|
|
always @(posedge clk)
|
412 |
|
|
begin
|
413 |
|
|
if (active_and_waiting_last_time & (master_bfm_m0_address != master_bfm_m0_address_last_time))
|
414 |
|
|
begin
|
415 |
|
|
$write("%0d ns: master_bfm_m0_address did not heed wait!!!", $time);
|
416 |
|
|
$stop;
|
417 |
|
|
end
|
418 |
|
|
end
|
419 |
|
|
|
420 |
|
|
|
421 |
|
|
//master_bfm_m0_read check against wait, which is an e_register
|
422 |
|
|
always @(posedge clk or negedge reset_n)
|
423 |
|
|
begin
|
424 |
|
|
if (reset_n == 0)
|
425 |
|
|
master_bfm_m0_read_last_time <= 0;
|
426 |
|
|
else
|
427 |
|
|
master_bfm_m0_read_last_time <= master_bfm_m0_read;
|
428 |
|
|
end
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
//master_bfm_m0_read matches last port_name, which is an e_process
|
432 |
|
|
always @(posedge clk)
|
433 |
|
|
begin
|
434 |
|
|
if (active_and_waiting_last_time & (master_bfm_m0_read != master_bfm_m0_read_last_time))
|
435 |
|
|
begin
|
436 |
|
|
$write("%0d ns: master_bfm_m0_read did not heed wait!!!", $time);
|
437 |
|
|
$stop;
|
438 |
|
|
end
|
439 |
|
|
end
|
440 |
|
|
|
441 |
|
|
|
442 |
|
|
//master_bfm_m0_write check against wait, which is an e_register
|
443 |
|
|
always @(posedge clk or negedge reset_n)
|
444 |
|
|
begin
|
445 |
|
|
if (reset_n == 0)
|
446 |
|
|
master_bfm_m0_write_last_time <= 0;
|
447 |
|
|
else
|
448 |
|
|
master_bfm_m0_write_last_time <= master_bfm_m0_write;
|
449 |
|
|
end
|
450 |
|
|
|
451 |
|
|
|
452 |
|
|
//master_bfm_m0_write matches last port_name, which is an e_process
|
453 |
|
|
always @(posedge clk)
|
454 |
|
|
begin
|
455 |
|
|
if (active_and_waiting_last_time & (master_bfm_m0_write != master_bfm_m0_write_last_time))
|
456 |
|
|
begin
|
457 |
|
|
$write("%0d ns: master_bfm_m0_write did not heed wait!!!", $time);
|
458 |
|
|
$stop;
|
459 |
|
|
end
|
460 |
|
|
end
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
//master_bfm_m0_writedata check against wait, which is an e_register
|
464 |
|
|
always @(posedge clk or negedge reset_n)
|
465 |
|
|
begin
|
466 |
|
|
if (reset_n == 0)
|
467 |
|
|
master_bfm_m0_writedata_last_time <= 0;
|
468 |
|
|
else
|
469 |
|
|
master_bfm_m0_writedata_last_time <= master_bfm_m0_writedata;
|
470 |
|
|
end
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
//master_bfm_m0_writedata matches last port_name, which is an e_process
|
474 |
|
|
always @(posedge clk)
|
475 |
|
|
begin
|
476 |
|
|
if (active_and_waiting_last_time & (master_bfm_m0_writedata != master_bfm_m0_writedata_last_time) & master_bfm_m0_write)
|
477 |
|
|
begin
|
478 |
|
|
$write("%0d ns: master_bfm_m0_writedata did not heed wait!!!", $time);
|
479 |
|
|
$stop;
|
480 |
|
|
end
|
481 |
|
|
end
|
482 |
|
|
|
483 |
|
|
|
484 |
|
|
|
485 |
|
|
//////////////// END SIMULATION-ONLY CONTENTS
|
486 |
|
|
|
487 |
|
|
//synthesis translate_on
|
488 |
|
|
|
489 |
|
|
endmodule
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
// turn off superfluous verilog processor warnings
|
494 |
|
|
// altera message_level Level1
|
495 |
|
|
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
496 |
|
|
|
497 |
|
|
module ha1588_inst_reset_clk_0_domain_synch_module (
|
498 |
|
|
// inputs:
|
499 |
|
|
clk,
|
500 |
|
|
data_in,
|
501 |
|
|
reset_n,
|
502 |
|
|
|
503 |
|
|
// outputs:
|
504 |
|
|
data_out
|
505 |
|
|
)
|
506 |
|
|
;
|
507 |
|
|
|
508 |
|
|
output data_out;
|
509 |
|
|
input clk;
|
510 |
|
|
input data_in;
|
511 |
|
|
input reset_n;
|
512 |
|
|
|
513 |
|
|
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
|
514 |
|
|
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
|
515 |
|
|
always @(posedge clk or negedge reset_n)
|
516 |
|
|
begin
|
517 |
|
|
if (reset_n == 0)
|
518 |
|
|
data_in_d1 <= 0;
|
519 |
|
|
else
|
520 |
|
|
data_in_d1 <= data_in;
|
521 |
|
|
end
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
always @(posedge clk or negedge reset_n)
|
525 |
|
|
begin
|
526 |
|
|
if (reset_n == 0)
|
527 |
|
|
data_out <= 0;
|
528 |
|
|
else
|
529 |
|
|
data_out <= data_in_d1;
|
530 |
|
|
end
|
531 |
|
|
|
532 |
|
|
|
533 |
|
|
|
534 |
|
|
endmodule
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
|
538 |
|
|
// turn off superfluous verilog processor warnings
|
539 |
|
|
// altera message_level Level1
|
540 |
|
|
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
541 |
|
|
|
542 |
|
|
module ha1588_inst (
|
543 |
|
|
// 1) global signals:
|
544 |
|
|
clk_0,
|
545 |
|
|
reset_n,
|
546 |
|
|
|
547 |
|
|
// the_ha1588_comp
|
548 |
|
|
rtc_clk_to_the_ha1588_comp,
|
549 |
|
|
rtc_time_ptp_ns_from_the_ha1588_comp,
|
550 |
|
|
rtc_time_ptp_sec_from_the_ha1588_comp,
|
551 |
|
|
rx_gmii_clk_to_the_ha1588_comp,
|
552 |
|
|
rx_gmii_ctrl_to_the_ha1588_comp,
|
553 |
|
|
rx_gmii_data_to_the_ha1588_comp,
|
554 |
|
|
tx_gmii_clk_to_the_ha1588_comp,
|
555 |
|
|
tx_gmii_ctrl_to_the_ha1588_comp,
|
556 |
|
|
tx_gmii_data_to_the_ha1588_comp
|
557 |
|
|
)
|
558 |
|
|
;
|
559 |
|
|
|
560 |
|
|
output [ 31: 0] rtc_time_ptp_ns_from_the_ha1588_comp;
|
561 |
|
|
output [ 47: 0] rtc_time_ptp_sec_from_the_ha1588_comp;
|
562 |
|
|
input clk_0;
|
563 |
|
|
input reset_n;
|
564 |
|
|
input rtc_clk_to_the_ha1588_comp;
|
565 |
|
|
input rx_gmii_clk_to_the_ha1588_comp;
|
566 |
|
|
input rx_gmii_ctrl_to_the_ha1588_comp;
|
567 |
|
|
input [ 7: 0] rx_gmii_data_to_the_ha1588_comp;
|
568 |
|
|
input tx_gmii_clk_to_the_ha1588_comp;
|
569 |
|
|
input tx_gmii_ctrl_to_the_ha1588_comp;
|
570 |
|
|
input [ 7: 0] tx_gmii_data_to_the_ha1588_comp;
|
571 |
|
|
|
572 |
|
|
wire clk_0_reset_n;
|
573 |
|
|
wire d1_ha1588_comp_avalon_slave_end_xfer;
|
574 |
|
|
wire [ 7: 0] ha1588_comp_avalon_slave_address;
|
575 |
|
|
wire ha1588_comp_avalon_slave_read;
|
576 |
|
|
wire [ 31: 0] ha1588_comp_avalon_slave_readdata;
|
577 |
|
|
wire [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa;
|
578 |
|
|
wire ha1588_comp_avalon_slave_reset;
|
579 |
|
|
wire ha1588_comp_avalon_slave_write;
|
580 |
|
|
wire [ 31: 0] ha1588_comp_avalon_slave_writedata;
|
581 |
|
|
wire master_bfm_granted_ha1588_comp_avalon_slave;
|
582 |
|
|
wire master_bfm_latency_counter;
|
583 |
|
|
wire [ 15: 0] master_bfm_m0_address;
|
584 |
|
|
wire [ 15: 0] master_bfm_m0_address_to_slave;
|
585 |
|
|
wire master_bfm_m0_read;
|
586 |
|
|
wire [ 31: 0] master_bfm_m0_readdata;
|
587 |
|
|
wire master_bfm_m0_readdatavalid;
|
588 |
|
|
wire master_bfm_m0_reset;
|
589 |
|
|
wire master_bfm_m0_waitrequest;
|
590 |
|
|
wire master_bfm_m0_write;
|
591 |
|
|
wire [ 31: 0] master_bfm_m0_writedata;
|
592 |
|
|
wire master_bfm_qualified_request_ha1588_comp_avalon_slave;
|
593 |
|
|
wire master_bfm_read_data_valid_ha1588_comp_avalon_slave;
|
594 |
|
|
wire master_bfm_requests_ha1588_comp_avalon_slave;
|
595 |
|
|
wire reset_n_sources;
|
596 |
|
|
wire [ 31: 0] rtc_time_ptp_ns_from_the_ha1588_comp;
|
597 |
|
|
wire [ 47: 0] rtc_time_ptp_sec_from_the_ha1588_comp;
|
598 |
|
|
ha1588_comp_avalon_slave_arbitrator the_ha1588_comp_avalon_slave
|
599 |
|
|
(
|
600 |
|
|
.clk (clk_0),
|
601 |
|
|
.d1_ha1588_comp_avalon_slave_end_xfer (d1_ha1588_comp_avalon_slave_end_xfer),
|
602 |
|
|
.ha1588_comp_avalon_slave_address (ha1588_comp_avalon_slave_address),
|
603 |
|
|
.ha1588_comp_avalon_slave_read (ha1588_comp_avalon_slave_read),
|
604 |
|
|
.ha1588_comp_avalon_slave_readdata (ha1588_comp_avalon_slave_readdata),
|
605 |
|
|
.ha1588_comp_avalon_slave_readdata_from_sa (ha1588_comp_avalon_slave_readdata_from_sa),
|
606 |
|
|
.ha1588_comp_avalon_slave_reset (ha1588_comp_avalon_slave_reset),
|
607 |
|
|
.ha1588_comp_avalon_slave_write (ha1588_comp_avalon_slave_write),
|
608 |
|
|
.ha1588_comp_avalon_slave_writedata (ha1588_comp_avalon_slave_writedata),
|
609 |
|
|
.master_bfm_granted_ha1588_comp_avalon_slave (master_bfm_granted_ha1588_comp_avalon_slave),
|
610 |
|
|
.master_bfm_latency_counter (master_bfm_latency_counter),
|
611 |
|
|
.master_bfm_m0_address_to_slave (master_bfm_m0_address_to_slave),
|
612 |
|
|
.master_bfm_m0_read (master_bfm_m0_read),
|
613 |
|
|
.master_bfm_m0_write (master_bfm_m0_write),
|
614 |
|
|
.master_bfm_m0_writedata (master_bfm_m0_writedata),
|
615 |
|
|
.master_bfm_qualified_request_ha1588_comp_avalon_slave (master_bfm_qualified_request_ha1588_comp_avalon_slave),
|
616 |
|
|
.master_bfm_read_data_valid_ha1588_comp_avalon_slave (master_bfm_read_data_valid_ha1588_comp_avalon_slave),
|
617 |
|
|
.master_bfm_requests_ha1588_comp_avalon_slave (master_bfm_requests_ha1588_comp_avalon_slave),
|
618 |
|
|
.reset_n (clk_0_reset_n)
|
619 |
|
|
);
|
620 |
|
|
|
621 |
|
|
ha1588_comp the_ha1588_comp
|
622 |
|
|
(
|
623 |
|
|
.addr_in (ha1588_comp_avalon_slave_address),
|
624 |
|
|
.clk (clk_0),
|
625 |
|
|
.data_in (ha1588_comp_avalon_slave_writedata),
|
626 |
|
|
.data_out (ha1588_comp_avalon_slave_readdata),
|
627 |
|
|
.rd_in (ha1588_comp_avalon_slave_read),
|
628 |
|
|
.rst (ha1588_comp_avalon_slave_reset),
|
629 |
|
|
.rtc_clk (rtc_clk_to_the_ha1588_comp),
|
630 |
|
|
.rtc_time_ptp_ns (rtc_time_ptp_ns_from_the_ha1588_comp),
|
631 |
|
|
.rtc_time_ptp_sec (rtc_time_ptp_sec_from_the_ha1588_comp),
|
632 |
|
|
.rx_gmii_clk (rx_gmii_clk_to_the_ha1588_comp),
|
633 |
|
|
.rx_gmii_ctrl (rx_gmii_ctrl_to_the_ha1588_comp),
|
634 |
|
|
.rx_gmii_data (rx_gmii_data_to_the_ha1588_comp),
|
635 |
|
|
.tx_gmii_clk (tx_gmii_clk_to_the_ha1588_comp),
|
636 |
|
|
.tx_gmii_ctrl (tx_gmii_ctrl_to_the_ha1588_comp),
|
637 |
|
|
.tx_gmii_data (tx_gmii_data_to_the_ha1588_comp),
|
638 |
|
|
.wr_in (ha1588_comp_avalon_slave_write)
|
639 |
|
|
);
|
640 |
|
|
|
641 |
|
|
master_bfm_m0_arbitrator the_master_bfm_m0
|
642 |
|
|
(
|
643 |
|
|
.clk (clk_0),
|
644 |
|
|
.d1_ha1588_comp_avalon_slave_end_xfer (d1_ha1588_comp_avalon_slave_end_xfer),
|
645 |
|
|
.ha1588_comp_avalon_slave_readdata_from_sa (ha1588_comp_avalon_slave_readdata_from_sa),
|
646 |
|
|
.master_bfm_granted_ha1588_comp_avalon_slave (master_bfm_granted_ha1588_comp_avalon_slave),
|
647 |
|
|
.master_bfm_latency_counter (master_bfm_latency_counter),
|
648 |
|
|
.master_bfm_m0_address (master_bfm_m0_address),
|
649 |
|
|
.master_bfm_m0_address_to_slave (master_bfm_m0_address_to_slave),
|
650 |
|
|
.master_bfm_m0_read (master_bfm_m0_read),
|
651 |
|
|
.master_bfm_m0_readdata (master_bfm_m0_readdata),
|
652 |
|
|
.master_bfm_m0_readdatavalid (master_bfm_m0_readdatavalid),
|
653 |
|
|
.master_bfm_m0_reset (master_bfm_m0_reset),
|
654 |
|
|
.master_bfm_m0_waitrequest (master_bfm_m0_waitrequest),
|
655 |
|
|
.master_bfm_m0_write (master_bfm_m0_write),
|
656 |
|
|
.master_bfm_m0_writedata (master_bfm_m0_writedata),
|
657 |
|
|
.master_bfm_qualified_request_ha1588_comp_avalon_slave (master_bfm_qualified_request_ha1588_comp_avalon_slave),
|
658 |
|
|
.master_bfm_read_data_valid_ha1588_comp_avalon_slave (master_bfm_read_data_valid_ha1588_comp_avalon_slave),
|
659 |
|
|
.master_bfm_requests_ha1588_comp_avalon_slave (master_bfm_requests_ha1588_comp_avalon_slave),
|
660 |
|
|
.reset_n (clk_0_reset_n)
|
661 |
|
|
);
|
662 |
|
|
|
663 |
|
|
master_bfm the_master_bfm
|
664 |
|
|
(
|
665 |
|
|
.avm_address (master_bfm_m0_address),
|
666 |
|
|
.avm_read (master_bfm_m0_read),
|
667 |
|
|
.avm_readdata (master_bfm_m0_readdata),
|
668 |
|
|
.avm_readdatavalid (master_bfm_m0_readdatavalid),
|
669 |
|
|
.avm_waitrequest (master_bfm_m0_waitrequest),
|
670 |
|
|
.avm_write (master_bfm_m0_write),
|
671 |
|
|
.avm_writedata (master_bfm_m0_writedata),
|
672 |
|
|
.clk (clk_0),
|
673 |
|
|
.reset (master_bfm_m0_reset)
|
674 |
|
|
);
|
675 |
|
|
|
676 |
|
|
//reset is asserted asynchronously and deasserted synchronously
|
677 |
|
|
ha1588_inst_reset_clk_0_domain_synch_module ha1588_inst_reset_clk_0_domain_synch
|
678 |
|
|
(
|
679 |
|
|
.clk (clk_0),
|
680 |
|
|
.data_in (1'b1),
|
681 |
|
|
.data_out (clk_0_reset_n),
|
682 |
|
|
.reset_n (reset_n_sources)
|
683 |
|
|
);
|
684 |
|
|
|
685 |
|
|
//reset sources mux, which is an e_mux
|
686 |
|
|
assign reset_n_sources = ~(~reset_n |
|
687 |
|
|
0);
|
688 |
|
|
|
689 |
|
|
|
690 |
|
|
endmodule
|
691 |
|
|
|
692 |
|
|
|
693 |
|
|
//synthesis translate_off
|
694 |
|
|
|
695 |
|
|
|
696 |
|
|
|
697 |
|
|
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
|
698 |
|
|
|
699 |
|
|
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
|
700 |
|
|
|
701 |
|
|
|
702 |
|
|
// If user logic components use Altsync_Ram with convert_hex2ver.dll,
|
703 |
|
|
// set USE_convert_hex2ver in the user comments section above
|
704 |
|
|
|
705 |
|
|
// `ifdef USE_convert_hex2ver
|
706 |
|
|
// `else
|
707 |
|
|
// `define NO_PLI 1
|
708 |
|
|
// `endif
|
709 |
|
|
|
710 |
49 |
edn_walter |
//`include "c:/altera/10.1/quartus/eda/sim_lib/altera_mf.v"
|
711 |
|
|
//`include "c:/altera/10.1/quartus/eda/sim_lib/220model.v"
|
712 |
|
|
//`include "c:/altera/10.1/quartus/eda/sim_lib/sgate.v"
|
713 |
48 |
edn_walter |
// C:/altera/10.1/ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv
|
714 |
|
|
// C:/altera/10.1/ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv
|
715 |
|
|
// C:/altera/10.1/ip/altera/sopc_builder_ip/verification/altera_avalon_mm_master_bfm/altera_avalon_mm_master_bfm.sv
|
716 |
|
|
|
717 |
|
|
`include "../../rtl/sopc/master_bfm.v"
|
718 |
|
|
`include "../../rtl/top/ha1588.v"
|
719 |
|
|
`include "../../rtl/reg/reg.v"
|
720 |
|
|
`include "../../rtl/rtc/rtc.v"
|
721 |
|
|
`include "../../rtl/tsu/tsu.v"
|
722 |
|
|
`include "../../rtl/tsu/ptp_parser.v"
|
723 |
|
|
`include "../../rtl/tsu/ptp_queue.v"
|
724 |
|
|
`include "../../rtl/sopc/ha1588_comp.v"
|
725 |
|
|
|
726 |
|
|
`timescale 1ns / 1ps
|
727 |
|
|
|
728 |
|
|
module test_bench
|
729 |
|
|
;
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
wire clk;
|
733 |
|
|
reg clk_0;
|
734 |
|
|
reg reset_n;
|
735 |
|
|
wire rtc_clk_to_the_ha1588_comp;
|
736 |
|
|
wire [ 31: 0] rtc_time_ptp_ns_from_the_ha1588_comp;
|
737 |
|
|
wire [ 47: 0] rtc_time_ptp_sec_from_the_ha1588_comp;
|
738 |
|
|
wire rx_gmii_clk_to_the_ha1588_comp;
|
739 |
|
|
wire rx_gmii_ctrl_to_the_ha1588_comp;
|
740 |
|
|
wire [ 7: 0] rx_gmii_data_to_the_ha1588_comp;
|
741 |
|
|
wire tx_gmii_clk_to_the_ha1588_comp;
|
742 |
|
|
wire tx_gmii_ctrl_to_the_ha1588_comp;
|
743 |
|
|
wire [ 7: 0] tx_gmii_data_to_the_ha1588_comp;
|
744 |
|
|
|
745 |
|
|
|
746 |
|
|
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
|
747 |
|
|
// add your signals and additional architecture here
|
748 |
|
|
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
|
749 |
|
|
|
750 |
|
|
//Set us up the Dut
|
751 |
|
|
ha1588_inst DUT
|
752 |
|
|
(
|
753 |
|
|
.clk_0 (clk_0),
|
754 |
|
|
.reset_n (reset_n),
|
755 |
|
|
.rtc_clk_to_the_ha1588_comp (rtc_clk_to_the_ha1588_comp),
|
756 |
|
|
.rtc_time_ptp_ns_from_the_ha1588_comp (rtc_time_ptp_ns_from_the_ha1588_comp),
|
757 |
|
|
.rtc_time_ptp_sec_from_the_ha1588_comp (rtc_time_ptp_sec_from_the_ha1588_comp),
|
758 |
|
|
.rx_gmii_clk_to_the_ha1588_comp (rx_gmii_clk_to_the_ha1588_comp),
|
759 |
|
|
.rx_gmii_ctrl_to_the_ha1588_comp (rx_gmii_ctrl_to_the_ha1588_comp),
|
760 |
|
|
.rx_gmii_data_to_the_ha1588_comp (rx_gmii_data_to_the_ha1588_comp),
|
761 |
|
|
.tx_gmii_clk_to_the_ha1588_comp (tx_gmii_clk_to_the_ha1588_comp),
|
762 |
|
|
.tx_gmii_ctrl_to_the_ha1588_comp (tx_gmii_ctrl_to_the_ha1588_comp),
|
763 |
|
|
.tx_gmii_data_to_the_ha1588_comp (tx_gmii_data_to_the_ha1588_comp)
|
764 |
|
|
);
|
765 |
|
|
|
766 |
|
|
initial
|
767 |
|
|
clk_0 = 1'b0;
|
768 |
|
|
always
|
769 |
|
|
#10 clk_0 <= ~clk_0;
|
770 |
|
|
|
771 |
|
|
initial
|
772 |
|
|
begin
|
773 |
|
|
reset_n <= 0;
|
774 |
|
|
#200 reset_n <= 1;
|
775 |
|
|
end
|
776 |
|
|
|
777 |
|
|
endmodule
|
778 |
|
|
|
779 |
|
|
|
780 |
|
|
//synthesis translate_on
|