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edn_walter |
//--------------------------------------------------------------------------
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// master_bfm_tb.v
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// This test bench instantiates a master BFM and an onchip RAM
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// as the slave DUT. The test starts with master BFM writing an
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// amount of data to the slave according to the number of
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// transactions which is defined by user.
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//
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// Next, master BFM starts reading back the data from slave.
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// The read back data is compared with the desired data .
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//
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// The test case is defined in the test_input.v file while the
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// result checking rountine is defined in test_result.v file
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//--------------------------------------------------------------------------
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// console messaging level
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`define VERBOSITY VERBOSITY_INFO
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//BFM hierachy
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`define MSTR_BFM tb.DUT.the_master_bfm.master_bfm
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//test bench parameters
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`define NUM_TRANS 5 //user-defined number of transactions to be performed
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`define INDEX_ZERO 0 //burst cycle with index zero for non-bursting transactions
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// BFM related parameters
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`define AV_ADDRESS_W 16
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`define AV_SYMBOL_W 8
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`define AV_NUMSYMBOLS 4
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// derived parameters
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`define AV_DATA_W (`AV_SYMBOL_W * `AV_NUMSYMBOLS)
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//-----------------------------------------------------------------------------
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// Test Top Level begins here
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//-----------------------------------------------------------------------------
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module master_bfm_tb();
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//importing verbosity and avalon_mm packages
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import verbosity_pkg::*;
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import avalon_mm_pkg::*;
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// instantiate SOPC system module
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test_bench tb();
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//local variables
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Request_t command_request, response_request;
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reg [`AV_ADDRESS_W-1:0] command_addr, response_addr;
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reg [`AV_DATA_W-1:0] command_data, response_data;
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reg [`AV_NUMSYMBOLS-1:0] byte_enable;
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reg [`AV_DATA_W-1:0] idle;
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integer init_latency;
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reg [`AV_DATA_W-1:0] master_scoreboard [$];
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reg [`AV_DATA_W-1:0] expected_data;
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integer failure = 0;
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integer checked = 0;
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event start_test;
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event go_check;
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//initialize the master BFM
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initial
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begin
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set_verbosity(`VERBOSITY);
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`MSTR_BFM.init();
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//wait for reset to de-assert and trigger start_test event
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wait(`MSTR_BFM.reset == 0);
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-> start_test;
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end
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//check responses received by master BFM
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always @(posedge tb.clk_0)
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begin
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while (`MSTR_BFM.get_response_queue_size() > 0)
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begin
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//pop out the response desriptor from queue when queue is not empty
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master_pop_and_get_response(response_request, response_addr, response_data);
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//trigger event to check the response with expected data
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-> go_check;
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end
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end
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//simulation ends here
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//both write and read transactions do have response descriptors, so the number
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//of responses received by master BFM is double of NUM_TRANS
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initial
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begin
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while (checked != (`NUM_TRANS*2))
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@(tb.clk_0);
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//we care only the result for read transactions
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$sformat(message, "%m: Test has completed. %0d pass, %0d fail", ((checked / 2) - failure), failure);
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print(VERBOSITY_INFO, message);
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$stop;
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end
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`include "test_input.v"
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`include "test_result.v"
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//----------------------------------------------------------------------------------
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// tasks
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//----------------------------------------------------------------------------------
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//this task sets the command descriptor for master BFM and push it to the queue
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task master_set_and_push_command;
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input Request_t request;
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input [`AV_ADDRESS_W-1:0] addr;
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input [`AV_DATA_W-1:0] data;
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input [`AV_NUMSYMBOLS-1:0] byte_enable;
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input [`AV_DATA_W-1:0] idle;
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input [31:0] init_latency;
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begin
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`MSTR_BFM.set_command_request(request);
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`MSTR_BFM.set_command_address(addr);
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`MSTR_BFM.set_command_byte_enable(byte_enable,`INDEX_ZERO);
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`MSTR_BFM.set_command_idle(idle, `INDEX_ZERO);
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`MSTR_BFM.set_command_init_latency(init_latency);
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if (request == REQ_WRITE)
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begin
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`MSTR_BFM.set_command_data(data, `INDEX_ZERO);
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end
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`MSTR_BFM.push_command();
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end
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endtask
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//this task pops the response received by master BFM from queue
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task master_pop_and_get_response;
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output Request_t request;
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output [`AV_ADDRESS_W-1:0] addr;
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output [`AV_DATA_W-1:0] data;
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begin
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`MSTR_BFM.pop_response();
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request = Request_t' (`MSTR_BFM.get_response_request());
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addr = `MSTR_BFM.get_response_address();
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data = `MSTR_BFM.get_response_data(`INDEX_ZERO);
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end
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endtask
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endmodule
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