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[/] [ha1588/] [tags/] [v1p2/] [sim/] [sopc/] [test_input.v] - Blame information for rev 48

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Line No. Rev Author Line
1 48 edn_walter
//change this file for different test case
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initial
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begin
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  @ start_test;
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  command_addr = 0;  //write address start from 0x0
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  byte_enable = '1;  //all byte lanes are used
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  idle = 0;  //no idle cycle between each command of the master BFM
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  init_latency = 0;  //the command is launched to Avalon bus with no delay
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  //First write NUM_TRANS of random data to the DUT
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  for (int i = 0; i < `NUM_TRANS; i++)
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  begin
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    command_data = {$random()} % 8;
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        master_scoreboard.push_back(command_data); //make a local copy of the write data
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    master_set_and_push_command(REQ_WRITE, command_addr, command_data, byte_enable, idle, init_latency);
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        command_addr = command_addr + 4;
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  end
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  //Next read back the data
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  command_addr = 0;
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  for (int i = 0; i < `NUM_TRANS; i++)
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  begin
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    master_set_and_push_command(REQ_READ, command_addr, 0, byte_enable, idle, init_latency);
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        command_addr = command_addr + 4;
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  end
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end

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