Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packet transmitting and receiving is implemented by PTP SW protocol stack with any existing MAC function internal or external to the FPGA; The IP Core implements the Real-Time Clock (RTC) and Time Stamping of PTP event packets (TSU).
The IP Core can be used as an IP Component in Altera SOPC Builder. Example provided.
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The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by any equivalent dual clock FIFO from other FPGA vendors.