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edn_walter |
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2011 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
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# Date created = 14:35:47 March 31, 2012
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# ha1588_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY ha1588
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47 MARCH 31, 2012"
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set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name SDC_FILE ha1588.sdc
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set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v
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set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v
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set_global_assignment -name VERILOG_FILE ../../rtl/tsu/tsu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_queue.v
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set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_parser.v
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
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set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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