Subversion Repositories ha1588

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2011 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version

# Date created = 14:35:47  March 31, 2012

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               ha1588_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone III"

set_global_assignment -name DEVICE AUTO

set_global_assignment -name TOP_LEVEL_ENTITY ha1588

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47  MARCH 31, 2012"

set_global_assignment -name LAST_QUARTUS_VERSION 12.1

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name SDC_FILE ha1588.sdc

set_global_assignment -name SEARCH_PATH .\\ip

set_global_assignment -name VERILOG_FILE ./ip/dcfifo_128b_16.v

set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v

set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v

set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v

set_global_assignment -name VERILOG_FILE ../../rtl/tsu/tsu.v

set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_queue.v

set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_parser.v

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON

set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO

set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top