Subversion Repositories ha1588

# TCL File Generated by Component Editor 10.1sp1

# Sat Mar 31 21:26:56 CST 2012

# DO NOT MODIFY

# +-----------------------------------

# | 

# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0

# | BABY&HW 2012.03.31.21:26:56

# | Hardware Assisted IEEE 1588 IP Core

# | 

# | ha1588.v

# | 

# |    ../../../rtl/top/ha1588.v syn, sim

# |    ../../../rtl/reg/reg.v syn, sim

# |    ../../../rtl/rtc/rtc.v syn, sim

# |    ../../../rtl/tsu/tsu.v syn, sim

# |    ../../../rtl/tsu/ptp_parser.v syn, sim

# |    ../../../rtl/tsu/ptp_queue.v syn, sim

# | 

# +-----------------------------------

# +-----------------------------------

# | request TCL package from ACDS 10.1

# | 

package require -exact sopc 10.1

# | 

# +-----------------------------------

# +-----------------------------------

# | module ha1588

# | 

set_module_property DESCRIPTION "Hardware Assisted IEEE 1588 IP Core"

set_module_property NAME ha1588

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property AUTHOR "BABY&HW"

set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core"

set_module_property TOP_LEVEL_HDL_FILE ha1588.v

set_module_property TOP_LEVEL_HDL_MODULE ha1588

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL TRUE

# | 

# +-----------------------------------

# +-----------------------------------

# | files

# | 

add_file ../../../par/altera/ip/define.h {SYNTHESIS SIMULATION}

add_file ../../../par/altera/ip/dcfifo_128_16.v {SYNTHESIS SIMULATION}

add_file ../../../rtl/top/ha1588.v {SYNTHESIS SIMULATION}

add_file ../../../rtl/reg/reg.v {SYNTHESIS SIMULATION}

add_file ../../../rtl/rtc/rtc.v {SYNTHESIS SIMULATION}

add_file ../../../rtl/tsu/tsu.v {SYNTHESIS SIMULATION}

add_file ../../../rtl/tsu/ptp_parser.v {SYNTHESIS SIMULATION}

add_file ../../../rtl/tsu/ptp_queue.v {SYNTHESIS SIMULATION}

# | 

# +-----------------------------------

# +-----------------------------------

# | parameters

# | 

add_parameter addr_is_in_word BOOLEAN true ""

set_parameter_property addr_is_in_word DEFAULT_VALUE true

set_parameter_property addr_is_in_word DISPLAY_NAME addr_is_in_word

set_parameter_property addr_is_in_word WIDTH ""

set_parameter_property addr_is_in_word TYPE BOOLEAN

set_parameter_property addr_is_in_word ENABLED false

set_parameter_property addr_is_in_word UNITS None

set_parameter_property addr_is_in_word DESCRIPTION ""

set_parameter_property addr_is_in_word AFFECTS_GENERATION false

set_parameter_property addr_is_in_word HDL_PARAMETER true

# | 

# +-----------------------------------

# +-----------------------------------

# | display items

# | 

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point clock

# | 

add_interface clock clock end

set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1

add_interface_port clock rst reset Input 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point reg_interface

# | 

add_interface reg_interface avalon end

set_interface_property reg_interface addressAlignment DYNAMIC

set_interface_property reg_interface addressUnits WORDS

set_interface_property reg_interface associatedClock clock

set_interface_property reg_interface burstOnBurstBoundariesOnly false

set_interface_property reg_interface explicitAddressSpan 0

set_interface_property reg_interface holdTime 0

set_interface_property reg_interface isMemoryDevice false

set_interface_property reg_interface isNonVolatileStorage false

set_interface_property reg_interface linewrapBursts false

set_interface_property reg_interface maximumPendingReadTransactions 0

set_interface_property reg_interface printableDevice false

set_interface_property reg_interface readLatency 0

set_interface_property reg_interface readWaitTime 1

set_interface_property reg_interface setupTime 0

set_interface_property reg_interface timingUnits Cycles

set_interface_property reg_interface writeWaitTime 0

set_interface_property reg_interface ENABLED true

add_interface_port reg_interface wr_in write Input 1

add_interface_port reg_interface rd_in read Input 1

add_interface_port reg_interface addr_in address Input 8

add_interface_port reg_interface data_in writedata Input 32

add_interface_port reg_interface data_out readdata Output 32

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point rtc_interface

# | 

add_interface rtc_interface conduit end

set_interface_property rtc_interface ENABLED true

add_interface_port rtc_interface rtc_clk export Input 1

add_interface_port rtc_interface rtc_time_ptp_ns export Output 32

add_interface_port rtc_interface rtc_time_ptp_sec export Output 48

add_interface_port rtc_interface rtc_time_one_pps export Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point tsu_interface

# | 

add_interface tsu_interface conduit end

set_interface_property tsu_interface ENABLED true

add_interface_port tsu_interface rx_gmii_clk export Input 1

add_interface_port tsu_interface rx_gmii_ctrl export Input 1

add_interface_port tsu_interface rx_gmii_data export Input 8

add_interface_port tsu_interface rx_giga_mode export Input 1

add_interface_port tsu_interface tx_gmii_clk export Input 1

add_interface_port tsu_interface tx_gmii_ctrl export Input 1

add_interface_port tsu_interface tx_gmii_data export Input 8

add_interface_port tsu_interface tx_giga_mode export Input 1

# | 

# +-----------------------------------