OpenCores
URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [bus/] [wishbone/] [wb_slv_wrapper.v] - Blame information for rev 67

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 66 ash_riple
/*
2
 * wb_slv_wrapper.v
3
 *
4
 * Copyright (c) 2012, BABY&HW. All rights reserved.
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2.1 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19
 * MA 02110-1301  USA
20
 */
21
 
22
`timescale 1ns/1ns
23
 
24
module wb_slv_wrapper (
25
  // wishbone side
26
  input         rst_i,clk_i,
27
  input         stb_i,we_i,
28
  output        ack_o,
29
  input  [31:0] adr_i,  // in byte
30
  input  [31:0] dat_i,
31
  output [31:0] dat_o,
32
  // localbus side
33 67 ash_riple
  output        rst,clk,
34 66 ash_riple
  output        wr_out,rd_out,
35
  output [ 7:0] addr_out,  // in byte
36
  output [31:0] data_out,
37
  input  [31:0] data_in
38
);
39
 
40
reg  stb_i_d1;
41
wire stb_internal = stb_i && !stb_i_d1;
42
reg  ack_internal;
43
 
44
// localbus output
45
always @(posedge rst_i or posedge clk_i) begin
46
  if (rst_i)
47
    stb_i_d1 <= 1'b0;
48
  else if (ack_internal)
49
    stb_i_d1 <= 1'b0;
50
  else
51
    stb_i_d1 <= stb_i;
52
end
53
 
54
assign {rst, clk}     = {rst_i, clk_i};
55
assign wr_out         = stb_internal &&  we_i;
56
assign rd_out         = stb_internal && !we_i;
57
assign addr_out[ 7:0] = adr_i[ 7:0];
58
assign data_out[31:0] = dat_i[31:0];
59
 
60
// wishbone output
61
always @(posedge rst_i or posedge clk_i) begin
62
  if (rst_i)
63
    ack_internal <= 1'b0;
64
  else if (ack_internal)
65
    ack_internal <= 1'b0;
66
  else if (stb_i)
67
    ack_internal <= 1'b1;
68
  else
69
    ack_internal <= ack_internal;
70
end
71
 
72
assign ack_o       = ack_internal;
73
assign dat_o[31:0] = data_in[31:0];
74
 
75
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.