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[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Blame information for rev 69

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1 34 edn_walter 
/*
2 38 edn_walter 
 * rtc.v
3 34 edn_walter 
 *
4 37 edn_walter 
 * Copyright (c) 2012, BABY&HW. All rights reserved.
5 34 edn_walter 
 *
6 
 * This library is free software; you can redistribute it and/or
7 
 * modify it under the terms of the GNU Lesser General Public
8 
 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
10 
 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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 * MA 02110-1301  USA
20 
 */
21 
 
22 3 ash_riple 
`timescale 1ns/1ns
23 
 
24 15 edn_walter 
module rtc (
25 3 ash_riple 
  input rst, clk,
26 
  // 1. direct time adjustment: ToD set up
27 39 edn_walter 
  input        time_ld,
28 3 ash_riple 
  input [37:0] time_reg_ns_in,   // 37:8 ns, 7:0 ns_fraction
29 
  input [47:0] time_reg_sec_in,  // 47:0 sec
30 
  // 2. frequency adjustment: frequency set up for drift compensation
31 39 edn_walter 
  input        period_ld,
32 3 ash_riple 
  input [39:0] period_in,        // 39:32 ns, 31:0 ns_fraction
33 
  // 3. precise time adjustment: small time difference adjustment with a time mark
34 39 edn_walter 
  input        adj_ld,
35 3 ash_riple 
  input [31:0] adj_ld_data,
36 38 edn_walter 
  output reg   adj_ld_done,
37 3 ash_riple 
  input [39:0] period_adj,  // 39:32 ns, 31:0 ns_fraction
38 
 
39 32 edn_walter 
  // time output: for internal with ns fraction
40 3 ash_riple 
  output [37:0] time_reg_ns,  // 37:8 ns, 7:0 ns_fraction
41 32 edn_walter 
  output [47:0] time_reg_sec, // 47:0 sec
42 58 edn_walter 
  // time output: for external with one pps accuracy
43 
  output reg    time_one_pps,
44 32 edn_walter 
  // time output: for external with ptp standard
45 
  output [31:0] time_ptp_ns,  // 31:0 ns
46 
  output [47:0] time_ptp_sec  // 47:0 sec
47 3 ash_riple 
);
48 
 
49 69 ash_riple 
parameter time_acc_modulo = 38'd256000000000;  // 1,000,000,000ns * 256ns_fraction, 1s carry_out
50 38 edn_walter 
 
51 3 ash_riple 
reg  [39:0] period_fix;  // 39:32 ns, 31:0 ns_fraction
52 
reg  [31:0] adj_cnt;
53 
reg  [39:0] time_adj;    // 39:32 ns, 31:0 ns_fraction
54 
// frequency and small time difference adjustment registers
55 
always @(posedge rst or posedge clk) begin
56 
  if (rst) begin
57 38 edn_walter 
    period_fix  <= period_fix;  //40'd0;
58 
    adj_cnt     <= 32'hffffffff;
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    time_adj    <= time_adj;    //40'd0;
60 
    adj_ld_done <= 1'b0;
61 3 ash_riple 
  end
62 
  else begin
63 
    if (period_ld)  // load period adjustment
64 
      period_fix <= period_in;
65 
    else
66 
      period_fix <= period_fix;
67 
 
68 
    if (adj_ld)  // load precise time adjustment time mark
69 
      adj_cnt  <= adj_ld_data;
70 
    else if (adj_cnt==32'hffffffff)
71 
      adj_cnt  <= adj_cnt;  // no cycling
72 
    else
73 
      adj_cnt  <= adj_cnt - 1;  // counting down
74 
 
75 
    if (adj_cnt==0)  // change period temparorily
76 
      time_adj <= period_fix + period_adj;
77 
    else
78 
      time_adj <= period_fix + 0;
79 38 edn_walter 
 
80 
    if (adj_cnt==32'hffffffff)
81 
      adj_ld_done <= 1'b1;
82 
    else
83 
      adj_ld_done <= 1'b0;
84 3 ash_riple 
  end
85 
end
86 
 
87 69 ash_riple 
reg  [39:0] time_adj_08n_32f;      //             39:32 ns, 31:0 ns_fraction
88 
reg  [39:0] time_adj_16b_00n_24f;  // 39:24 sign,           23:0 ns_fraction
89 
wire [37:0] time_adj_22b_08n_08f;  // 37:16 sign, 15: 8 ns,  7:0 ns_fraction
90 3 ash_riple 
// delta-sigma circuit to keep the lower 24bit of time_adj
91 19 edn_walter 
always @(posedge rst or posedge clk) begin
92 3 ash_riple 
  if (rst) begin
93 69 ash_riple 
    time_adj_08n_32f     <= 40'd0;
94 
    time_adj_16b_00n_24f <= 24'd0;
95 3 ash_riple 
  end
96 
  else begin
97 69 ash_riple 
    time_adj_08n_32f     <= time_adj[39: 0] + time_adj_16b_00n_24f;  // add the delta
98 
    time_adj_16b_00n_24f <= {16'h0000, time_adj_08n_32f[23: 0]}; // save the delta
99 3 ash_riple 
  end
100 
end
101 69 ash_riple 
assign time_adj_22b_08n_08f = time_adj_08n_32f[39]? {22'h3fffff, time_adj_08n_32f[39:24]}: {22'h000000, time_adj_08n_32f[39:24]};  // preserve the sign
102 3 ash_riple 
 
103 41 edn_walter 
reg  [37:0] time_acc_30n_08f_pre_pos;  // 37:8 ns , 7:0 ns_fraction
104 
reg  [37:0] time_acc_30n_08f_pre_neg;  // 37:8 ns , 7:0 ns_fraction
105 
wire        time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;
106 
// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)
107 
always @(posedge rst or posedge clk) begin
108 
  if (rst) begin
109 45 edn_walter 
    time_acc_30n_08f_pre_pos <= 38'd0;
110 
    time_acc_30n_08f_pre_neg <= 38'd0;
111 41 edn_walter 
  end
112 
  else begin
113 
    if (time_ld) begin  // direct write
114 69 ash_riple 
      time_acc_30n_08f_pre_pos <= time_reg_ns_in + time_adj_22b_08n_08f;
115 
      time_acc_30n_08f_pre_neg <= time_reg_ns_in + time_adj_22b_08n_08f;
116 41 edn_walter 
    end
117 
    else begin
118 
      if (time_acc_48s_inc) begin
119 69 ash_riple 
        time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_neg + time_adj_22b_08n_08f;
120 
        time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_neg + time_adj_22b_08n_08f - time_acc_modulo;
121 41 edn_walter 
      end
122 
      else begin
123 69 ash_riple 
        time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_pos + time_adj_22b_08n_08f;
124 
        time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_pos + time_adj_22b_08n_08f - time_acc_modulo;
125 41 edn_walter 
      end
126 
    end
127 
  end
128 
end
129 
 
130 
reg  [37:0] time_acc_30n_08f;          // 37:8 ns , 7:0 ns_fraction
131 
reg  [47:0] time_acc_48s;              // 47:0 sec
132 3 ash_riple 
// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction)
133 
always @(posedge rst or posedge clk) begin
134 
  if (rst) begin
135 
    time_acc_30n_08f <= 38'd0;
136 
    time_acc_48s     <= 48'd0;
137 
  end
138 
  else begin
139 
    if (time_ld) begin  // direct write
140 
      time_acc_30n_08f <= time_reg_ns_in;
141 
      time_acc_48s     <= time_reg_sec_in;
142 
    end
143 
    else begin
144 19 edn_walter 
 
145 
      if (time_acc_48s_inc)
146 41 edn_walter 
        time_acc_30n_08f <= time_acc_30n_08f_pre_neg;
147 19 edn_walter 
      else
148 41 edn_walter 
        time_acc_30n_08f <= time_acc_30n_08f_pre_pos;
149 19 edn_walter 
 
150 
      if (time_acc_48s_inc)
151 
        time_acc_48s     <= time_acc_48s + 1;
152 
      else
153 
        time_acc_48s     <= time_acc_48s;
154 
 
155 3 ash_riple 
    end
156 
  end
157 
end
158 
 
159 
// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
160 
assign time_reg_ns  = time_acc_30n_08f;
161 
assign time_reg_sec = time_acc_48s;
162 32 edn_walter 
// time output (48bit_s + 32bit_ns)
163 69 ash_riple 
assign time_ptp_ns  = {2'b00, time_acc_30n_08f[37:8]};  // 30bit is enough to represent 1,000,000,000ns
164 32 edn_walter 
assign time_ptp_sec = time_acc_48s;
165 58 edn_walter 
// time output one pps
166 
always @(posedge rst or posedge clk) begin
167 
  if (rst)
168 
    time_one_pps <= 1'b0;
169 
  else
170 
    time_one_pps <= time_acc_48s_inc;
171 
end
172 3 ash_riple 
 
173 
endmodule

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