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[/] [ha1588/] [trunk/] [rtl/] [top/] [ha1588.v] - Blame information for rev 27

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Line No. Rev Author Line
1 18 edn_walter
`timescale 1ns/1ns
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module ha1588 (
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  input         rst,clk,
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  input         wr_in,rd_in,
6 21 edn_walter
  input  [ 7:0] addr_in,
7 18 edn_walter
  input  [31:0] data_in,
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  output [31:0] data_out,
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  input rtc_clk,
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  input       rx_gmii_clk,
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  input       rx_gmii_ctrl,
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  input [7:0] rx_gmii_data,
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  input       tx_gmii_clk,
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  input       tx_gmii_ctrl,
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  input [7:0] tx_gmii_data
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);
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wire rtc_rst;
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wire rtc_time_ld, rtc_period_ld, rtc_adj_ld;
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wire [37:0] rtc_time_reg_ns;
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wire [47:0] rtc_time_reg_sec;
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wire [39:0] rtc_period;
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wire [37:0] rtc_time_acc_modulo;
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wire [31:0] rtc_adj_ld_data;
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wire [39:0] rtc_period_adj;
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wire [37:0] rtc_time_reg_ns_val;
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wire [47:0] rtc_time_reg_sec_val;
30 27 edn_walter
wire [35:0] rtc_time_reg_val = {rtc_time_reg_sec_val[5:0],rtc_time_reg_ns_val[37:8]};  // 64.000,000,000 sec
31 18 edn_walter
 
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wire rx_q_rst, rx_q_clk;
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wire rx_q_rd_en;
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wire [ 7:0] rx_q_stat;
35 27 edn_walter
wire [63:0] rx_q_data;
36 18 edn_walter
wire tx_q_rst, tx_q_clk;
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wire tx_q_rd_en;
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wire [ 7:0] tx_q_stat;
39 27 edn_walter
wire [63:0] tx_q_data;
40 18 edn_walter
 
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rgs u_rgs
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(
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  .rst(rst),
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  .clk(clk),
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  .wr_in(wr_in),
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  .rd_in(rd_in),
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  .addr_in(addr_in),
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  .data_in(data_in),
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  .data_out(data_out),
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  .rtc_clk_in(rtc_clk),
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  .rtc_rst_out(rtc_rst),
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  .time_ld_out(rtc_time_ld),
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  .time_reg_ns_out(rtc_time_reg_ns),
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  .time_reg_sec_out(rtc_time_reg_sec),
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  .period_ld_out(rtc_period_ld),
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  .period_out(rtc_period),
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  .time_acc_modulo_out(rtc_time_acc_modulo),
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  .adj_ld_out(rtc_adj_ld),
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  .adj_ld_data_out(rtc_adj_ld_data),
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  .period_adj_out(rtc_period_adj),
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  .time_reg_ns_in(rtc_time_reg_ns_val),
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  .time_reg_sec_in(rtc_time_reg_sec_val),
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  .rx_q_rst_out(rx_q_rst),
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  .rx_q_rd_clk_out(rx_q_clk),
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  .rx_q_rd_en_out(rx_q_rd_en),
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  .rx_q_stat_in(rx_q_stat),
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  .rx_q_data_in(rx_q_data),
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  .tx_q_rst_out(tx_q_rst),
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  .tx_q_rd_clk_out(tx_q_clk),
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  .tx_q_rd_en_out(tx_q_rd_en),
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  .tx_q_stat_in(tx_q_stat),
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  .tx_q_data_in(tx_q_data)
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);
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rtc u_rtc
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(
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  .rst(rtc_rst),
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  .clk(rtc_clk),
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  .time_ld(rtc_time_ld),
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  .time_reg_ns_in(rtc_time_reg_ns),
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  .time_reg_sec_in(rtc_time_reg_sec),
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  .period_ld(rtc_period_ld),
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  .period_in(rtc_period),
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  .time_acc_modulo(rtc_time_acc_modulo),
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  .adj_ld(rtc_adj_ld),
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  .adj_ld_data(rtc_adj_ld_data),
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  .period_adj(rtc_period_adj),
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  .time_reg_ns(rtc_time_reg_ns_val),
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  .time_reg_sec(rtc_time_reg_sec_val)
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);
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tsu u_rx_tsu
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(
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  .rst(rst),
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  .gmii_clk(rx_gmii_clk),
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  .gmii_ctrl(rx_gmii_ctrl),
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  .gmii_data(rx_gmii_data),
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  .rtc_timer_clk(rtc_clk),
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  .rtc_timer_in(rtc_time_reg_val),
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  .q_rst(rx_q_rst),
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  .q_rd_clk(rx_q_clk),
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  .q_rd_en(rx_q_rd_en),
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  .q_rd_stat(rx_q_stat),
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  .q_rd_data(rx_q_data)
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);
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tsu u_tx_tsu
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(
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  .rst(rst),
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  .gmii_clk(tx_gmii_clk),
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  .gmii_ctrl(tx_gmii_ctrl),
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  .gmii_data(tx_gmii_data),
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  .rtc_timer_clk(rtc_clk),
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  .rtc_timer_in(rtc_time_reg_val),
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  .q_rst(tx_q_rst),
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  .q_rd_clk(tx_q_clk),
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  .q_rd_en(tx_q_rd_en),
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  .q_rd_stat(tx_q_stat),
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  .q_rd_data(tx_q_data)
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);
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endmodule

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