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edn_walter |
// Copyright (C) 1991-2011 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// Quartus II 10.1 Build 197 11/29/2010
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//START_MODULE_NAME------------------------------------------------------------
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//
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// Module Name : ALTERA_MF_HINT_EVALUATION
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//
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// Description : Common function to grep the value of altera specific parameters
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// within the lpm_hint parameter.
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//
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// Limitation : No error checking to check whether the content of the lpm_hint
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// is valid or not.
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//
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// Results expected: If the target parameter found, return the value of the parameter.
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// Otherwise, return empty string.
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//
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//END_MODULE_NAME--------------------------------------------------------------
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// BEGINNING OF MODULE
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`timescale 1 ps / 1 ps
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// MODULE DECLARATION
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module ALTERA_MF_HINT_EVALUATION;
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// FUNCTON DECLARATION
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// This function will search through the string (given string) to look for a match for the
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// a given parameter(compare_param_name). It will return the value for the given parameter.
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function [8*200:1] GET_PARAMETER_VALUE;
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input [8*200:1] given_string; // string to be searched
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input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string.
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integer param_value_char_count; // to indicate current character count in the param_value
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integer param_name_char_count; // to indicate current character count in the param_name
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integer white_space_count;
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reg extract_param_value; // if 1 mean extracting parameters value from given string
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reg extract_param_name; // if 1 mean extracting parameters name from given string
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reg param_found; // to indicate whether compare_param_name have been found in the given_string
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reg include_white_space; // if 1, include white space in the parameter value
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reg [8*200:1] reg_string; // to store the value of the given string
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reg [8*50:1] param_name; // to store parameter name
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reg [8*20:1] param_value; // to store parameter value
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reg [8:1] tmp; // to get the value of the current byte
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begin
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reg_string = given_string;
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param_value_char_count = 0;
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param_name_char_count =0;
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extract_param_value = 1;
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extract_param_name = 0;
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param_found = 0;
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include_white_space = 0;
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white_space_count = 0;
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tmp = reg_string[8:1];
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// checking every bytes of the reg_string from right to left.
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while ((tmp != 0 ) && (param_found != 1))
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begin
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tmp = reg_string[8:1];
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//if tmp != ' ' or should include white space (trailing white space are ignored)
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if((tmp != 32) || (include_white_space == 1))
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begin
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if(tmp == 32)
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begin
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white_space_count = 1;
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end
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else if(tmp == 61) // if tmp = '='
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begin
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extract_param_value = 0;
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extract_param_name = 1; // subsequent bytes should be part of param_name
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include_white_space = 0; // ignore the white space (if any) between param_name and '='
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white_space_count = 0;
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param_value = param_value >> (8 * (20 - param_value_char_count));
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param_value_char_count = 0;
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end
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else if (tmp == 44) // if tmp = ','
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begin
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extract_param_value = 1; // subsequent bytes should be part of param_value
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extract_param_name = 0;
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param_name = param_name >> (8 * (50 - param_name_char_count));
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param_name_char_count = 0;
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if(param_name == compare_param_name)
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param_found = 1; // the compare_param_name have been found in the reg_string
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end
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else
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begin
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if(extract_param_value == 1)
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begin
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param_value_char_count = param_value_char_count + white_space_count + 1;
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include_white_space = 1;
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if(white_space_count > 0)
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begin
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param_value = {8'b100000, param_value[20*8:9]};
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white_space_count = 0;
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end
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param_value = {tmp, param_value[20*8:9]};
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end
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else if(extract_param_name == 1)
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begin
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param_name = {tmp, param_name[50*8:9]};
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param_name_char_count = param_name_char_count + 1;
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end
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end
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end
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reg_string = reg_string >> 8; // shift 1 byte to the right
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end
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// for the case whether param_name is the left most part of the reg_string
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if(extract_param_name == 1)
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begin
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param_name = param_name >> (8 * (50 - param_name_char_count));
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if(param_name == compare_param_name)
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param_found = 1;
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end
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if (param_found == 1)
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GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for
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else
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GET_PARAMETER_VALUE = ""; // return empty string if parameter not found
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end
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endfunction
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endmodule // ALTERA_MF_HINT_EVALUATION
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//START_MODULE_NAME------------------------------------------------------------
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//
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// Module Name : ALTERA_DEVICE_FAMILIES
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//
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// Description : Common Altera device families comparison
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//
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// Limitation :
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//
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// Results expected:
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//
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//END_MODULE_NAME--------------------------------------------------------------
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// BEGINNING OF MODULE
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`timescale 1 ps / 1 ps
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// MODULE DECLARATION
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module ALTERA_DEVICE_FAMILIES;
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function IS_FAMILY_STRATIX;
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input[8*20:1] device;
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reg is_stratix;
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begin
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if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
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is_stratix = 1;
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else
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is_stratix = 0;
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IS_FAMILY_STRATIX = is_stratix;
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end
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endfunction //IS_FAMILY_STRATIX
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function IS_FAMILY_STRATIXGX;
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input[8*20:1] device;
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reg is_stratixgx;
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begin
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if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
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is_stratixgx = 1;
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else
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is_stratixgx = 0;
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IS_FAMILY_STRATIXGX = is_stratixgx;
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end
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endfunction //IS_FAMILY_STRATIXGX
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function IS_FAMILY_CYCLONE;
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input[8*20:1] device;
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reg is_cyclone;
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begin
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if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
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is_cyclone = 1;
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else
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is_cyclone = 0;
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IS_FAMILY_CYCLONE = is_cyclone;
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end
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endfunction //IS_FAMILY_CYCLONE
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function IS_FAMILY_MAXII;
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input[8*20:1] device;
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reg is_maxii;
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begin
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if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
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is_maxii = 1;
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else
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is_maxii = 0;
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IS_FAMILY_MAXII = is_maxii;
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end
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endfunction //IS_FAMILY_MAXII
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function IS_FAMILY_STRATIXII;
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input[8*20:1] device;
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reg is_stratixii;
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begin
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if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
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is_stratixii = 1;
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else
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is_stratixii = 0;
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IS_FAMILY_STRATIXII = is_stratixii;
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end
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endfunction //IS_FAMILY_STRATIXII
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function IS_FAMILY_STRATIXIIGX;
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input[8*20:1] device;
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reg is_stratixiigx;
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begin
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if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
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is_stratixiigx = 1;
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else
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is_stratixiigx = 0;
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IS_FAMILY_STRATIXIIGX = is_stratixiigx;
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end
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endfunction //IS_FAMILY_STRATIXIIGX
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function IS_FAMILY_ARRIAGX;
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input[8*20:1] device;
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reg is_arriagx;
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begin
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if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
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is_arriagx = 1;
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else
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is_arriagx = 0;
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IS_FAMILY_ARRIAGX = is_arriagx;
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end
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endfunction //IS_FAMILY_ARRIAGX
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function IS_FAMILY_CYCLONEII;
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input[8*20:1] device;
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reg is_cycloneii;
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begin
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if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
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is_cycloneii = 1;
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else
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is_cycloneii = 0;
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IS_FAMILY_CYCLONEII = is_cycloneii;
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end
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endfunction //IS_FAMILY_CYCLONEII
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function IS_FAMILY_HARDCOPYII;
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input[8*20:1] device;
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reg is_hardcopyii;
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begin
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if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
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is_hardcopyii = 1;
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else
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is_hardcopyii = 0;
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IS_FAMILY_HARDCOPYII = is_hardcopyii;
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end
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endfunction //IS_FAMILY_HARDCOPYII
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function IS_FAMILY_STRATIXIII;
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input[8*20:1] device;
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reg is_stratixiii;
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begin
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if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
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is_stratixiii = 1;
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else
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is_stratixiii = 0;
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IS_FAMILY_STRATIXIII = is_stratixiii;
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end
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endfunction //IS_FAMILY_STRATIXIII
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function IS_FAMILY_CYCLONEIII;
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input[8*20:1] device;
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reg is_cycloneiii;
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begin
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if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
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is_cycloneiii = 1;
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else
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is_cycloneiii = 0;
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IS_FAMILY_CYCLONEIII = is_cycloneiii;
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end
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endfunction //IS_FAMILY_CYCLONEIII
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function IS_FAMILY_STRATIXIV;
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input[8*20:1] device;
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reg is_stratixiv;
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begin
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if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|
309 |
|
|
is_stratixiv = 1;
|
310 |
|
|
else
|
311 |
|
|
is_stratixiv = 0;
|
312 |
|
|
|
313 |
|
|
IS_FAMILY_STRATIXIV = is_stratixiv;
|
314 |
|
|
end
|
315 |
|
|
endfunction //IS_FAMILY_STRATIXIV
|
316 |
|
|
|
317 |
|
|
function IS_FAMILY_ARRIAIIGX;
|
318 |
|
|
input[8*20:1] device;
|
319 |
|
|
reg is_arriaiigx;
|
320 |
|
|
begin
|
321 |
|
|
if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|
322 |
|
|
is_arriaiigx = 1;
|
323 |
|
|
else
|
324 |
|
|
is_arriaiigx = 0;
|
325 |
|
|
|
326 |
|
|
IS_FAMILY_ARRIAIIGX = is_arriaiigx;
|
327 |
|
|
end
|
328 |
|
|
endfunction //IS_FAMILY_ARRIAIIGX
|
329 |
|
|
|
330 |
|
|
function IS_FAMILY_HARDCOPYIII;
|
331 |
|
|
input[8*20:1] device;
|
332 |
|
|
reg is_hardcopyiii;
|
333 |
|
|
begin
|
334 |
|
|
if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|
335 |
|
|
is_hardcopyiii = 1;
|
336 |
|
|
else
|
337 |
|
|
is_hardcopyiii = 0;
|
338 |
|
|
|
339 |
|
|
IS_FAMILY_HARDCOPYIII = is_hardcopyiii;
|
340 |
|
|
end
|
341 |
|
|
endfunction //IS_FAMILY_HARDCOPYIII
|
342 |
|
|
|
343 |
|
|
function IS_FAMILY_HARDCOPYIV;
|
344 |
|
|
input[8*20:1] device;
|
345 |
|
|
reg is_hardcopyiv;
|
346 |
|
|
begin
|
347 |
|
|
if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|
348 |
|
|
is_hardcopyiv = 1;
|
349 |
|
|
else
|
350 |
|
|
is_hardcopyiv = 0;
|
351 |
|
|
|
352 |
|
|
IS_FAMILY_HARDCOPYIV = is_hardcopyiv;
|
353 |
|
|
end
|
354 |
|
|
endfunction //IS_FAMILY_HARDCOPYIV
|
355 |
|
|
|
356 |
|
|
function IS_FAMILY_CYCLONEIIILS;
|
357 |
|
|
input[8*20:1] device;
|
358 |
|
|
reg is_cycloneiiils;
|
359 |
|
|
begin
|
360 |
|
|
if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|
361 |
|
|
is_cycloneiiils = 1;
|
362 |
|
|
else
|
363 |
|
|
is_cycloneiiils = 0;
|
364 |
|
|
|
365 |
|
|
IS_FAMILY_CYCLONEIIILS = is_cycloneiiils;
|
366 |
|
|
end
|
367 |
|
|
endfunction //IS_FAMILY_CYCLONEIIILS
|
368 |
|
|
|
369 |
|
|
function IS_FAMILY_CYCLONEIVGX;
|
370 |
|
|
input[8*20:1] device;
|
371 |
|
|
reg is_cycloneivgx;
|
372 |
|
|
begin
|
373 |
|
|
if ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|
374 |
|
|
is_cycloneivgx = 1;
|
375 |
|
|
else
|
376 |
|
|
is_cycloneivgx = 0;
|
377 |
|
|
|
378 |
|
|
IS_FAMILY_CYCLONEIVGX = is_cycloneivgx;
|
379 |
|
|
end
|
380 |
|
|
endfunction //IS_FAMILY_CYCLONEIVGX
|
381 |
|
|
|
382 |
|
|
function IS_FAMILY_CYCLONEIVE;
|
383 |
|
|
input[8*20:1] device;
|
384 |
|
|
reg is_cycloneive;
|
385 |
|
|
begin
|
386 |
|
|
if ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|
387 |
|
|
is_cycloneive = 1;
|
388 |
|
|
else
|
389 |
|
|
is_cycloneive = 0;
|
390 |
|
|
|
391 |
|
|
IS_FAMILY_CYCLONEIVE = is_cycloneive;
|
392 |
|
|
end
|
393 |
|
|
endfunction //IS_FAMILY_CYCLONEIVE
|
394 |
|
|
|
395 |
|
|
function IS_FAMILY_STRATIXV;
|
396 |
|
|
input[8*20:1] device;
|
397 |
|
|
reg is_stratixv;
|
398 |
|
|
begin
|
399 |
|
|
if ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
|
400 |
|
|
is_stratixv = 1;
|
401 |
|
|
else
|
402 |
|
|
is_stratixv = 0;
|
403 |
|
|
|
404 |
|
|
IS_FAMILY_STRATIXV = is_stratixv;
|
405 |
|
|
end
|
406 |
|
|
endfunction //IS_FAMILY_STRATIXV
|
407 |
|
|
|
408 |
|
|
function IS_FAMILY_ARRIAIIGZ;
|
409 |
|
|
input[8*20:1] device;
|
410 |
|
|
reg is_arriaiigz;
|
411 |
|
|
begin
|
412 |
|
|
if ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|
413 |
|
|
is_arriaiigz = 1;
|
414 |
|
|
else
|
415 |
|
|
is_arriaiigz = 0;
|
416 |
|
|
|
417 |
|
|
IS_FAMILY_ARRIAIIGZ = is_arriaiigz;
|
418 |
|
|
end
|
419 |
|
|
endfunction //IS_FAMILY_ARRIAIIGZ
|
420 |
|
|
|
421 |
|
|
function IS_FAMILY_MAXV;
|
422 |
|
|
input[8*20:1] device;
|
423 |
|
|
reg is_maxv;
|
424 |
|
|
begin
|
425 |
|
|
if ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|
426 |
|
|
is_maxv = 1;
|
427 |
|
|
else
|
428 |
|
|
is_maxv = 0;
|
429 |
|
|
|
430 |
|
|
IS_FAMILY_MAXV = is_maxv;
|
431 |
|
|
end
|
432 |
|
|
endfunction //IS_FAMILY_MAXV
|
433 |
|
|
|
434 |
|
|
function FEATURE_FAMILY_STRATIXGX;
|
435 |
|
|
input[8*20:1] device;
|
436 |
|
|
reg var_family_stratixgx;
|
437 |
|
|
begin
|
438 |
|
|
if (IS_FAMILY_STRATIXGX(device) )
|
439 |
|
|
var_family_stratixgx = 1;
|
440 |
|
|
else
|
441 |
|
|
var_family_stratixgx = 0;
|
442 |
|
|
|
443 |
|
|
FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
|
444 |
|
|
end
|
445 |
|
|
endfunction //FEATURE_FAMILY_STRATIXGX
|
446 |
|
|
|
447 |
|
|
function FEATURE_FAMILY_CYCLONE;
|
448 |
|
|
input[8*20:1] device;
|
449 |
|
|
reg var_family_cyclone;
|
450 |
|
|
begin
|
451 |
|
|
if (IS_FAMILY_CYCLONE(device) )
|
452 |
|
|
var_family_cyclone = 1;
|
453 |
|
|
else
|
454 |
|
|
var_family_cyclone = 0;
|
455 |
|
|
|
456 |
|
|
FEATURE_FAMILY_CYCLONE = var_family_cyclone;
|
457 |
|
|
end
|
458 |
|
|
endfunction //FEATURE_FAMILY_CYCLONE
|
459 |
|
|
|
460 |
|
|
function FEATURE_FAMILY_STRATIXIIGX;
|
461 |
|
|
input[8*20:1] device;
|
462 |
|
|
reg var_family_stratixiigx;
|
463 |
|
|
begin
|
464 |
|
|
if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) )
|
465 |
|
|
var_family_stratixiigx = 1;
|
466 |
|
|
else
|
467 |
|
|
var_family_stratixiigx = 0;
|
468 |
|
|
|
469 |
|
|
FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx;
|
470 |
|
|
end
|
471 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIIGX
|
472 |
|
|
|
473 |
|
|
function FEATURE_FAMILY_STRATIXIII;
|
474 |
|
|
input[8*20:1] device;
|
475 |
|
|
reg var_family_stratixiii;
|
476 |
|
|
begin
|
477 |
|
|
if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) )
|
478 |
|
|
var_family_stratixiii = 1;
|
479 |
|
|
else
|
480 |
|
|
var_family_stratixiii = 0;
|
481 |
|
|
|
482 |
|
|
FEATURE_FAMILY_STRATIXIII = var_family_stratixiii;
|
483 |
|
|
end
|
484 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIII
|
485 |
|
|
|
486 |
|
|
function FEATURE_FAMILY_STRATIXV;
|
487 |
|
|
input[8*20:1] device;
|
488 |
|
|
reg var_family_stratixv;
|
489 |
|
|
begin
|
490 |
|
|
if (IS_FAMILY_STRATIXV(device) )
|
491 |
|
|
var_family_stratixv = 1;
|
492 |
|
|
else
|
493 |
|
|
var_family_stratixv = 0;
|
494 |
|
|
|
495 |
|
|
FEATURE_FAMILY_STRATIXV = var_family_stratixv;
|
496 |
|
|
end
|
497 |
|
|
endfunction //FEATURE_FAMILY_STRATIXV
|
498 |
|
|
|
499 |
|
|
function FEATURE_FAMILY_STRATIXII;
|
500 |
|
|
input[8*20:1] device;
|
501 |
|
|
reg var_family_stratixii;
|
502 |
|
|
begin
|
503 |
|
|
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) )
|
504 |
|
|
var_family_stratixii = 1;
|
505 |
|
|
else
|
506 |
|
|
var_family_stratixii = 0;
|
507 |
|
|
|
508 |
|
|
FEATURE_FAMILY_STRATIXII = var_family_stratixii;
|
509 |
|
|
end
|
510 |
|
|
endfunction //FEATURE_FAMILY_STRATIXII
|
511 |
|
|
|
512 |
|
|
function FEATURE_FAMILY_CYCLONEIVGX;
|
513 |
|
|
input[8*20:1] device;
|
514 |
|
|
reg var_family_cycloneivgx;
|
515 |
|
|
begin
|
516 |
|
|
if (IS_FAMILY_CYCLONEIVGX(device) || IS_FAMILY_CYCLONEIVGX(device) )
|
517 |
|
|
var_family_cycloneivgx = 1;
|
518 |
|
|
else
|
519 |
|
|
var_family_cycloneivgx = 0;
|
520 |
|
|
|
521 |
|
|
FEATURE_FAMILY_CYCLONEIVGX = var_family_cycloneivgx;
|
522 |
|
|
end
|
523 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIVGX
|
524 |
|
|
|
525 |
|
|
function FEATURE_FAMILY_CYCLONEIVE;
|
526 |
|
|
input[8*20:1] device;
|
527 |
|
|
reg var_family_cycloneive;
|
528 |
|
|
begin
|
529 |
|
|
if (IS_FAMILY_CYCLONEIVE(device) )
|
530 |
|
|
var_family_cycloneive = 1;
|
531 |
|
|
else
|
532 |
|
|
var_family_cycloneive = 0;
|
533 |
|
|
|
534 |
|
|
FEATURE_FAMILY_CYCLONEIVE = var_family_cycloneive;
|
535 |
|
|
end
|
536 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIVE
|
537 |
|
|
|
538 |
|
|
function FEATURE_FAMILY_CYCLONEIII;
|
539 |
|
|
input[8*20:1] device;
|
540 |
|
|
reg var_family_cycloneiii;
|
541 |
|
|
begin
|
542 |
|
|
if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) || FEATURE_FAMILY_CYCLONEIVGX(device) || FEATURE_FAMILY_CYCLONEIVE(device) )
|
543 |
|
|
var_family_cycloneiii = 1;
|
544 |
|
|
else
|
545 |
|
|
var_family_cycloneiii = 0;
|
546 |
|
|
|
547 |
|
|
FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii;
|
548 |
|
|
end
|
549 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIII
|
550 |
|
|
|
551 |
|
|
function FEATURE_FAMILY_STRATIX_HC;
|
552 |
|
|
input[8*20:1] device;
|
553 |
|
|
reg var_family_stratix_hc;
|
554 |
|
|
begin
|
555 |
|
|
if ((device == "StratixHC") )
|
556 |
|
|
var_family_stratix_hc = 1;
|
557 |
|
|
else
|
558 |
|
|
var_family_stratix_hc = 0;
|
559 |
|
|
|
560 |
|
|
FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
|
561 |
|
|
end
|
562 |
|
|
endfunction //FEATURE_FAMILY_STRATIX_HC
|
563 |
|
|
|
564 |
|
|
function FEATURE_FAMILY_STRATIX;
|
565 |
|
|
input[8*20:1] device;
|
566 |
|
|
reg var_family_stratix;
|
567 |
|
|
begin
|
568 |
|
|
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
|
569 |
|
|
var_family_stratix = 1;
|
570 |
|
|
else
|
571 |
|
|
var_family_stratix = 0;
|
572 |
|
|
|
573 |
|
|
FEATURE_FAMILY_STRATIX = var_family_stratix;
|
574 |
|
|
end
|
575 |
|
|
endfunction //FEATURE_FAMILY_STRATIX
|
576 |
|
|
|
577 |
|
|
function FEATURE_FAMILY_MAXII;
|
578 |
|
|
input[8*20:1] device;
|
579 |
|
|
reg var_family_maxii;
|
580 |
|
|
begin
|
581 |
|
|
if (IS_FAMILY_MAXII(device) || FEATURE_FAMILY_MAXV(device) )
|
582 |
|
|
var_family_maxii = 1;
|
583 |
|
|
else
|
584 |
|
|
var_family_maxii = 0;
|
585 |
|
|
|
586 |
|
|
FEATURE_FAMILY_MAXII = var_family_maxii;
|
587 |
|
|
end
|
588 |
|
|
endfunction //FEATURE_FAMILY_MAXII
|
589 |
|
|
|
590 |
|
|
function FEATURE_FAMILY_MAXV;
|
591 |
|
|
input[8*20:1] device;
|
592 |
|
|
reg var_family_maxv;
|
593 |
|
|
begin
|
594 |
|
|
if (IS_FAMILY_MAXV(device) )
|
595 |
|
|
var_family_maxv = 1;
|
596 |
|
|
else
|
597 |
|
|
var_family_maxv = 0;
|
598 |
|
|
|
599 |
|
|
FEATURE_FAMILY_MAXV = var_family_maxv;
|
600 |
|
|
end
|
601 |
|
|
endfunction //FEATURE_FAMILY_MAXV
|
602 |
|
|
|
603 |
|
|
function FEATURE_FAMILY_CYCLONEII;
|
604 |
|
|
input[8*20:1] device;
|
605 |
|
|
reg var_family_cycloneii;
|
606 |
|
|
begin
|
607 |
|
|
if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
|
608 |
|
|
var_family_cycloneii = 1;
|
609 |
|
|
else
|
610 |
|
|
var_family_cycloneii = 0;
|
611 |
|
|
|
612 |
|
|
FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
|
613 |
|
|
end
|
614 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEII
|
615 |
|
|
|
616 |
|
|
function FEATURE_FAMILY_STRATIXIV;
|
617 |
|
|
input[8*20:1] device;
|
618 |
|
|
reg var_family_stratixiv;
|
619 |
|
|
begin
|
620 |
|
|
if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGX(device) || IS_FAMILY_HARDCOPYIV(device) || FEATURE_FAMILY_STRATIXV(device) || FEATURE_FAMILY_ARRIAIIGZ(device) )
|
621 |
|
|
var_family_stratixiv = 1;
|
622 |
|
|
else
|
623 |
|
|
var_family_stratixiv = 0;
|
624 |
|
|
|
625 |
|
|
FEATURE_FAMILY_STRATIXIV = var_family_stratixiv;
|
626 |
|
|
end
|
627 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIV
|
628 |
|
|
|
629 |
|
|
function FEATURE_FAMILY_ARRIAIIGZ;
|
630 |
|
|
input[8*20:1] device;
|
631 |
|
|
reg var_family_arriaiigz;
|
632 |
|
|
begin
|
633 |
|
|
if (IS_FAMILY_ARRIAIIGZ(device) )
|
634 |
|
|
var_family_arriaiigz = 1;
|
635 |
|
|
else
|
636 |
|
|
var_family_arriaiigz = 0;
|
637 |
|
|
|
638 |
|
|
FEATURE_FAMILY_ARRIAIIGZ = var_family_arriaiigz;
|
639 |
|
|
end
|
640 |
|
|
endfunction //FEATURE_FAMILY_ARRIAIIGZ
|
641 |
|
|
|
642 |
|
|
function FEATURE_FAMILY_ARRIAIIGX;
|
643 |
|
|
input[8*20:1] device;
|
644 |
|
|
reg var_family_arriaiigx;
|
645 |
|
|
begin
|
646 |
|
|
if (IS_FAMILY_ARRIAIIGX(device) )
|
647 |
|
|
var_family_arriaiigx = 1;
|
648 |
|
|
else
|
649 |
|
|
var_family_arriaiigx = 0;
|
650 |
|
|
|
651 |
|
|
FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx;
|
652 |
|
|
end
|
653 |
|
|
endfunction //FEATURE_FAMILY_ARRIAIIGX
|
654 |
|
|
|
655 |
|
|
function FEATURE_FAMILY_BASE_STRATIXII;
|
656 |
|
|
input[8*20:1] device;
|
657 |
|
|
reg var_family_base_stratixii;
|
658 |
|
|
begin
|
659 |
|
|
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
|
660 |
|
|
var_family_base_stratixii = 1;
|
661 |
|
|
else
|
662 |
|
|
var_family_base_stratixii = 0;
|
663 |
|
|
|
664 |
|
|
FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii;
|
665 |
|
|
end
|
666 |
|
|
endfunction //FEATURE_FAMILY_BASE_STRATIXII
|
667 |
|
|
|
668 |
|
|
function FEATURE_FAMILY_BASE_STRATIX;
|
669 |
|
|
input[8*20:1] device;
|
670 |
|
|
reg var_family_base_stratix;
|
671 |
|
|
begin
|
672 |
|
|
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
|
673 |
|
|
var_family_base_stratix = 1;
|
674 |
|
|
else
|
675 |
|
|
var_family_base_stratix = 0;
|
676 |
|
|
|
677 |
|
|
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
|
678 |
|
|
end
|
679 |
|
|
endfunction //FEATURE_FAMILY_BASE_STRATIX
|
680 |
|
|
|
681 |
|
|
function FEATURE_FAMILY_BASE_CYCLONEII;
|
682 |
|
|
input[8*20:1] device;
|
683 |
|
|
reg var_family_base_cycloneii;
|
684 |
|
|
begin
|
685 |
|
|
if (IS_FAMILY_CYCLONEII(device) )
|
686 |
|
|
var_family_base_cycloneii = 1;
|
687 |
|
|
else
|
688 |
|
|
var_family_base_cycloneii = 0;
|
689 |
|
|
|
690 |
|
|
FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii;
|
691 |
|
|
end
|
692 |
|
|
endfunction //FEATURE_FAMILY_BASE_CYCLONEII
|
693 |
|
|
|
694 |
|
|
function FEATURE_FAMILY_BASE_CYCLONE;
|
695 |
|
|
input[8*20:1] device;
|
696 |
|
|
reg var_family_base_cyclone;
|
697 |
|
|
begin
|
698 |
|
|
if (IS_FAMILY_CYCLONE(device) )
|
699 |
|
|
var_family_base_cyclone = 1;
|
700 |
|
|
else
|
701 |
|
|
var_family_base_cyclone = 0;
|
702 |
|
|
|
703 |
|
|
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
|
704 |
|
|
end
|
705 |
|
|
endfunction //FEATURE_FAMILY_BASE_CYCLONE
|
706 |
|
|
|
707 |
|
|
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
|
708 |
|
|
input[8*20:1] device;
|
709 |
|
|
reg var_family_has_stratixii_style_ram;
|
710 |
|
|
begin
|
711 |
|
|
if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
|
712 |
|
|
var_family_has_stratixii_style_ram = 1;
|
713 |
|
|
else
|
714 |
|
|
var_family_has_stratixii_style_ram = 0;
|
715 |
|
|
|
716 |
|
|
FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
|
717 |
|
|
end
|
718 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
|
719 |
|
|
|
720 |
|
|
function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM;
|
721 |
|
|
input[8*20:1] device;
|
722 |
|
|
reg var_family_has_stratixiii_style_ram;
|
723 |
|
|
begin
|
724 |
|
|
if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
|
725 |
|
|
var_family_has_stratixiii_style_ram = 1;
|
726 |
|
|
else
|
727 |
|
|
var_family_has_stratixiii_style_ram = 0;
|
728 |
|
|
|
729 |
|
|
FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram;
|
730 |
|
|
end
|
731 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM
|
732 |
|
|
|
733 |
|
|
function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL;
|
734 |
|
|
input[8*20:1] device;
|
735 |
|
|
reg var_family_has_stratix_style_pll;
|
736 |
|
|
begin
|
737 |
|
|
if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) )
|
738 |
|
|
var_family_has_stratix_style_pll = 1;
|
739 |
|
|
else
|
740 |
|
|
var_family_has_stratix_style_pll = 0;
|
741 |
|
|
|
742 |
|
|
FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll;
|
743 |
|
|
end
|
744 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL
|
745 |
|
|
|
746 |
|
|
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL;
|
747 |
|
|
input[8*20:1] device;
|
748 |
|
|
reg var_family_has_stratixii_style_pll;
|
749 |
|
|
begin
|
750 |
|
|
if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) )
|
751 |
|
|
var_family_has_stratixii_style_pll = 1;
|
752 |
|
|
else
|
753 |
|
|
var_family_has_stratixii_style_pll = 0;
|
754 |
|
|
|
755 |
|
|
FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll;
|
756 |
|
|
end
|
757 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL
|
758 |
|
|
|
759 |
|
|
function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
|
760 |
|
|
input[8*20:1] device;
|
761 |
|
|
reg var_family_has_inverted_output_ddio;
|
762 |
|
|
begin
|
763 |
|
|
if (FEATURE_FAMILY_CYCLONEII(device) )
|
764 |
|
|
var_family_has_inverted_output_ddio = 1;
|
765 |
|
|
else
|
766 |
|
|
var_family_has_inverted_output_ddio = 0;
|
767 |
|
|
|
768 |
|
|
FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
|
769 |
|
|
end
|
770 |
|
|
endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
|
771 |
|
|
|
772 |
|
|
function IS_VALID_FAMILY;
|
773 |
|
|
input[8*20:1] device;
|
774 |
|
|
reg is_valid;
|
775 |
|
|
begin
|
776 |
|
|
if (((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|
777 |
|
|
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|
778 |
|
|
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|
779 |
|
|
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|
780 |
|
|
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|
781 |
|
|
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|
782 |
|
|
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|
783 |
|
|
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|
784 |
|
|
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|
785 |
|
|
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|
786 |
|
|
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|
787 |
|
|
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
|
788 |
|
|
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|
789 |
|
|
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|
790 |
|
|
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|
791 |
|
|
|| ((device == "BS") || (device == "bs"))
|
792 |
|
|
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|
793 |
|
|
|| ((device == "tgx_commercial_v1_1") || (device == "TGX_COMMERCIAL_V1_1"))
|
794 |
|
|
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|
795 |
|
|
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|
796 |
|
|
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|
797 |
|
|
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|
798 |
|
|
|| ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|
799 |
|
|
|| ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|
800 |
|
|
|| ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
|
801 |
|
|
|| ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|
802 |
|
|
|| ((device == "arriaiigz_commercial_v1_1") || (device == "ARRIAIIGZ_COMMERCIAL_V1_1"))
|
803 |
|
|
|| ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|
804 |
|
|
|| ((device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V") || (device == "ARRIA V") || (device == "arria v")))
|
805 |
|
|
is_valid = 1;
|
806 |
|
|
else
|
807 |
|
|
is_valid = 0;
|
808 |
|
|
|
809 |
|
|
IS_VALID_FAMILY = is_valid;
|
810 |
|
|
end
|
811 |
|
|
endfunction // IS_VALID_FAMILY
|
812 |
|
|
|
813 |
|
|
|
814 |
|
|
endmodule // ALTERA_DEVICE_FAMILIES
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
818 |
|
|
//
|
819 |
|
|
// Module Name : dcfifo_dffpipe
|
820 |
|
|
//
|
821 |
|
|
// Description : Dual Clocks FIFO
|
822 |
|
|
//
|
823 |
|
|
// Limitation :
|
824 |
|
|
//
|
825 |
|
|
// Results expected:
|
826 |
|
|
//
|
827 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
828 |
|
|
|
829 |
|
|
// BEGINNING OF MODULE
|
830 |
|
|
`timescale 1 ps / 1 ps
|
831 |
|
|
|
832 |
|
|
// MODULE DECLARATION
|
833 |
|
|
module dcfifo_dffpipe ( d, clock, aclr,
|
834 |
|
|
q);
|
835 |
|
|
|
836 |
|
|
// GLOBAL PARAMETER DECLARATION
|
837 |
|
|
parameter lpm_delay = 1;
|
838 |
|
|
parameter lpm_width = 64;
|
839 |
|
|
|
840 |
|
|
// LOCAL PARAMETER DECLARATION
|
841 |
|
|
parameter delay = (lpm_delay < 2) ? 1 : lpm_delay-1;
|
842 |
|
|
|
843 |
|
|
// INPUT PORT DECLARATION
|
844 |
|
|
input [lpm_width-1:0] d;
|
845 |
|
|
input clock;
|
846 |
|
|
input aclr;
|
847 |
|
|
|
848 |
|
|
// OUTPUT PORT DECLARATION
|
849 |
|
|
output [lpm_width-1:0] q;
|
850 |
|
|
|
851 |
|
|
// INTERNAL REGISTERS DECLARATION
|
852 |
|
|
reg [(lpm_width*delay)-1:0] dffpipe;
|
853 |
|
|
reg [lpm_width-1:0] q;
|
854 |
|
|
|
855 |
|
|
// LOCAL INTEGER DECLARATION
|
856 |
|
|
|
857 |
|
|
// INITIAL CONSTRUCT BLOCK
|
858 |
|
|
initial
|
859 |
|
|
begin
|
860 |
|
|
dffpipe = {(lpm_width*delay){1'b0}};
|
861 |
|
|
q <= 0;
|
862 |
|
|
end
|
863 |
|
|
|
864 |
|
|
// ALWAYS CONSTRUCT BLOCK
|
865 |
|
|
always @(posedge clock or posedge aclr)
|
866 |
|
|
begin
|
867 |
|
|
if (aclr)
|
868 |
|
|
begin
|
869 |
|
|
dffpipe <= {(lpm_width*delay){1'b0}};
|
870 |
|
|
q <= 0;
|
871 |
|
|
end
|
872 |
|
|
else
|
873 |
|
|
begin
|
874 |
|
|
if ((lpm_delay > 0) && ($time > 0))
|
875 |
|
|
begin
|
876 |
|
|
if (lpm_delay > 1)
|
877 |
|
|
begin
|
878 |
|
|
{q, dffpipe} <= {dffpipe, d};
|
879 |
|
|
end
|
880 |
|
|
else
|
881 |
|
|
q <= d;
|
882 |
|
|
end
|
883 |
|
|
end
|
884 |
|
|
end // @(posedge aclr or posedge clock)
|
885 |
|
|
|
886 |
|
|
always @(d)
|
887 |
|
|
begin
|
888 |
|
|
if (lpm_delay == 0)
|
889 |
|
|
q <= d;
|
890 |
|
|
end // @(d)
|
891 |
|
|
|
892 |
|
|
endmodule // dcfifo_dffpipe
|
893 |
|
|
// END OF MODULE
|
894 |
|
|
|
895 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
896 |
|
|
//
|
897 |
|
|
// Module Name : dcfifo_fefifo
|
898 |
|
|
//
|
899 |
|
|
// Description : Dual Clock FIFO
|
900 |
|
|
//
|
901 |
|
|
// Limitation :
|
902 |
|
|
//
|
903 |
|
|
// Results expected:
|
904 |
|
|
//
|
905 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
906 |
|
|
|
907 |
|
|
// BEGINNING OF MODULE
|
908 |
|
|
`timescale 1 ps / 1 ps
|
909 |
|
|
|
910 |
|
|
// MODULE DECLARATION
|
911 |
|
|
module dcfifo_fefifo ( usedw_in, wreq, rreq, clock, aclr,
|
912 |
|
|
empty, full);
|
913 |
|
|
|
914 |
|
|
// GLOBAL PARAMETER DECLARATION
|
915 |
|
|
parameter lpm_widthad = 1;
|
916 |
|
|
parameter lpm_numwords = 1;
|
917 |
|
|
parameter underflow_checking = "ON";
|
918 |
|
|
parameter overflow_checking = "ON";
|
919 |
|
|
parameter lpm_mode = "READ";
|
920 |
|
|
|
921 |
|
|
// INPUT PORT DECLARATION
|
922 |
|
|
input [lpm_widthad-1:0] usedw_in;
|
923 |
|
|
input wreq, rreq;
|
924 |
|
|
input clock;
|
925 |
|
|
input aclr;
|
926 |
|
|
|
927 |
|
|
// OUTPUT PORT DECLARATION
|
928 |
|
|
output empty, full;
|
929 |
|
|
|
930 |
|
|
// INTERNAL REGISTERS DECLARATION
|
931 |
|
|
reg [1:0] sm_empty;
|
932 |
|
|
reg lrreq;
|
933 |
|
|
reg i_empty, i_full;
|
934 |
|
|
|
935 |
|
|
// LOCAL INTEGER DECLARATION
|
936 |
|
|
integer almostfull;
|
937 |
|
|
|
938 |
|
|
// INITIAL CONSTRUCT BLOCK
|
939 |
|
|
initial
|
940 |
|
|
begin
|
941 |
|
|
if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
|
942 |
|
|
begin
|
943 |
|
|
$display ("Error! LPM_MODE must be READ or WRITE.");
|
944 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
945 |
|
|
end
|
946 |
|
|
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
|
947 |
|
|
begin
|
948 |
|
|
$display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
|
949 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
950 |
|
|
end
|
951 |
|
|
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
|
952 |
|
|
begin
|
953 |
|
|
$display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
|
954 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
955 |
|
|
end
|
956 |
|
|
|
957 |
|
|
sm_empty <= 2'b00;
|
958 |
|
|
i_empty <= 1'b1;
|
959 |
|
|
i_full <= 1'b0;
|
960 |
|
|
|
961 |
|
|
if (lpm_numwords >= 3)
|
962 |
|
|
almostfull <= lpm_numwords - 3;
|
963 |
|
|
else
|
964 |
|
|
almostfull <= 0;
|
965 |
|
|
end
|
966 |
|
|
|
967 |
|
|
// ALWAYS CONSTRUCT BLOCK
|
968 |
|
|
always @(posedge aclr)
|
969 |
|
|
begin
|
970 |
|
|
sm_empty <= 2'b00;
|
971 |
|
|
i_empty <= 1'b1;
|
972 |
|
|
i_full <= 1'b0;
|
973 |
|
|
lrreq <= 1'b0;
|
974 |
|
|
end // @(posedge aclr)
|
975 |
|
|
|
976 |
|
|
always @(posedge clock)
|
977 |
|
|
begin
|
978 |
|
|
if (underflow_checking == "OFF")
|
979 |
|
|
lrreq <= rreq;
|
980 |
|
|
else
|
981 |
|
|
lrreq <= rreq && ~i_empty;
|
982 |
|
|
|
983 |
|
|
if (~aclr && $time > 0)
|
984 |
|
|
begin
|
985 |
|
|
if (lpm_mode == "READ")
|
986 |
|
|
begin
|
987 |
|
|
casex (sm_empty)
|
988 |
|
|
// state_empty
|
989 |
|
|
2'b00:
|
990 |
|
|
if (usedw_in != 0)
|
991 |
|
|
sm_empty <= 2'b01;
|
992 |
|
|
// state_non_empty
|
993 |
|
|
2'b01:
|
994 |
|
|
if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
|
995 |
|
|
sm_empty <= 2'b10;
|
996 |
|
|
// state_emptywait
|
997 |
|
|
2'b10:
|
998 |
|
|
if (usedw_in > 1)
|
999 |
|
|
sm_empty <= 2'b01;
|
1000 |
|
|
else
|
1001 |
|
|
sm_empty <= 2'b00;
|
1002 |
|
|
default:
|
1003 |
|
|
$display ("Error! Invalid sm_empty state in read mode.");
|
1004 |
|
|
endcase
|
1005 |
|
|
end // if (lpm_mode == "READ")
|
1006 |
|
|
else if (lpm_mode == "WRITE")
|
1007 |
|
|
begin
|
1008 |
|
|
casex (sm_empty)
|
1009 |
|
|
// state_empty
|
1010 |
|
|
2'b00:
|
1011 |
|
|
if (wreq)
|
1012 |
|
|
sm_empty <= 2'b01;
|
1013 |
|
|
// state_one
|
1014 |
|
|
2'b01:
|
1015 |
|
|
if (!wreq)
|
1016 |
|
|
sm_empty <= 2'b11;
|
1017 |
|
|
// state_non_empty
|
1018 |
|
|
2'b11:
|
1019 |
|
|
if (wreq)
|
1020 |
|
|
sm_empty <= 2'b01;
|
1021 |
|
|
else if (usedw_in == 0)
|
1022 |
|
|
sm_empty <= 2'b00;
|
1023 |
|
|
default:
|
1024 |
|
|
$display ("Error! Invalid sm_empty state in write mode.");
|
1025 |
|
|
endcase
|
1026 |
|
|
end // if (lpm_mode == "WRITE")
|
1027 |
|
|
|
1028 |
|
|
if (~aclr && (usedw_in >= almostfull) && ($time > 0))
|
1029 |
|
|
i_full <= 1'b1;
|
1030 |
|
|
else
|
1031 |
|
|
i_full <= 1'b0;
|
1032 |
|
|
end // if (~aclr && $time > 0)
|
1033 |
|
|
end // @(posedge clock)
|
1034 |
|
|
|
1035 |
|
|
always @(sm_empty)
|
1036 |
|
|
begin
|
1037 |
|
|
i_empty <= !sm_empty[0];
|
1038 |
|
|
end
|
1039 |
|
|
// @(sm_empty)
|
1040 |
|
|
|
1041 |
|
|
// CONTINOUS ASSIGNMENT
|
1042 |
|
|
assign empty = i_empty;
|
1043 |
|
|
assign full = i_full;
|
1044 |
|
|
endmodule // dcfifo_fefifo
|
1045 |
|
|
// END OF MODULE
|
1046 |
|
|
|
1047 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
1048 |
|
|
//
|
1049 |
|
|
// Module Name : dcfifo_async
|
1050 |
|
|
//
|
1051 |
|
|
// Description : Asynchronous Dual Clocks FIFO
|
1052 |
|
|
//
|
1053 |
|
|
// Limitation :
|
1054 |
|
|
//
|
1055 |
|
|
// Results expected:
|
1056 |
|
|
//
|
1057 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
1058 |
|
|
|
1059 |
|
|
// BEGINNING OF MODULE
|
1060 |
|
|
`timescale 1 ps / 1 ps
|
1061 |
|
|
|
1062 |
|
|
// MODULE DECLARATION
|
1063 |
|
|
module dcfifo_async (data, rdclk, wrclk, aclr, rdreq, wrreq,
|
1064 |
|
|
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
|
1065 |
|
|
|
1066 |
|
|
// GLOBAL PARAMETER DECLARATION
|
1067 |
|
|
parameter lpm_width = 1;
|
1068 |
|
|
parameter lpm_widthu = 1;
|
1069 |
|
|
parameter lpm_numwords = 2;
|
1070 |
|
|
parameter delay_rdusedw = 1;
|
1071 |
|
|
parameter delay_wrusedw = 1;
|
1072 |
|
|
parameter rdsync_delaypipe = 0;
|
1073 |
|
|
parameter wrsync_delaypipe = 0;
|
1074 |
|
|
parameter intended_device_family = "Stratix";
|
1075 |
|
|
parameter lpm_showahead = "OFF";
|
1076 |
|
|
parameter underflow_checking = "ON";
|
1077 |
|
|
parameter overflow_checking = "ON";
|
1078 |
|
|
parameter use_eab = "ON";
|
1079 |
|
|
parameter add_ram_output_register = "OFF";
|
1080 |
|
|
|
1081 |
|
|
// INPUT PORT DECLARATION
|
1082 |
|
|
input [lpm_width-1:0] data;
|
1083 |
|
|
input rdclk;
|
1084 |
|
|
input wrclk;
|
1085 |
|
|
input aclr;
|
1086 |
|
|
input wrreq;
|
1087 |
|
|
input rdreq;
|
1088 |
|
|
|
1089 |
|
|
// OUTPUT PORT DECLARATION
|
1090 |
|
|
output rdfull;
|
1091 |
|
|
output wrfull;
|
1092 |
|
|
output rdempty;
|
1093 |
|
|
output wrempty;
|
1094 |
|
|
output [lpm_widthu-1:0] rdusedw;
|
1095 |
|
|
output [lpm_widthu-1:0] wrusedw;
|
1096 |
|
|
output [lpm_width-1:0] q;
|
1097 |
|
|
|
1098 |
|
|
// INTERNAL REGISTERS DECLARATION
|
1099 |
|
|
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
|
1100 |
|
|
reg [lpm_width-1:0] mem_data2 [(1<<lpm_widthu)-1:0];
|
1101 |
|
|
reg data_ready [(1<<lpm_widthu)-1:0];
|
1102 |
|
|
reg [2:0] data_delay_count [(1<<lpm_widthu)-1:0];
|
1103 |
|
|
reg [lpm_width-1:0] i_data_tmp;
|
1104 |
|
|
reg [lpm_widthu-1:0] i_rdptr;
|
1105 |
|
|
reg [lpm_widthu-1:0] i_wrptr;
|
1106 |
|
|
reg [lpm_widthu-1:0] i_wrptr_tmp;
|
1107 |
|
|
reg i_rdenclock;
|
1108 |
|
|
reg i_wren_tmp;
|
1109 |
|
|
reg i_showahead_flag;
|
1110 |
|
|
reg i_showahead_flag1;
|
1111 |
|
|
reg i_showahead_flag2;
|
1112 |
|
|
reg i_showahead_flag3;
|
1113 |
|
|
reg [lpm_widthu-1:0] i_wr_udwn;
|
1114 |
|
|
reg [lpm_widthu-1:0] i_rd_udwn;
|
1115 |
|
|
reg [lpm_widthu:0] i_rdusedw;
|
1116 |
|
|
reg [lpm_widthu-1:0] i_wrusedw;
|
1117 |
|
|
reg [lpm_width-1:0] i_q_tmp;
|
1118 |
|
|
reg feature_family_base_stratix;
|
1119 |
|
|
reg feature_family_base_cyclone;
|
1120 |
|
|
|
1121 |
|
|
// INTERNAL WIRE DECLARATION
|
1122 |
|
|
wire i_rden;
|
1123 |
|
|
wire i_wren;
|
1124 |
|
|
wire w_rdempty;
|
1125 |
|
|
wire w_wrempty;
|
1126 |
|
|
wire w_rdfull;
|
1127 |
|
|
wire w_wrfull;
|
1128 |
|
|
wire [lpm_widthu-1:0] w_rdptrrg;
|
1129 |
|
|
wire [lpm_widthu-1:0] w_wrdelaycycle;
|
1130 |
|
|
wire [lpm_widthu-1:0] w_ws_nbrp;
|
1131 |
|
|
wire [lpm_widthu-1:0] w_rs_nbwp;
|
1132 |
|
|
wire [lpm_widthu-1:0] w_ws_dbrp;
|
1133 |
|
|
wire [lpm_widthu-1:0] w_rs_dbwp;
|
1134 |
|
|
wire [lpm_widthu-1:0] w_rd_dbuw;
|
1135 |
|
|
wire [lpm_widthu-1:0] w_wr_dbuw;
|
1136 |
|
|
wire [lpm_widthu-1:0] w_rdusedw;
|
1137 |
|
|
wire [lpm_widthu-1:0] w_wrusedw;
|
1138 |
|
|
|
1139 |
|
|
// INTERNAL TRI DECLARATION
|
1140 |
|
|
tri0 aclr;
|
1141 |
|
|
|
1142 |
|
|
// LOCAL INTEGER DECLARATION
|
1143 |
|
|
integer i;
|
1144 |
|
|
integer j;
|
1145 |
|
|
integer k;
|
1146 |
|
|
|
1147 |
|
|
// COMPONENT INSTANTIATION
|
1148 |
|
|
ALTERA_DEVICE_FAMILIES dev ();
|
1149 |
|
|
|
1150 |
|
|
// INITIAL CONSTRUCT BLOCK
|
1151 |
|
|
initial
|
1152 |
|
|
begin
|
1153 |
|
|
|
1154 |
|
|
feature_family_base_stratix = dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family);
|
1155 |
|
|
feature_family_base_cyclone = dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family);
|
1156 |
|
|
|
1157 |
|
|
if((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
|
1158 |
|
|
$display ("Error! lpm_showahead must be ON or OFF.");
|
1159 |
|
|
if((underflow_checking != "ON") && (underflow_checking != "OFF"))
|
1160 |
|
|
$display ("Error! underflow_checking must be ON or OFF.");
|
1161 |
|
|
if((overflow_checking != "ON") && (overflow_checking != "OFF"))
|
1162 |
|
|
$display ("Error! overflow_checking must be ON or OFF.");
|
1163 |
|
|
if((use_eab != "ON") && (use_eab != "OFF"))
|
1164 |
|
|
$display ("Error! use_eab must be ON or OFF.");
|
1165 |
|
|
if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
|
1166 |
|
|
$display ("Error! add_ram_output_register must be ON or OFF.");
|
1167 |
|
|
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
|
1168 |
|
|
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
|
1169 |
|
|
|
1170 |
|
|
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
|
1171 |
|
|
begin
|
1172 |
|
|
mem_data[i] <= 0;
|
1173 |
|
|
mem_data2[i] <= 0;
|
1174 |
|
|
data_ready[i] <= 1'b0;
|
1175 |
|
|
data_delay_count[i] <= 0;
|
1176 |
|
|
end
|
1177 |
|
|
|
1178 |
|
|
if ((add_ram_output_register == "OFF") &&
|
1179 |
|
|
((feature_family_base_stratix == 1) || (feature_family_base_cyclone == 1)))
|
1180 |
|
|
begin
|
1181 |
|
|
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
|
1182 |
|
|
begin
|
1183 |
|
|
mem_data2[i] <= {lpm_width{1'bx}};
|
1184 |
|
|
end
|
1185 |
|
|
end
|
1186 |
|
|
else
|
1187 |
|
|
begin
|
1188 |
|
|
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
|
1189 |
|
|
begin
|
1190 |
|
|
mem_data2[i] <= 0;
|
1191 |
|
|
end
|
1192 |
|
|
end
|
1193 |
|
|
|
1194 |
|
|
i_data_tmp <= 0;
|
1195 |
|
|
i_rdptr <= 0;
|
1196 |
|
|
i_wrptr <= 0;
|
1197 |
|
|
i_wrptr_tmp <= 0;
|
1198 |
|
|
i_wren_tmp <= 0;
|
1199 |
|
|
i_wr_udwn <= 0;
|
1200 |
|
|
i_rd_udwn <= 0;
|
1201 |
|
|
i_rdusedw <= 0;
|
1202 |
|
|
i_wrusedw <= 0;
|
1203 |
|
|
i_q_tmp <= 0;
|
1204 |
|
|
end
|
1205 |
|
|
|
1206 |
|
|
// COMPONENT INSTANTIATIONS
|
1207 |
|
|
// Delays & DFF Pipes
|
1208 |
|
|
dcfifo_dffpipe DP_RDPTR_D (
|
1209 |
|
|
.d (i_rdptr),
|
1210 |
|
|
.clock (i_rdenclock),
|
1211 |
|
|
.aclr (aclr),
|
1212 |
|
|
.q (w_rdptrrg));
|
1213 |
|
|
dcfifo_dffpipe DP_WRPTR_D (
|
1214 |
|
|
.d (i_wrptr),
|
1215 |
|
|
.clock (wrclk),
|
1216 |
|
|
.aclr (aclr),
|
1217 |
|
|
.q (w_wrdelaycycle));
|
1218 |
|
|
defparam
|
1219 |
|
|
DP_RDPTR_D.lpm_delay = 0,
|
1220 |
|
|
DP_RDPTR_D.lpm_width = lpm_widthu,
|
1221 |
|
|
DP_WRPTR_D.lpm_delay = 1,
|
1222 |
|
|
DP_WRPTR_D.lpm_width = lpm_widthu;
|
1223 |
|
|
|
1224 |
|
|
dcfifo_dffpipe DP_WS_NBRP (
|
1225 |
|
|
.d (w_rdptrrg),
|
1226 |
|
|
.clock (wrclk),
|
1227 |
|
|
.aclr (aclr),
|
1228 |
|
|
.q (w_ws_nbrp));
|
1229 |
|
|
dcfifo_dffpipe DP_RS_NBWP (
|
1230 |
|
|
.d (w_wrdelaycycle),
|
1231 |
|
|
.clock (rdclk),
|
1232 |
|
|
.aclr (aclr),
|
1233 |
|
|
.q (w_rs_nbwp));
|
1234 |
|
|
dcfifo_dffpipe DP_WS_DBRP (
|
1235 |
|
|
.d (w_ws_nbrp),
|
1236 |
|
|
.clock (wrclk),
|
1237 |
|
|
.aclr (aclr),
|
1238 |
|
|
.q (w_ws_dbrp));
|
1239 |
|
|
dcfifo_dffpipe DP_RS_DBWP (
|
1240 |
|
|
.d (w_rs_nbwp),
|
1241 |
|
|
.clock (rdclk),
|
1242 |
|
|
.aclr (aclr),
|
1243 |
|
|
.q (w_rs_dbwp));
|
1244 |
|
|
defparam
|
1245 |
|
|
DP_WS_NBRP.lpm_delay = wrsync_delaypipe,
|
1246 |
|
|
DP_WS_NBRP.lpm_width = lpm_widthu,
|
1247 |
|
|
DP_RS_NBWP.lpm_delay = rdsync_delaypipe,
|
1248 |
|
|
DP_RS_NBWP.lpm_width = lpm_widthu,
|
1249 |
|
|
DP_WS_DBRP.lpm_delay = 1, // gray_delaypipe
|
1250 |
|
|
DP_WS_DBRP.lpm_width = lpm_widthu,
|
1251 |
|
|
DP_RS_DBWP.lpm_delay = 1, // gray_delaypipe
|
1252 |
|
|
DP_RS_DBWP.lpm_width = lpm_widthu;
|
1253 |
|
|
|
1254 |
|
|
dcfifo_dffpipe DP_WRUSEDW (
|
1255 |
|
|
.d (i_wr_udwn),
|
1256 |
|
|
.clock (wrclk),
|
1257 |
|
|
.aclr (aclr),
|
1258 |
|
|
.q (w_wrusedw));
|
1259 |
|
|
dcfifo_dffpipe DP_RDUSEDW (
|
1260 |
|
|
.d (i_rd_udwn),
|
1261 |
|
|
.clock (rdclk),
|
1262 |
|
|
.aclr (aclr),
|
1263 |
|
|
.q (w_rdusedw));
|
1264 |
|
|
dcfifo_dffpipe DP_WR_DBUW (
|
1265 |
|
|
.d (i_wr_udwn),
|
1266 |
|
|
.clock (wrclk),
|
1267 |
|
|
.aclr (aclr),
|
1268 |
|
|
.q (w_wr_dbuw));
|
1269 |
|
|
dcfifo_dffpipe DP_RD_DBUW (
|
1270 |
|
|
.d (i_rd_udwn),
|
1271 |
|
|
.clock (rdclk),
|
1272 |
|
|
.aclr (aclr),
|
1273 |
|
|
.q (w_rd_dbuw));
|
1274 |
|
|
defparam
|
1275 |
|
|
DP_WRUSEDW.lpm_delay = delay_wrusedw,
|
1276 |
|
|
DP_WRUSEDW.lpm_width = lpm_widthu,
|
1277 |
|
|
DP_RDUSEDW.lpm_delay = delay_rdusedw,
|
1278 |
|
|
DP_RDUSEDW.lpm_width = lpm_widthu,
|
1279 |
|
|
DP_WR_DBUW.lpm_delay = 1, // wrusedw_delaypipe
|
1280 |
|
|
DP_WR_DBUW.lpm_width = lpm_widthu,
|
1281 |
|
|
DP_RD_DBUW.lpm_delay = 1, // rdusedw_delaypipe
|
1282 |
|
|
DP_RD_DBUW.lpm_width = lpm_widthu;
|
1283 |
|
|
|
1284 |
|
|
// Empty/Full
|
1285 |
|
|
dcfifo_fefifo WR_FE (
|
1286 |
|
|
.usedw_in (w_wr_dbuw),
|
1287 |
|
|
.wreq (wrreq),
|
1288 |
|
|
.rreq (rdreq),
|
1289 |
|
|
.clock (wrclk),
|
1290 |
|
|
.aclr (aclr),
|
1291 |
|
|
.empty (w_wrempty),
|
1292 |
|
|
.full (w_wrfull));
|
1293 |
|
|
dcfifo_fefifo RD_FE (
|
1294 |
|
|
.usedw_in (w_rd_dbuw),
|
1295 |
|
|
.rreq (rdreq),
|
1296 |
|
|
.wreq(wrreq),
|
1297 |
|
|
.clock (rdclk),
|
1298 |
|
|
.aclr (aclr),
|
1299 |
|
|
.empty (w_rdempty),
|
1300 |
|
|
.full (w_rdfull));
|
1301 |
|
|
defparam
|
1302 |
|
|
WR_FE.lpm_widthad = lpm_widthu,
|
1303 |
|
|
WR_FE.lpm_numwords = lpm_numwords,
|
1304 |
|
|
WR_FE.underflow_checking = underflow_checking,
|
1305 |
|
|
WR_FE.overflow_checking = overflow_checking,
|
1306 |
|
|
WR_FE.lpm_mode = "WRITE",
|
1307 |
|
|
RD_FE.lpm_widthad = lpm_widthu,
|
1308 |
|
|
RD_FE.lpm_numwords = lpm_numwords,
|
1309 |
|
|
RD_FE.underflow_checking = underflow_checking,
|
1310 |
|
|
RD_FE.overflow_checking = overflow_checking,
|
1311 |
|
|
RD_FE.lpm_mode = "READ";
|
1312 |
|
|
|
1313 |
|
|
// ALWAYS CONSTRUCT BLOCK
|
1314 |
|
|
always @(posedge aclr)
|
1315 |
|
|
begin
|
1316 |
|
|
i_rdptr <= 0;
|
1317 |
|
|
i_wrptr <= 0;
|
1318 |
|
|
if (!((feature_family_base_stratix == 1) ||
|
1319 |
|
|
(feature_family_base_cyclone == 1)) ||
|
1320 |
|
|
(use_eab == "OFF"))
|
1321 |
|
|
begin
|
1322 |
|
|
if (lpm_showahead == "ON")
|
1323 |
|
|
i_q_tmp <= mem_data[0];
|
1324 |
|
|
else
|
1325 |
|
|
i_q_tmp <= 0;
|
1326 |
|
|
end
|
1327 |
|
|
else if ((add_ram_output_register == "ON") &&
|
1328 |
|
|
((feature_family_base_stratix == 1) ||
|
1329 |
|
|
(feature_family_base_cyclone == 1)))
|
1330 |
|
|
begin
|
1331 |
|
|
if (lpm_showahead == "OFF")
|
1332 |
|
|
i_q_tmp <= 0;
|
1333 |
|
|
else
|
1334 |
|
|
begin
|
1335 |
|
|
i_q_tmp <= {lpm_width{1'bx}};
|
1336 |
|
|
|
1337 |
|
|
for (j = 0; j < (1<<lpm_widthu); j = j + 1)
|
1338 |
|
|
begin
|
1339 |
|
|
data_ready[i_wrptr_tmp] <= 1'b0;
|
1340 |
|
|
data_delay_count[k] <= 0;
|
1341 |
|
|
end
|
1342 |
|
|
end
|
1343 |
|
|
end
|
1344 |
|
|
end // @(posedge aclr)
|
1345 |
|
|
|
1346 |
|
|
always @(posedge wrclk)
|
1347 |
|
|
begin
|
1348 |
|
|
if (aclr && (!((feature_family_base_stratix == 1) ||
|
1349 |
|
|
(feature_family_base_cyclone == 1)) ||
|
1350 |
|
|
(add_ram_output_register == "ON") || (use_eab == "OFF")))
|
1351 |
|
|
begin
|
1352 |
|
|
i_data_tmp <= 0;
|
1353 |
|
|
i_wrptr_tmp <= 0;
|
1354 |
|
|
i_wren_tmp <= 0;
|
1355 |
|
|
end
|
1356 |
|
|
else if (wrclk && ($time > 0))
|
1357 |
|
|
begin
|
1358 |
|
|
i_data_tmp <= data;
|
1359 |
|
|
i_wrptr_tmp <= i_wrptr;
|
1360 |
|
|
i_wren_tmp <= i_wren;
|
1361 |
|
|
|
1362 |
|
|
if (i_wren)
|
1363 |
|
|
begin
|
1364 |
|
|
if (~aclr && ((i_wrptr < (1<<lpm_widthu)-1) || (overflow_checking == "OFF")))
|
1365 |
|
|
i_wrptr <= i_wrptr + 1;
|
1366 |
|
|
else
|
1367 |
|
|
i_wrptr <= 0;
|
1368 |
|
|
|
1369 |
|
|
if (use_eab == "OFF")
|
1370 |
|
|
begin
|
1371 |
|
|
mem_data[i_wrptr] <= data;
|
1372 |
|
|
|
1373 |
|
|
if (lpm_showahead == "ON")
|
1374 |
|
|
i_showahead_flag3 <= 1'b1;
|
1375 |
|
|
end
|
1376 |
|
|
end
|
1377 |
|
|
end
|
1378 |
|
|
end // @(posedge wrclk)
|
1379 |
|
|
|
1380 |
|
|
always @(negedge wrclk)
|
1381 |
|
|
begin
|
1382 |
|
|
if ((~wrclk && (use_eab == "ON")) && ($time > 0))
|
1383 |
|
|
begin
|
1384 |
|
|
if (i_wren_tmp)
|
1385 |
|
|
begin
|
1386 |
|
|
mem_data[i_wrptr_tmp] <= i_data_tmp;
|
1387 |
|
|
data_ready[i_wrptr_tmp] <= 1'b0;
|
1388 |
|
|
end
|
1389 |
|
|
|
1390 |
|
|
if ((lpm_showahead == "ON") &&
|
1391 |
|
|
(!((feature_family_base_stratix == 1) ||
|
1392 |
|
|
(feature_family_base_cyclone == 1))))
|
1393 |
|
|
i_showahead_flag3 <= 1'b1;
|
1394 |
|
|
end
|
1395 |
|
|
end // @(negedge wrclk)
|
1396 |
|
|
|
1397 |
|
|
always @(posedge rdclk)
|
1398 |
|
|
begin
|
1399 |
|
|
|
1400 |
|
|
if (rdclk && ($time > 0))
|
1401 |
|
|
begin
|
1402 |
|
|
if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") &&
|
1403 |
|
|
((feature_family_base_stratix == 1) ||
|
1404 |
|
|
(feature_family_base_cyclone == 1)))
|
1405 |
|
|
begin
|
1406 |
|
|
for (k = 0; k < (1<<lpm_widthu); k = k + 1)
|
1407 |
|
|
begin
|
1408 |
|
|
if (data_ready[k] == 1'b0)
|
1409 |
|
|
data_delay_count[k] <= data_delay_count[k] + 1;
|
1410 |
|
|
|
1411 |
|
|
if (data_delay_count[k] == (rdsync_delaypipe+2))
|
1412 |
|
|
begin
|
1413 |
|
|
data_ready[k] <= 1'b1;
|
1414 |
|
|
data_delay_count[k] <= 0;
|
1415 |
|
|
end
|
1416 |
|
|
end
|
1417 |
|
|
|
1418 |
|
|
if (~aclr)
|
1419 |
|
|
begin
|
1420 |
|
|
i_showahead_flag3 <= 1'b1;
|
1421 |
|
|
end
|
1422 |
|
|
end
|
1423 |
|
|
|
1424 |
|
|
end
|
1425 |
|
|
|
1426 |
|
|
if (aclr && (!((feature_family_base_stratix == 1) ||
|
1427 |
|
|
(feature_family_base_cyclone == 1)) ||
|
1428 |
|
|
(use_eab == "OFF")))
|
1429 |
|
|
begin
|
1430 |
|
|
if (lpm_showahead == "ON")
|
1431 |
|
|
i_q_tmp <= mem_data[0];
|
1432 |
|
|
else
|
1433 |
|
|
i_q_tmp <= 0;
|
1434 |
|
|
end
|
1435 |
|
|
else if (aclr && (add_ram_output_register == "ON") &&
|
1436 |
|
|
((feature_family_base_stratix == 1) ||
|
1437 |
|
|
(feature_family_base_cyclone == 1)))
|
1438 |
|
|
begin
|
1439 |
|
|
if (lpm_showahead == "ON")
|
1440 |
|
|
i_q_tmp <= {lpm_width{1'bx}};
|
1441 |
|
|
else
|
1442 |
|
|
i_q_tmp <= 0;
|
1443 |
|
|
end
|
1444 |
|
|
else if (rdclk && i_rden && ($time > 0))
|
1445 |
|
|
begin
|
1446 |
|
|
if (~aclr && ((i_rdptr < (1<<lpm_widthu)-1) || (underflow_checking == "OFF")))
|
1447 |
|
|
i_rdptr <= i_rdptr + 1;
|
1448 |
|
|
else
|
1449 |
|
|
i_rdptr <= 0;
|
1450 |
|
|
|
1451 |
|
|
if (lpm_showahead == "ON")
|
1452 |
|
|
i_showahead_flag3 <= 1'b1;
|
1453 |
|
|
else
|
1454 |
|
|
i_q_tmp <= mem_data[i_rdptr];
|
1455 |
|
|
end
|
1456 |
|
|
end // @(posedge rdclk)
|
1457 |
|
|
|
1458 |
|
|
always @(i_showahead_flag3)
|
1459 |
|
|
begin
|
1460 |
|
|
i_showahead_flag2 <= i_showahead_flag3;
|
1461 |
|
|
end
|
1462 |
|
|
|
1463 |
|
|
always @(i_showahead_flag2)
|
1464 |
|
|
begin
|
1465 |
|
|
i_showahead_flag1 <= i_showahead_flag2;
|
1466 |
|
|
end
|
1467 |
|
|
|
1468 |
|
|
always @(i_showahead_flag1)
|
1469 |
|
|
begin
|
1470 |
|
|
i_showahead_flag <= i_showahead_flag1;
|
1471 |
|
|
end
|
1472 |
|
|
|
1473 |
|
|
|
1474 |
|
|
always @(posedge i_showahead_flag)
|
1475 |
|
|
begin
|
1476 |
|
|
if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") &&
|
1477 |
|
|
((feature_family_base_stratix == 1) ||
|
1478 |
|
|
(feature_family_base_cyclone == 1)))
|
1479 |
|
|
begin
|
1480 |
|
|
if (w_rdempty == 1'b0)
|
1481 |
|
|
begin
|
1482 |
|
|
if (data_ready[i_rdptr] == 1'b1)
|
1483 |
|
|
begin
|
1484 |
|
|
i_q_tmp <= mem_data[i_rdptr];
|
1485 |
|
|
mem_data2[i_rdptr] <= mem_data[i_rdptr];
|
1486 |
|
|
end
|
1487 |
|
|
else
|
1488 |
|
|
i_q_tmp <= mem_data2[i_rdptr];
|
1489 |
|
|
end
|
1490 |
|
|
end
|
1491 |
|
|
else
|
1492 |
|
|
i_q_tmp <= mem_data[i_rdptr];
|
1493 |
|
|
i_showahead_flag3 <= 1'b0;
|
1494 |
|
|
end // @(posedge i_showahead_flag)
|
1495 |
|
|
|
1496 |
|
|
// Delays & DFF Pipes
|
1497 |
|
|
always @(negedge rdclk)
|
1498 |
|
|
begin
|
1499 |
|
|
i_rdenclock <= 0;
|
1500 |
|
|
end // @(negedge rdclk)
|
1501 |
|
|
|
1502 |
|
|
always @(posedge rdclk)
|
1503 |
|
|
begin
|
1504 |
|
|
if (i_rden)
|
1505 |
|
|
i_rdenclock <= 1;
|
1506 |
|
|
end // @(posedge rdclk)
|
1507 |
|
|
|
1508 |
|
|
always @(i_wrptr or w_ws_dbrp)
|
1509 |
|
|
begin
|
1510 |
|
|
i_wr_udwn = i_wrptr - w_ws_dbrp;
|
1511 |
|
|
end // @(i_wrptr or w_ws_dbrp)
|
1512 |
|
|
|
1513 |
|
|
always @(i_rdptr or w_rs_dbwp)
|
1514 |
|
|
begin
|
1515 |
|
|
i_rd_udwn = w_rs_dbwp - i_rdptr;
|
1516 |
|
|
end // @(i_rdptr or w_rs_dbwp)
|
1517 |
|
|
|
1518 |
|
|
|
1519 |
|
|
// CONTINOUS ASSIGNMENT
|
1520 |
|
|
assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !w_rdempty);
|
1521 |
|
|
assign i_wren = (overflow_checking == "OFF") ? wrreq : (wrreq && !w_wrfull);
|
1522 |
|
|
assign q = i_q_tmp;
|
1523 |
|
|
assign wrfull = w_wrfull;
|
1524 |
|
|
assign rdfull = w_rdfull;
|
1525 |
|
|
assign wrempty = w_wrempty;
|
1526 |
|
|
assign rdempty = w_rdempty;
|
1527 |
|
|
assign wrusedw = w_wrusedw;
|
1528 |
|
|
assign rdusedw = w_rdusedw;
|
1529 |
|
|
|
1530 |
|
|
endmodule // dcfifo_async
|
1531 |
|
|
// END OF MODULE
|
1532 |
|
|
|
1533 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
1534 |
|
|
//
|
1535 |
|
|
// Module Name : dcfifo_sync
|
1536 |
|
|
//
|
1537 |
|
|
// Description : Synchronous Dual Clock FIFO
|
1538 |
|
|
//
|
1539 |
|
|
// Limitation :
|
1540 |
|
|
//
|
1541 |
|
|
// Results expected:
|
1542 |
|
|
//
|
1543 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
1544 |
|
|
|
1545 |
|
|
// BEGINNING OF MODULE
|
1546 |
|
|
`timescale 1 ps / 1 ps
|
1547 |
|
|
|
1548 |
|
|
// MODULE DECLARATION
|
1549 |
|
|
module dcfifo_sync (data, rdclk, wrclk, aclr, rdreq, wrreq,
|
1550 |
|
|
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
|
1551 |
|
|
|
1552 |
|
|
// GLOBAL PARAMETER DECLARATION
|
1553 |
|
|
parameter lpm_width = 1;
|
1554 |
|
|
parameter lpm_widthu = 1;
|
1555 |
|
|
parameter lpm_numwords = 2;
|
1556 |
|
|
parameter intended_device_family = "Stratix";
|
1557 |
|
|
parameter lpm_showahead = "OFF";
|
1558 |
|
|
parameter underflow_checking = "ON";
|
1559 |
|
|
parameter overflow_checking = "ON";
|
1560 |
|
|
parameter use_eab = "ON";
|
1561 |
|
|
parameter add_ram_output_register = "OFF";
|
1562 |
|
|
|
1563 |
|
|
// INPUT PORT DECLARATION
|
1564 |
|
|
input [lpm_width-1:0] data;
|
1565 |
|
|
input rdclk;
|
1566 |
|
|
input wrclk;
|
1567 |
|
|
input aclr;
|
1568 |
|
|
input rdreq;
|
1569 |
|
|
input wrreq;
|
1570 |
|
|
|
1571 |
|
|
// OUTPUT PORT DECLARATION
|
1572 |
|
|
output rdfull;
|
1573 |
|
|
output wrfull;
|
1574 |
|
|
output rdempty;
|
1575 |
|
|
output wrempty;
|
1576 |
|
|
output [lpm_widthu-1:0] rdusedw;
|
1577 |
|
|
output [lpm_widthu-1:0] wrusedw;
|
1578 |
|
|
output [lpm_width-1:0] q;
|
1579 |
|
|
|
1580 |
|
|
// INTERNAL REGISTERS DECLARATION
|
1581 |
|
|
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
|
1582 |
|
|
reg [lpm_width-1:0] i_data_tmp;
|
1583 |
|
|
reg [lpm_widthu:0] i_rdptr;
|
1584 |
|
|
reg [lpm_widthu:0] i_wrptr;
|
1585 |
|
|
reg [lpm_widthu-1:0] i_wrptr_tmp;
|
1586 |
|
|
reg i_wren_tmp;
|
1587 |
|
|
reg i_showahead_flag;
|
1588 |
|
|
reg i_showahead_flag2;
|
1589 |
|
|
reg [lpm_widthu:0] i_rdusedw;
|
1590 |
|
|
reg [lpm_widthu:0] i_wrusedw;
|
1591 |
|
|
reg [lpm_width-1:0] i_q_tmp;
|
1592 |
|
|
reg feature_family_base_stratix;
|
1593 |
|
|
reg feature_family_base_cyclone;
|
1594 |
|
|
reg feature_family_stratixii;
|
1595 |
|
|
reg feature_family_cycloneii;
|
1596 |
|
|
|
1597 |
|
|
// INTERNAL WIRE DECLARATION
|
1598 |
|
|
wire [lpm_widthu:0] w_rdptr_s;
|
1599 |
|
|
wire [lpm_widthu:0] w_wrptr_s;
|
1600 |
|
|
wire [lpm_widthu:0] w_wrptr_r;
|
1601 |
|
|
wire i_rden;
|
1602 |
|
|
wire i_wren;
|
1603 |
|
|
wire i_rdempty;
|
1604 |
|
|
wire i_wrempty;
|
1605 |
|
|
wire i_rdfull;
|
1606 |
|
|
wire i_wrfull;
|
1607 |
|
|
|
1608 |
|
|
// LOCAL INTEGER DECLARATION
|
1609 |
|
|
integer cnt_mod;
|
1610 |
|
|
integer i;
|
1611 |
|
|
|
1612 |
|
|
// COMPONENT INSTANTIATION
|
1613 |
|
|
ALTERA_DEVICE_FAMILIES dev ();
|
1614 |
|
|
|
1615 |
|
|
// INITIAL CONSTRUCT BLOCK
|
1616 |
|
|
initial
|
1617 |
|
|
begin
|
1618 |
|
|
|
1619 |
|
|
feature_family_base_stratix = dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family);
|
1620 |
|
|
feature_family_base_cyclone = dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family);
|
1621 |
|
|
feature_family_stratixii = dev.FEATURE_FAMILY_STRATIXII(intended_device_family);
|
1622 |
|
|
feature_family_cycloneii = dev.FEATURE_FAMILY_CYCLONEII(intended_device_family);
|
1623 |
|
|
|
1624 |
|
|
if ((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
|
1625 |
|
|
$display ("Error! LPM_SHOWAHEAD must be ON or OFF.");
|
1626 |
|
|
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
|
1627 |
|
|
$display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
|
1628 |
|
|
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
|
1629 |
|
|
$display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
|
1630 |
|
|
if ((use_eab != "ON") && (use_eab != "OFF"))
|
1631 |
|
|
$display ("Error! USE_EAB must be ON or OFF.");
|
1632 |
|
|
if (lpm_numwords > (1 << lpm_widthu))
|
1633 |
|
|
$display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
|
1634 |
|
|
if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
|
1635 |
|
|
$display ("Error! add_ram_output_register must be ON or OFF.");
|
1636 |
|
|
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
|
1637 |
|
|
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
|
1638 |
|
|
|
1639 |
|
|
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
|
1640 |
|
|
mem_data[i] <= 0;
|
1641 |
|
|
i_data_tmp <= 0;
|
1642 |
|
|
i_rdptr <= 0;
|
1643 |
|
|
i_wrptr <= 0;
|
1644 |
|
|
i_wrptr_tmp <= 0;
|
1645 |
|
|
i_wren_tmp <= 0;
|
1646 |
|
|
|
1647 |
|
|
i_rdusedw <= 0;
|
1648 |
|
|
i_wrusedw <= 0;
|
1649 |
|
|
i_q_tmp <= 0;
|
1650 |
|
|
|
1651 |
|
|
if (lpm_numwords == (1 << lpm_widthu))
|
1652 |
|
|
cnt_mod <= 1 << (lpm_widthu + 1);
|
1653 |
|
|
else
|
1654 |
|
|
cnt_mod <= 1 << lpm_widthu;
|
1655 |
|
|
end
|
1656 |
|
|
|
1657 |
|
|
// COMPONENT INSTANTIATIONS
|
1658 |
|
|
dcfifo_dffpipe RDPTR_D (
|
1659 |
|
|
.d (i_rdptr),
|
1660 |
|
|
.clock (wrclk),
|
1661 |
|
|
.aclr (aclr),
|
1662 |
|
|
.q (w_rdptr_s));
|
1663 |
|
|
dcfifo_dffpipe WRPTR_D (
|
1664 |
|
|
.d (i_wrptr),
|
1665 |
|
|
.clock (wrclk),
|
1666 |
|
|
.aclr (aclr),
|
1667 |
|
|
.q (w_wrptr_r));
|
1668 |
|
|
dcfifo_dffpipe WRPTR_E (
|
1669 |
|
|
.d (w_wrptr_r),
|
1670 |
|
|
.clock (rdclk),
|
1671 |
|
|
.aclr (aclr),
|
1672 |
|
|
.q (w_wrptr_s));
|
1673 |
|
|
defparam
|
1674 |
|
|
RDPTR_D.lpm_delay = 1,
|
1675 |
|
|
RDPTR_D.lpm_width = lpm_widthu + 1,
|
1676 |
|
|
WRPTR_D.lpm_delay = 1,
|
1677 |
|
|
WRPTR_D.lpm_width = lpm_widthu + 1,
|
1678 |
|
|
WRPTR_E.lpm_delay = 1,
|
1679 |
|
|
WRPTR_E.lpm_width = lpm_widthu + 1;
|
1680 |
|
|
|
1681 |
|
|
// ALWAYS CONSTRUCT BLOCK
|
1682 |
|
|
always @(posedge aclr)
|
1683 |
|
|
begin
|
1684 |
|
|
i_rdptr <= 0;
|
1685 |
|
|
i_wrptr <= 0;
|
1686 |
|
|
if (!((feature_family_base_stratix == 1) ||
|
1687 |
|
|
(feature_family_base_cyclone == 1)) ||
|
1688 |
|
|
((add_ram_output_register == "ON") && (use_eab == "OFF")))
|
1689 |
|
|
if (lpm_showahead == "ON")
|
1690 |
|
|
begin
|
1691 |
|
|
if ((feature_family_stratixii == 1) ||
|
1692 |
|
|
(feature_family_cycloneii == 1))
|
1693 |
|
|
i_q_tmp <= {lpm_width{1'bX}};
|
1694 |
|
|
else
|
1695 |
|
|
i_q_tmp <= mem_data[0];
|
1696 |
|
|
end
|
1697 |
|
|
else
|
1698 |
|
|
i_q_tmp <= 0;
|
1699 |
|
|
end // @(posedge aclr)
|
1700 |
|
|
|
1701 |
|
|
always @(posedge wrclk)
|
1702 |
|
|
begin
|
1703 |
|
|
if (aclr && (!((feature_family_base_stratix == 1) ||
|
1704 |
|
|
(feature_family_base_cyclone == 1)) ||
|
1705 |
|
|
((add_ram_output_register == "ON") && (use_eab == "OFF"))))
|
1706 |
|
|
begin
|
1707 |
|
|
i_data_tmp <= 0;
|
1708 |
|
|
i_wrptr_tmp <= 0;
|
1709 |
|
|
i_wren_tmp <= 0;
|
1710 |
|
|
end
|
1711 |
|
|
else if (wrclk && ($time > 0))
|
1712 |
|
|
begin
|
1713 |
|
|
i_data_tmp <= data;
|
1714 |
|
|
i_wrptr_tmp <= i_wrptr[lpm_widthu-1:0];
|
1715 |
|
|
i_wren_tmp <= i_wren;
|
1716 |
|
|
|
1717 |
|
|
if (i_wren)
|
1718 |
|
|
begin
|
1719 |
|
|
if (~aclr && (i_wrptr < cnt_mod - 1))
|
1720 |
|
|
i_wrptr <= i_wrptr + 1;
|
1721 |
|
|
else
|
1722 |
|
|
i_wrptr <= 0;
|
1723 |
|
|
|
1724 |
|
|
if (use_eab == "OFF")
|
1725 |
|
|
begin
|
1726 |
|
|
mem_data[i_wrptr[lpm_widthu-1:0]] <= data;
|
1727 |
|
|
|
1728 |
|
|
if (lpm_showahead == "ON")
|
1729 |
|
|
i_showahead_flag2 <= 1'b1;
|
1730 |
|
|
end
|
1731 |
|
|
end
|
1732 |
|
|
end
|
1733 |
|
|
end // @(posedge wrclk)
|
1734 |
|
|
|
1735 |
|
|
always @(negedge wrclk)
|
1736 |
|
|
begin
|
1737 |
|
|
if ((~wrclk && (use_eab == "ON")) && ($time > 0))
|
1738 |
|
|
begin
|
1739 |
|
|
if (i_wren_tmp)
|
1740 |
|
|
begin
|
1741 |
|
|
mem_data[i_wrptr_tmp] <= i_data_tmp;
|
1742 |
|
|
end
|
1743 |
|
|
|
1744 |
|
|
if ((lpm_showahead == "ON") &&
|
1745 |
|
|
(!((feature_family_base_stratix == 1) ||
|
1746 |
|
|
(feature_family_base_cyclone == 1))))
|
1747 |
|
|
i_showahead_flag2 <= 1'b1;
|
1748 |
|
|
end
|
1749 |
|
|
end // @(negedge wrclk)
|
1750 |
|
|
|
1751 |
|
|
always @(posedge rdclk)
|
1752 |
|
|
begin
|
1753 |
|
|
if (aclr && (!((feature_family_base_stratix == 1) ||
|
1754 |
|
|
(feature_family_base_cyclone == 1)) ||
|
1755 |
|
|
((add_ram_output_register == "ON") && (use_eab == "OFF"))))
|
1756 |
|
|
begin
|
1757 |
|
|
if (lpm_showahead == "ON")
|
1758 |
|
|
begin
|
1759 |
|
|
if ((feature_family_stratixii == 1) ||
|
1760 |
|
|
(feature_family_cycloneii == 1))
|
1761 |
|
|
i_q_tmp <= {lpm_width{1'bX}};
|
1762 |
|
|
else
|
1763 |
|
|
i_q_tmp <= mem_data[0];
|
1764 |
|
|
end
|
1765 |
|
|
else
|
1766 |
|
|
i_q_tmp <= 0;
|
1767 |
|
|
end
|
1768 |
|
|
else if (rdclk && i_rden && ($time > 0))
|
1769 |
|
|
begin
|
1770 |
|
|
if (~aclr && (i_rdptr < cnt_mod - 1))
|
1771 |
|
|
i_rdptr <= i_rdptr + 1;
|
1772 |
|
|
else
|
1773 |
|
|
i_rdptr <= 0;
|
1774 |
|
|
|
1775 |
|
|
if ((lpm_showahead == "ON") && (!((use_eab == "ON") &&
|
1776 |
|
|
((feature_family_base_stratix == 1) ||
|
1777 |
|
|
(feature_family_base_cyclone == 1)))))
|
1778 |
|
|
i_showahead_flag2 <= 1'b1;
|
1779 |
|
|
else
|
1780 |
|
|
i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
|
1781 |
|
|
end
|
1782 |
|
|
end // @(rdclk)
|
1783 |
|
|
|
1784 |
|
|
always @(posedge i_showahead_flag)
|
1785 |
|
|
begin
|
1786 |
|
|
i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
|
1787 |
|
|
i_showahead_flag2 <= 1'b0;
|
1788 |
|
|
end // @(posedge i_showahead_flag)
|
1789 |
|
|
|
1790 |
|
|
always @(i_showahead_flag2)
|
1791 |
|
|
begin
|
1792 |
|
|
i_showahead_flag <= i_showahead_flag2;
|
1793 |
|
|
end // @(i_showahead_flag2)
|
1794 |
|
|
|
1795 |
|
|
// Usedw, Empty, Full
|
1796 |
|
|
always @(i_rdptr or w_wrptr_s or cnt_mod)
|
1797 |
|
|
begin
|
1798 |
|
|
if (w_wrptr_s >= i_rdptr)
|
1799 |
|
|
i_rdusedw <= w_wrptr_s - i_rdptr;
|
1800 |
|
|
else
|
1801 |
|
|
i_rdusedw <= w_wrptr_s + cnt_mod - i_rdptr;
|
1802 |
|
|
end // @(i_rdptr or w_wrptr_s)
|
1803 |
|
|
|
1804 |
|
|
always @(i_wrptr or w_rdptr_s or cnt_mod)
|
1805 |
|
|
begin
|
1806 |
|
|
if (i_wrptr >= w_rdptr_s)
|
1807 |
|
|
i_wrusedw <= i_wrptr - w_rdptr_s;
|
1808 |
|
|
else
|
1809 |
|
|
i_wrusedw <= i_wrptr + cnt_mod - w_rdptr_s;
|
1810 |
|
|
end // @(i_wrptr or w_rdptr_s)
|
1811 |
|
|
|
1812 |
|
|
|
1813 |
|
|
// CONTINOUS ASSIGNMENT
|
1814 |
|
|
assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !i_rdempty);
|
1815 |
|
|
assign i_wren = (overflow_checking == "OFF") ? wrreq : (wrreq && !i_wrfull);
|
1816 |
|
|
assign i_rdempty = (i_rdusedw == 0) ? 1'b1 : 1'b0;
|
1817 |
|
|
assign i_wrempty = (i_wrusedw == 0) ? 1'b1 : 1'b0;
|
1818 |
|
|
assign i_rdfull = (((lpm_numwords == (1 << lpm_widthu)) && i_rdusedw[lpm_widthu]) ||
|
1819 |
|
|
((lpm_numwords < (1 << lpm_widthu)) && (i_rdusedw == lpm_numwords)))
|
1820 |
|
|
? 1'b1 : 1'b0;
|
1821 |
|
|
assign i_wrfull = (((lpm_numwords == (1 << lpm_widthu)) && i_wrusedw[lpm_widthu]) ||
|
1822 |
|
|
((lpm_numwords < (1 << lpm_widthu)) && (i_wrusedw == lpm_numwords)))
|
1823 |
|
|
? 1'b1 : 1'b0;
|
1824 |
|
|
assign rdempty = i_rdempty;
|
1825 |
|
|
assign wrempty = i_wrempty;
|
1826 |
|
|
assign rdfull = i_rdfull;
|
1827 |
|
|
assign wrfull = i_wrfull;
|
1828 |
|
|
assign wrusedw = i_wrusedw[lpm_widthu-1:0];
|
1829 |
|
|
assign rdusedw = i_rdusedw[lpm_widthu-1:0];
|
1830 |
|
|
assign q = i_q_tmp;
|
1831 |
|
|
|
1832 |
|
|
endmodule // dcfifo_sync
|
1833 |
|
|
// END OF MODULE
|
1834 |
|
|
|
1835 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
1836 |
|
|
//
|
1837 |
|
|
// Module Name : dcfifo_low_latency
|
1838 |
|
|
//
|
1839 |
|
|
// Description : Dual Clocks FIFO with lowest latency. This fifo implements
|
1840 |
|
|
// the fifo behavior for Stratix II, Cyclone II, Stratix III,
|
1841 |
|
|
// Cyclone III and Stratix showahead area mode (LPM_SHOWAHEAD=
|
1842 |
|
|
// ON, ADD_RAM_OUTPUT_REGISTER=OFF)
|
1843 |
|
|
//
|
1844 |
|
|
// Limitation :
|
1845 |
|
|
//
|
1846 |
|
|
// Results expected:
|
1847 |
|
|
//
|
1848 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
1849 |
|
|
|
1850 |
|
|
// BEGINNING OF MODULE
|
1851 |
|
|
`timescale 1 ps / 1 ps
|
1852 |
|
|
|
1853 |
|
|
// MODULE DECLARATION
|
1854 |
|
|
module dcfifo_low_latency (data, rdclk, wrclk, aclr, rdreq, wrreq,
|
1855 |
|
|
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
|
1856 |
|
|
|
1857 |
|
|
// GLOBAL PARAMETER DECLARATION
|
1858 |
|
|
parameter lpm_width = 1;
|
1859 |
|
|
parameter lpm_widthu = 1;
|
1860 |
|
|
parameter lpm_width_r = lpm_width;
|
1861 |
|
|
parameter lpm_widthu_r = lpm_widthu;
|
1862 |
|
|
parameter lpm_numwords = 2;
|
1863 |
|
|
parameter delay_rdusedw = 2;
|
1864 |
|
|
parameter delay_wrusedw = 2;
|
1865 |
|
|
parameter rdsync_delaypipe = 0;
|
1866 |
|
|
parameter wrsync_delaypipe = 0;
|
1867 |
|
|
parameter intended_device_family = "Stratix";
|
1868 |
|
|
parameter lpm_showahead = "OFF";
|
1869 |
|
|
parameter underflow_checking = "ON";
|
1870 |
|
|
parameter overflow_checking = "ON";
|
1871 |
|
|
parameter add_usedw_msb_bit = "OFF";
|
1872 |
|
|
parameter write_aclr_synch = "OFF";
|
1873 |
|
|
parameter use_eab = "ON";
|
1874 |
|
|
parameter clocks_are_synchronized = "FALSE";
|
1875 |
|
|
parameter add_ram_output_register = "OFF";
|
1876 |
|
|
parameter lpm_hint = "USE_EAB=ON";
|
1877 |
|
|
|
1878 |
|
|
// LOCAL PARAMETER DECLARATION
|
1879 |
|
|
parameter WIDTH_RATIO = (lpm_width > lpm_width_r) ? lpm_width / lpm_width_r :
|
1880 |
|
|
lpm_width_r / lpm_width;
|
1881 |
|
|
parameter FIFO_DEPTH = (add_usedw_msb_bit == "OFF") ? lpm_widthu_r : lpm_widthu_r -1;
|
1882 |
|
|
|
1883 |
|
|
// INPUT PORT DECLARATION
|
1884 |
|
|
input [lpm_width-1:0] data;
|
1885 |
|
|
input rdclk;
|
1886 |
|
|
input wrclk;
|
1887 |
|
|
input aclr;
|
1888 |
|
|
input rdreq;
|
1889 |
|
|
input wrreq;
|
1890 |
|
|
|
1891 |
|
|
// OUTPUT PORT DECLARATION
|
1892 |
|
|
output rdfull;
|
1893 |
|
|
output wrfull;
|
1894 |
|
|
output rdempty;
|
1895 |
|
|
output wrempty;
|
1896 |
|
|
output [lpm_widthu_r-1:0] rdusedw;
|
1897 |
|
|
output [lpm_widthu-1:0] wrusedw;
|
1898 |
|
|
output [lpm_width_r-1:0] q;
|
1899 |
|
|
|
1900 |
|
|
// INTERNAL REGISTERS DECLARATION
|
1901 |
|
|
reg [lpm_width_r-1:0] mem_data [(1<<FIFO_DEPTH) + WIDTH_RATIO : 0];
|
1902 |
|
|
reg [lpm_width-1:0] i_data_tmp;
|
1903 |
|
|
reg [lpm_width-1:0] i_temp_reg;
|
1904 |
|
|
reg [lpm_widthu_r:0] i_rdptr_g;
|
1905 |
|
|
reg [lpm_widthu:0] i_wrptr_g;
|
1906 |
|
|
reg [lpm_widthu:0] i_wrptr_g_tmp;
|
1907 |
|
|
reg [lpm_widthu:0] i_wrptr_g1;
|
1908 |
|
|
reg [lpm_widthu_r:0] i_rdptr_g1p;
|
1909 |
|
|
reg [lpm_widthu:0] i_delayed_wrptr_g;
|
1910 |
|
|
|
1911 |
|
|
reg i_wren_tmp;
|
1912 |
|
|
reg i_rdempty;
|
1913 |
|
|
reg i_wrempty_area;
|
1914 |
|
|
reg i_wrempty_speed;
|
1915 |
|
|
reg i_rdempty_rreg;
|
1916 |
|
|
reg i_rdfull_speed;
|
1917 |
|
|
reg i_rdfull_area;
|
1918 |
|
|
reg i_wrfull;
|
1919 |
|
|
reg i_wrfull_wreg;
|
1920 |
|
|
reg [lpm_widthu_r:0] i_rdusedw_tmp;
|
1921 |
|
|
reg [lpm_widthu:0] i_wrusedw_tmp;
|
1922 |
|
|
reg [lpm_width_r-1:0] i_q;
|
1923 |
|
|
reg i_q_is_registered;
|
1924 |
|
|
reg use_wrempty_speed;
|
1925 |
|
|
reg use_rdfull_speed;
|
1926 |
|
|
reg sync_aclr_pre;
|
1927 |
|
|
reg sync_aclr;
|
1928 |
|
|
reg is_underflow;
|
1929 |
|
|
reg is_overflow;
|
1930 |
|
|
reg no_warn;
|
1931 |
|
|
reg feature_family_has_stratixiii_style_ram;
|
1932 |
|
|
reg feature_family_has_stratixii_style_ram;
|
1933 |
|
|
reg feature_family_stratixii;
|
1934 |
|
|
reg feature_family_cycloneii;
|
1935 |
|
|
reg feature_family_stratix;
|
1936 |
|
|
|
1937 |
|
|
// INTERNAL WIRE DECLARATION
|
1938 |
|
|
wire [lpm_widthu:0] i_rs_dgwp;
|
1939 |
|
|
wire [lpm_widthu_r:0] i_ws_dgrp;
|
1940 |
|
|
wire [lpm_widthu_r:0] i_rdusedw;
|
1941 |
|
|
wire [lpm_widthu:0] i_wrusedw;
|
1942 |
|
|
wire i_rden;
|
1943 |
|
|
wire i_wren;
|
1944 |
|
|
wire write_aclr;
|
1945 |
|
|
|
1946 |
|
|
// INTERNAL TRI DECLARATION
|
1947 |
|
|
tri0 aclr;
|
1948 |
|
|
|
1949 |
|
|
// LOCAL INTEGER DECLARATION
|
1950 |
|
|
integer cnt_mod;
|
1951 |
|
|
integer cnt_mod_r;
|
1952 |
|
|
integer i;
|
1953 |
|
|
integer i_maximize_speed;
|
1954 |
|
|
integer i_mem_address;
|
1955 |
|
|
integer i_first_bit_position;
|
1956 |
|
|
|
1957 |
|
|
// COMPONENT INSTANTIATION
|
1958 |
|
|
ALTERA_DEVICE_FAMILIES dev ();
|
1959 |
|
|
ALTERA_MF_HINT_EVALUATION eva();
|
1960 |
|
|
|
1961 |
|
|
// FUNCTION DELCRARATION
|
1962 |
|
|
// Convert string to integer
|
1963 |
|
|
function integer str_to_int;
|
1964 |
|
|
input [8*16:1] s;
|
1965 |
|
|
|
1966 |
|
|
reg [8*16:1] reg_s;
|
1967 |
|
|
reg [8:1] digit;
|
1968 |
|
|
reg [8:1] tmp;
|
1969 |
|
|
integer m, ivalue;
|
1970 |
|
|
|
1971 |
|
|
begin
|
1972 |
|
|
ivalue = 0;
|
1973 |
|
|
reg_s = s;
|
1974 |
|
|
for (m=1; m<=16; m=m+1)
|
1975 |
|
|
begin
|
1976 |
|
|
tmp = reg_s[128:121];
|
1977 |
|
|
digit = tmp & 8'b00001111;
|
1978 |
|
|
reg_s = reg_s << 8;
|
1979 |
|
|
ivalue = ivalue * 10 + digit;
|
1980 |
|
|
end
|
1981 |
|
|
str_to_int = ivalue;
|
1982 |
|
|
end
|
1983 |
|
|
endfunction
|
1984 |
|
|
|
1985 |
|
|
// INITIAL CONSTRUCT BLOCK
|
1986 |
|
|
initial
|
1987 |
|
|
begin
|
1988 |
|
|
|
1989 |
|
|
feature_family_has_stratixiii_style_ram = dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family);
|
1990 |
|
|
feature_family_has_stratixii_style_ram = dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family);
|
1991 |
|
|
feature_family_stratixii = dev.FEATURE_FAMILY_STRATIXII(intended_device_family);
|
1992 |
|
|
feature_family_cycloneii = dev.FEATURE_FAMILY_CYCLONEII(intended_device_family);
|
1993 |
|
|
feature_family_stratix = dev.FEATURE_FAMILY_STRATIX(intended_device_family);
|
1994 |
|
|
|
1995 |
|
|
if ((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
|
1996 |
|
|
$display ("Error! LPM_SHOWAHEAD must be ON or OFF.");
|
1997 |
|
|
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
|
1998 |
|
|
$display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
|
1999 |
|
|
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
|
2000 |
|
|
$display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
|
2001 |
|
|
if (lpm_numwords > (1 << lpm_widthu))
|
2002 |
|
|
$display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
|
2003 |
|
|
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
|
2004 |
|
|
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
|
2005 |
|
|
|
2006 |
|
|
for (i = 0; i < (1 << lpm_widthu_r) + WIDTH_RATIO; i = i + 1)
|
2007 |
|
|
mem_data[i] <= {lpm_width_r{1'b0}};
|
2008 |
|
|
i_data_tmp <= 0;
|
2009 |
|
|
i_temp_reg <= 0;
|
2010 |
|
|
i_wren_tmp <= 0;
|
2011 |
|
|
i_rdptr_g <= 0;
|
2012 |
|
|
i_rdptr_g1p <= 1;
|
2013 |
|
|
i_wrptr_g <= 0;
|
2014 |
|
|
i_wrptr_g_tmp <= 0;
|
2015 |
|
|
i_wrptr_g1 <= 1;
|
2016 |
|
|
i_delayed_wrptr_g <= 0;
|
2017 |
|
|
i_rdempty <= 1;
|
2018 |
|
|
i_wrempty_area <= 1;
|
2019 |
|
|
i_wrempty_speed <= 1;
|
2020 |
|
|
i_rdempty_rreg <= 1;
|
2021 |
|
|
i_rdfull_speed <= 0;
|
2022 |
|
|
i_rdfull_area <= 0;
|
2023 |
|
|
i_wrfull <= 0;
|
2024 |
|
|
i_wrfull_wreg <= 0;
|
2025 |
|
|
sync_aclr_pre <= 1'b1;
|
2026 |
|
|
sync_aclr <= 1'b1;
|
2027 |
|
|
i_q <= {lpm_width_r{1'b0}};
|
2028 |
|
|
is_underflow <= 0;
|
2029 |
|
|
is_overflow <= 0;
|
2030 |
|
|
no_warn <= 0;
|
2031 |
|
|
i_mem_address <= 0;
|
2032 |
|
|
i_first_bit_position <= 0;
|
2033 |
|
|
|
2034 |
|
|
i_maximize_speed = str_to_int(eva.GET_PARAMETER_VALUE(lpm_hint, "MAXIMIZE_SPEED"));
|
2035 |
|
|
|
2036 |
|
|
if (feature_family_has_stratixiii_style_ram == 1)
|
2037 |
|
|
begin
|
2038 |
|
|
use_wrempty_speed <= 1;
|
2039 |
|
|
use_rdfull_speed <= 1;
|
2040 |
|
|
end
|
2041 |
|
|
else if (feature_family_has_stratixii_style_ram == 1)
|
2042 |
|
|
begin
|
2043 |
|
|
use_wrempty_speed <= ((i_maximize_speed > 5) || (wrsync_delaypipe >= 2)) ? 1 : 0;
|
2044 |
|
|
use_rdfull_speed <= ((i_maximize_speed > 5) || (rdsync_delaypipe >= 2)) ? 1 : 0;
|
2045 |
|
|
end
|
2046 |
|
|
else
|
2047 |
|
|
begin
|
2048 |
|
|
use_wrempty_speed <= 0;
|
2049 |
|
|
use_rdfull_speed <= 0;
|
2050 |
|
|
end
|
2051 |
|
|
|
2052 |
|
|
if (feature_family_has_stratixii_style_ram == 1)
|
2053 |
|
|
begin
|
2054 |
|
|
if (add_usedw_msb_bit == "OFF")
|
2055 |
|
|
begin
|
2056 |
|
|
if (lpm_width_r > lpm_width)
|
2057 |
|
|
begin
|
2058 |
|
|
cnt_mod <= (1 << lpm_widthu) + WIDTH_RATIO;
|
2059 |
|
|
cnt_mod_r <= (1 << lpm_widthu_r) + 1;
|
2060 |
|
|
end
|
2061 |
|
|
else
|
2062 |
|
|
begin
|
2063 |
|
|
cnt_mod <= (1 << lpm_widthu) + 1;
|
2064 |
|
|
cnt_mod_r <= (1 << lpm_widthu_r) + WIDTH_RATIO;
|
2065 |
|
|
end
|
2066 |
|
|
end
|
2067 |
|
|
else
|
2068 |
|
|
begin
|
2069 |
|
|
if (lpm_width_r > lpm_width)
|
2070 |
|
|
begin
|
2071 |
|
|
cnt_mod <= (1 << (lpm_widthu-1)) + WIDTH_RATIO;
|
2072 |
|
|
cnt_mod_r <= (1 << (lpm_widthu_r-1)) + 1;
|
2073 |
|
|
end
|
2074 |
|
|
else
|
2075 |
|
|
begin
|
2076 |
|
|
cnt_mod <= (1 << (lpm_widthu-1)) + 1;
|
2077 |
|
|
cnt_mod_r <= (1 << (lpm_widthu_r-1)) + WIDTH_RATIO;
|
2078 |
|
|
end
|
2079 |
|
|
end
|
2080 |
|
|
end
|
2081 |
|
|
else
|
2082 |
|
|
begin
|
2083 |
|
|
cnt_mod <= 1 << lpm_widthu;
|
2084 |
|
|
cnt_mod_r <= 1 << lpm_widthu_r;
|
2085 |
|
|
end
|
2086 |
|
|
|
2087 |
|
|
if ((lpm_showahead == "OFF") &&
|
2088 |
|
|
((feature_family_stratixii == 1) ||
|
2089 |
|
|
((feature_family_cycloneii == 1))))
|
2090 |
|
|
i_q_is_registered = 1'b1;
|
2091 |
|
|
else
|
2092 |
|
|
i_q_is_registered = 1'b0;
|
2093 |
|
|
end
|
2094 |
|
|
|
2095 |
|
|
// COMPONENT INSTANTIATIONS
|
2096 |
|
|
dcfifo_dffpipe DP_WS_DGRP (
|
2097 |
|
|
.d (i_rdptr_g),
|
2098 |
|
|
.clock (wrclk),
|
2099 |
|
|
.aclr (aclr),
|
2100 |
|
|
.q (i_ws_dgrp));
|
2101 |
|
|
defparam
|
2102 |
|
|
DP_WS_DGRP.lpm_delay = wrsync_delaypipe,
|
2103 |
|
|
DP_WS_DGRP.lpm_width = lpm_widthu_r + 1;
|
2104 |
|
|
|
2105 |
|
|
dcfifo_dffpipe DP_RS_DGWP (
|
2106 |
|
|
.d (i_delayed_wrptr_g),
|
2107 |
|
|
.clock (rdclk),
|
2108 |
|
|
.aclr (aclr),
|
2109 |
|
|
.q (i_rs_dgwp));
|
2110 |
|
|
defparam
|
2111 |
|
|
DP_RS_DGWP.lpm_delay = rdsync_delaypipe,
|
2112 |
|
|
DP_RS_DGWP.lpm_width = lpm_widthu + 1;
|
2113 |
|
|
|
2114 |
|
|
dcfifo_dffpipe DP_RDUSEDW (
|
2115 |
|
|
.d (i_rdusedw_tmp),
|
2116 |
|
|
.clock (rdclk),
|
2117 |
|
|
.aclr (aclr),
|
2118 |
|
|
.q (i_rdusedw));
|
2119 |
|
|
dcfifo_dffpipe DP_WRUSEDW (
|
2120 |
|
|
.d (i_wrusedw_tmp),
|
2121 |
|
|
.clock (wrclk),
|
2122 |
|
|
.aclr (aclr),
|
2123 |
|
|
.q (i_wrusedw));
|
2124 |
|
|
defparam
|
2125 |
|
|
DP_RDUSEDW.lpm_delay = (delay_rdusedw > 2) ? 2 : delay_rdusedw,
|
2126 |
|
|
DP_RDUSEDW.lpm_width = lpm_widthu_r + 1,
|
2127 |
|
|
DP_WRUSEDW.lpm_delay = (delay_wrusedw > 2) ? 2 : delay_wrusedw,
|
2128 |
|
|
DP_WRUSEDW.lpm_width = lpm_widthu + 1;
|
2129 |
|
|
|
2130 |
|
|
// ALWAYS CONSTRUCT BLOCK
|
2131 |
|
|
always @(posedge aclr)
|
2132 |
|
|
begin
|
2133 |
|
|
i_data_tmp <= 0;
|
2134 |
|
|
i_wren_tmp <= 0;
|
2135 |
|
|
i_rdptr_g <= 0;
|
2136 |
|
|
i_rdptr_g1p <= 1;
|
2137 |
|
|
i_wrptr_g <= 0;
|
2138 |
|
|
i_wrptr_g_tmp <= 0;
|
2139 |
|
|
i_wrptr_g1 <= 1;
|
2140 |
|
|
i_delayed_wrptr_g <= 0;
|
2141 |
|
|
i_rdempty <= 1;
|
2142 |
|
|
i_wrempty_area <= 1;
|
2143 |
|
|
i_wrempty_speed <= 1;
|
2144 |
|
|
i_rdempty_rreg <= 1;
|
2145 |
|
|
i_rdfull_speed <= 0;
|
2146 |
|
|
i_rdfull_area <= 0;
|
2147 |
|
|
i_wrfull <= 0;
|
2148 |
|
|
i_wrfull_wreg <= 0;
|
2149 |
|
|
is_underflow <= 0;
|
2150 |
|
|
is_overflow <= 0;
|
2151 |
|
|
no_warn <= 0;
|
2152 |
|
|
i_mem_address <= 0;
|
2153 |
|
|
i_first_bit_position <= 0;
|
2154 |
|
|
|
2155 |
|
|
if(i_q_is_registered)
|
2156 |
|
|
i_q <= 0;
|
2157 |
|
|
else if ((feature_family_stratixii == 1) ||
|
2158 |
|
|
(feature_family_cycloneii == 1))
|
2159 |
|
|
i_q <= {lpm_width_r{1'bx}};
|
2160 |
|
|
|
2161 |
|
|
end // @(posedge aclr)
|
2162 |
|
|
|
2163 |
|
|
always @(posedge wrclk or posedge aclr)
|
2164 |
|
|
begin
|
2165 |
|
|
if ($time > 0)
|
2166 |
|
|
begin
|
2167 |
|
|
if (aclr)
|
2168 |
|
|
begin
|
2169 |
|
|
sync_aclr <= 1'b1;
|
2170 |
|
|
sync_aclr_pre <= 1'b1;
|
2171 |
|
|
end
|
2172 |
|
|
else
|
2173 |
|
|
begin
|
2174 |
|
|
sync_aclr <= sync_aclr_pre;
|
2175 |
|
|
sync_aclr_pre <= 1'b0;
|
2176 |
|
|
end
|
2177 |
|
|
end
|
2178 |
|
|
end
|
2179 |
|
|
|
2180 |
|
|
always @(posedge wrclk)
|
2181 |
|
|
begin
|
2182 |
|
|
i_data_tmp <= data;
|
2183 |
|
|
i_wrptr_g_tmp <= i_wrptr_g;
|
2184 |
|
|
i_wren_tmp <= i_wren;
|
2185 |
|
|
|
2186 |
|
|
if (~write_aclr && ($time > 0))
|
2187 |
|
|
begin
|
2188 |
|
|
if (i_wren)
|
2189 |
|
|
begin
|
2190 |
|
|
if (i_wrfull && (overflow_checking == "OFF"))
|
2191 |
|
|
begin
|
2192 |
|
|
if (((feature_family_has_stratixii_style_ram == 1) &&
|
2193 |
|
|
((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
|
2194 |
|
|
((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
|
2195 |
|
|
((feature_family_stratix == 1) && (use_eab == "ON") &&
|
2196 |
|
|
(((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
|
2197 |
|
|
(clocks_are_synchronized == "FALSE_LOW_LATENCY"))))
|
2198 |
|
|
begin
|
2199 |
|
|
if (no_warn == 1'b0)
|
2200 |
|
|
begin
|
2201 |
|
|
$display("Warning : Overflow occurred! Fifo output is unknown until the next reset is asserted.");
|
2202 |
|
|
$display("Time: %0t Instance: %m", $time);
|
2203 |
|
|
no_warn <= 1'b1;
|
2204 |
|
|
end
|
2205 |
|
|
is_overflow <= 1'b1;
|
2206 |
|
|
end
|
2207 |
|
|
end
|
2208 |
|
|
else
|
2209 |
|
|
begin
|
2210 |
|
|
if (i_wrptr_g1 < cnt_mod - 1)
|
2211 |
|
|
i_wrptr_g1 <= i_wrptr_g1 + 1;
|
2212 |
|
|
else
|
2213 |
|
|
i_wrptr_g1 <= 0;
|
2214 |
|
|
|
2215 |
|
|
i_wrptr_g <= i_wrptr_g1;
|
2216 |
|
|
|
2217 |
|
|
if (lpm_width > lpm_width_r)
|
2218 |
|
|
begin
|
2219 |
|
|
for (i = 0; i < WIDTH_RATIO; i = i+1)
|
2220 |
|
|
mem_data[i_wrptr_g*WIDTH_RATIO+i] <= data >> (lpm_width_r*i);
|
2221 |
|
|
end
|
2222 |
|
|
else if (lpm_width < lpm_width_r)
|
2223 |
|
|
begin
|
2224 |
|
|
i_mem_address <= i_wrptr_g1 /WIDTH_RATIO;
|
2225 |
|
|
i_first_bit_position <= (i_wrptr_g1 % WIDTH_RATIO) *lpm_width;
|
2226 |
|
|
for(i = 0; i < lpm_width; i = i+1)
|
2227 |
|
|
mem_data[i_mem_address][i_first_bit_position + i] <= data[i];
|
2228 |
|
|
end
|
2229 |
|
|
else
|
2230 |
|
|
mem_data[i_wrptr_g] <= data;
|
2231 |
|
|
end
|
2232 |
|
|
end
|
2233 |
|
|
i_delayed_wrptr_g <= i_wrptr_g;
|
2234 |
|
|
end
|
2235 |
|
|
end // @(wrclk)
|
2236 |
|
|
|
2237 |
|
|
always @(posedge rdclk)
|
2238 |
|
|
begin
|
2239 |
|
|
if(~aclr)
|
2240 |
|
|
begin
|
2241 |
|
|
if (i_rden && ($time > 0))
|
2242 |
|
|
begin
|
2243 |
|
|
if (i_rdempty && (underflow_checking == "OFF"))
|
2244 |
|
|
begin
|
2245 |
|
|
if (((feature_family_has_stratixii_style_ram == 1) &&
|
2246 |
|
|
((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
|
2247 |
|
|
((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
|
2248 |
|
|
((feature_family_stratix == 1) && (use_eab == "ON") &&
|
2249 |
|
|
(((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
|
2250 |
|
|
(clocks_are_synchronized == "FALSE_LOW_LATENCY"))))
|
2251 |
|
|
begin
|
2252 |
|
|
if (no_warn == 1'b0)
|
2253 |
|
|
begin
|
2254 |
|
|
$display("Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted.");
|
2255 |
|
|
$display("Time: %0t Instance: %m", $time);
|
2256 |
|
|
no_warn <= 1'b1;
|
2257 |
|
|
end
|
2258 |
|
|
is_underflow <= 1'b1;
|
2259 |
|
|
end
|
2260 |
|
|
end
|
2261 |
|
|
else
|
2262 |
|
|
begin
|
2263 |
|
|
if (i_rdptr_g1p < cnt_mod_r - 1)
|
2264 |
|
|
i_rdptr_g1p <= i_rdptr_g1p + 1;
|
2265 |
|
|
else
|
2266 |
|
|
i_rdptr_g1p <= 0;
|
2267 |
|
|
|
2268 |
|
|
i_rdptr_g <= i_rdptr_g1p;
|
2269 |
|
|
end
|
2270 |
|
|
end
|
2271 |
|
|
end
|
2272 |
|
|
end
|
2273 |
|
|
|
2274 |
|
|
always @(posedge rdclk)
|
2275 |
|
|
begin
|
2276 |
|
|
if (is_underflow || is_overflow)
|
2277 |
|
|
i_q <= {lpm_width_r{1'bx}};
|
2278 |
|
|
else
|
2279 |
|
|
begin
|
2280 |
|
|
if ((! i_q_is_registered) && ($time > 0))
|
2281 |
|
|
begin
|
2282 |
|
|
if (aclr && ((feature_family_stratixii == 1) ||
|
2283 |
|
|
(feature_family_cycloneii == 1)))
|
2284 |
|
|
i_q <= {lpm_width_r{1'bx}};
|
2285 |
|
|
else
|
2286 |
|
|
begin
|
2287 |
|
|
if (i_rdempty == 1'b1)
|
2288 |
|
|
i_q <= mem_data[i_rdptr_g];
|
2289 |
|
|
else if (i_rden)
|
2290 |
|
|
i_q <= mem_data[i_rdptr_g1p];
|
2291 |
|
|
end
|
2292 |
|
|
end
|
2293 |
|
|
else if (~aclr && i_rden && ($time > 0))
|
2294 |
|
|
i_q <= mem_data[i_rdptr_g];
|
2295 |
|
|
end
|
2296 |
|
|
end
|
2297 |
|
|
|
2298 |
|
|
// Usedw, Empty, Full
|
2299 |
|
|
always @(i_wrptr_g or i_ws_dgrp or cnt_mod)
|
2300 |
|
|
begin
|
2301 |
|
|
if (i_wrptr_g < (i_ws_dgrp*lpm_width_r/lpm_width))
|
2302 |
|
|
i_wrusedw_tmp <= cnt_mod + i_wrptr_g - i_ws_dgrp*lpm_width_r/lpm_width;
|
2303 |
|
|
else
|
2304 |
|
|
i_wrusedw_tmp <= i_wrptr_g - i_ws_dgrp*lpm_width_r/lpm_width;
|
2305 |
|
|
|
2306 |
|
|
if (lpm_width > lpm_width_r)
|
2307 |
|
|
begin
|
2308 |
|
|
if (i_wrptr_g == (i_ws_dgrp/WIDTH_RATIO))
|
2309 |
|
|
i_wrempty_speed <= 1;
|
2310 |
|
|
else
|
2311 |
|
|
i_wrempty_speed <= 0;
|
2312 |
|
|
end
|
2313 |
|
|
else
|
2314 |
|
|
begin
|
2315 |
|
|
if ((i_wrptr_g/WIDTH_RATIO) == i_ws_dgrp)
|
2316 |
|
|
i_wrempty_speed <= 1;
|
2317 |
|
|
else
|
2318 |
|
|
i_wrempty_speed <= 0;
|
2319 |
|
|
end
|
2320 |
|
|
end // @(i_wrptr_g or i_ws_dgrp)
|
2321 |
|
|
|
2322 |
|
|
always @(i_rdptr_g or i_rs_dgwp or cnt_mod)
|
2323 |
|
|
begin
|
2324 |
|
|
if ((i_rs_dgwp*lpm_width/lpm_width_r) < i_rdptr_g)
|
2325 |
|
|
i_rdusedw_tmp <= (cnt_mod + i_rs_dgwp)*lpm_width/lpm_width_r - i_rdptr_g;
|
2326 |
|
|
else
|
2327 |
|
|
i_rdusedw_tmp <= i_rs_dgwp*lpm_width/lpm_width_r - i_rdptr_g;
|
2328 |
|
|
|
2329 |
|
|
if (lpm_width < lpm_width_r)
|
2330 |
|
|
begin
|
2331 |
|
|
if ((i_rdptr_g*lpm_width_r/lpm_width) == (i_rs_dgwp + WIDTH_RATIO) %cnt_mod)
|
2332 |
|
|
i_rdfull_speed <= 1;
|
2333 |
|
|
else
|
2334 |
|
|
i_rdfull_speed <= 0;
|
2335 |
|
|
end
|
2336 |
|
|
else
|
2337 |
|
|
begin
|
2338 |
|
|
if (i_rdptr_g == ((i_rs_dgwp +1) % cnt_mod)*lpm_width/lpm_width_r)
|
2339 |
|
|
i_rdfull_speed <= 1;
|
2340 |
|
|
else
|
2341 |
|
|
i_rdfull_speed <= 0;
|
2342 |
|
|
end
|
2343 |
|
|
end // @(i_wrptr_g or i_rs_dgwp)
|
2344 |
|
|
|
2345 |
|
|
always @(i_wrptr_g1 or i_ws_dgrp or cnt_mod)
|
2346 |
|
|
begin
|
2347 |
|
|
if (lpm_width < lpm_width_r)
|
2348 |
|
|
begin
|
2349 |
|
|
if ((i_wrptr_g1 + WIDTH_RATIO -1) % cnt_mod == (i_ws_dgrp*lpm_width_r/lpm_width))
|
2350 |
|
|
i_wrfull <= 1;
|
2351 |
|
|
else
|
2352 |
|
|
i_wrfull <= 0;
|
2353 |
|
|
end
|
2354 |
|
|
else
|
2355 |
|
|
begin
|
2356 |
|
|
if (i_wrptr_g1 == (i_ws_dgrp*lpm_width_r/lpm_width))
|
2357 |
|
|
i_wrfull <= 1;
|
2358 |
|
|
else
|
2359 |
|
|
i_wrfull <= 0;
|
2360 |
|
|
end
|
2361 |
|
|
end // @(i_wrptr_g1 or i_ws_dgrp)
|
2362 |
|
|
|
2363 |
|
|
always @(i_rdptr_g or i_rs_dgwp)
|
2364 |
|
|
begin
|
2365 |
|
|
if (lpm_width > lpm_width_r)
|
2366 |
|
|
begin
|
2367 |
|
|
if ((i_rdptr_g/WIDTH_RATIO) == i_rs_dgwp)
|
2368 |
|
|
i_rdempty <= 1;
|
2369 |
|
|
else
|
2370 |
|
|
i_rdempty <= 0;
|
2371 |
|
|
end
|
2372 |
|
|
else
|
2373 |
|
|
begin
|
2374 |
|
|
if (i_rdptr_g == i_rs_dgwp/WIDTH_RATIO)
|
2375 |
|
|
i_rdempty <= 1;
|
2376 |
|
|
else
|
2377 |
|
|
i_rdempty <= 0;
|
2378 |
|
|
end
|
2379 |
|
|
end // @(i_rdptr_g or i_rs_dgwp)
|
2380 |
|
|
|
2381 |
|
|
always @(posedge rdclk)
|
2382 |
|
|
begin
|
2383 |
|
|
i_rdfull_area <= i_wrfull_wreg;
|
2384 |
|
|
i_rdempty_rreg <= i_rdempty;
|
2385 |
|
|
end // @(posedge rdclk)
|
2386 |
|
|
|
2387 |
|
|
always @(posedge wrclk)
|
2388 |
|
|
begin
|
2389 |
|
|
i_wrempty_area <= i_rdempty_rreg;
|
2390 |
|
|
|
2391 |
|
|
if ((~aclr) && (write_aclr_synch == "ON") && ((feature_family_stratixii == 1) ||
|
2392 |
|
|
(feature_family_cycloneii == 1)))
|
2393 |
|
|
i_wrfull_wreg <= (i_wrfull | write_aclr);
|
2394 |
|
|
else
|
2395 |
|
|
i_wrfull_wreg <= i_wrfull;
|
2396 |
|
|
end // @(posedge wrclk)
|
2397 |
|
|
|
2398 |
|
|
// CONTINOUS ASSIGNMENT
|
2399 |
|
|
assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !i_rdempty);
|
2400 |
|
|
assign i_wren = (((feature_family_stratixii == 1) ||
|
2401 |
|
|
(feature_family_cycloneii == 1)) &&
|
2402 |
|
|
(write_aclr_synch == "ON")) ?
|
2403 |
|
|
((overflow_checking == "OFF") ? wrreq && (!sync_aclr)
|
2404 |
|
|
: (wrreq && !(i_wrfull | sync_aclr))) :
|
2405 |
|
|
(overflow_checking == "OFF") ? wrreq : (wrreq && !i_wrfull);
|
2406 |
|
|
assign rdempty = (is_underflow || is_overflow) ? 1'bx : i_rdempty;
|
2407 |
|
|
assign wrempty = (is_underflow || is_overflow) ? 1'bx :
|
2408 |
|
|
(use_wrempty_speed) ? i_wrempty_speed : i_wrempty_area;
|
2409 |
|
|
assign rdfull = (is_underflow || is_overflow) ? 1'bx :
|
2410 |
|
|
(use_rdfull_speed) ? i_rdfull_speed : i_rdfull_area;
|
2411 |
|
|
assign wrfull = (is_underflow || is_overflow) ? 1'bx :
|
2412 |
|
|
(((feature_family_stratixii == 1) ||
|
2413 |
|
|
(feature_family_cycloneii == 1)) &&
|
2414 |
|
|
(write_aclr_synch == "ON")) ? (i_wrfull | write_aclr) : i_wrfull;
|
2415 |
|
|
assign wrusedw = (is_underflow || is_overflow) ? {lpm_widthu{1'bx}} :
|
2416 |
|
|
i_wrusedw[lpm_widthu-1:0];
|
2417 |
|
|
assign rdusedw = (is_underflow || is_overflow) ? {lpm_widthu_r{1'bx}} :
|
2418 |
|
|
i_rdusedw[lpm_widthu_r-1:0];
|
2419 |
|
|
assign q = (is_underflow || is_overflow) ? {lpm_width_r{1'bx}} : i_q;
|
2420 |
|
|
assign write_aclr = (((feature_family_stratixii == 1) ||
|
2421 |
|
|
(feature_family_cycloneii == 1)) &&
|
2422 |
|
|
(write_aclr_synch == "ON")) ? sync_aclr : aclr;
|
2423 |
|
|
|
2424 |
|
|
endmodule // dcfifo_low_latency
|
2425 |
|
|
// END OF MODULE
|
2426 |
|
|
|
2427 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
2428 |
|
|
//
|
2429 |
|
|
// Module Name : dcfifo_mixed_widths
|
2430 |
|
|
//
|
2431 |
|
|
// Description : Mixed widths Dual Clocks FIFO
|
2432 |
|
|
//
|
2433 |
|
|
// Limitation :
|
2434 |
|
|
//
|
2435 |
|
|
// Results expected:
|
2436 |
|
|
//
|
2437 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
2438 |
|
|
|
2439 |
|
|
// BEGINNING OF MODULE
|
2440 |
|
|
`timescale 1 ps / 1 ps
|
2441 |
|
|
|
2442 |
|
|
// MODULE DECLARATION
|
2443 |
|
|
module dcfifo_mixed_widths ( data, rdclk, wrclk, aclr, rdreq, wrreq,
|
2444 |
|
|
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
|
2445 |
|
|
|
2446 |
|
|
// GLOBAL PARAMETER DECLARATION
|
2447 |
|
|
parameter lpm_width = 1;
|
2448 |
|
|
parameter lpm_widthu = 1;
|
2449 |
|
|
parameter lpm_width_r = lpm_width;
|
2450 |
|
|
parameter lpm_widthu_r = lpm_widthu;
|
2451 |
|
|
parameter lpm_numwords = 2;
|
2452 |
|
|
parameter delay_rdusedw = 1;
|
2453 |
|
|
parameter delay_wrusedw = 1;
|
2454 |
|
|
parameter rdsync_delaypipe = 0;
|
2455 |
|
|
parameter wrsync_delaypipe = 0;
|
2456 |
|
|
parameter intended_device_family = "Stratix";
|
2457 |
|
|
parameter lpm_showahead = "OFF";
|
2458 |
|
|
parameter underflow_checking = "ON";
|
2459 |
|
|
parameter overflow_checking = "ON";
|
2460 |
|
|
parameter clocks_are_synchronized = "FALSE";
|
2461 |
|
|
parameter use_eab = "ON";
|
2462 |
|
|
parameter add_ram_output_register = "OFF";
|
2463 |
|
|
parameter lpm_hint = "USE_EAB=ON";
|
2464 |
|
|
parameter lpm_type = "dcfifo_mixed_widths";
|
2465 |
|
|
parameter add_usedw_msb_bit = "OFF";
|
2466 |
|
|
parameter write_aclr_synch = "OFF";
|
2467 |
|
|
|
2468 |
|
|
// LOCAL_PARAMETERS_BEGIN
|
2469 |
|
|
|
2470 |
|
|
parameter add_width = 1;
|
2471 |
|
|
parameter ram_block_type = "AUTO";
|
2472 |
|
|
|
2473 |
|
|
parameter FAMILY_HAS_STRATIXII_STYLE_RAM = (((((intended_device_family == "Stratix II") || (intended_device_family == "STRATIX II") || (intended_device_family == "stratix ii") || (intended_device_family == "StratixII") || (intended_device_family == "STRATIXII") || (intended_device_family == "stratixii") || (intended_device_family == "Armstrong") || (intended_device_family == "ARMSTRONG") || (intended_device_family == "armstrong"))
|
2474 |
|
|
|| ((intended_device_family == "HardCopy II") || (intended_device_family == "HARDCOPY II") || (intended_device_family == "hardcopy ii") || (intended_device_family == "HardCopyII") || (intended_device_family == "HARDCOPYII") || (intended_device_family == "hardcopyii") || (intended_device_family == "Fusion") || (intended_device_family == "FUSION") || (intended_device_family == "fusion"))
|
2475 |
|
|
|| (((intended_device_family == "Stratix II GX") || (intended_device_family == "STRATIX II GX") || (intended_device_family == "stratix ii gx") || (intended_device_family == "StratixIIGX") || (intended_device_family == "STRATIXIIGX") || (intended_device_family == "stratixiigx"))
|
2476 |
|
|
|| ((intended_device_family == "Arria GX") || (intended_device_family == "ARRIA GX") || (intended_device_family == "arria gx") || (intended_device_family == "ArriaGX") || (intended_device_family == "ARRIAGX") || (intended_device_family == "arriagx") || (intended_device_family == "Stratix II GX Lite") || (intended_device_family == "STRATIX II GX LITE") || (intended_device_family == "stratix ii gx lite") || (intended_device_family == "StratixIIGXLite") || (intended_device_family == "STRATIXIIGXLITE") || (intended_device_family == "stratixiigxlite"))
|
2477 |
|
|
) || (((intended_device_family == "Stratix III") || (intended_device_family == "STRATIX III") || (intended_device_family == "stratix iii") || (intended_device_family == "StratixIII") || (intended_device_family == "STRATIXIII") || (intended_device_family == "stratixiii") || (intended_device_family == "Titan") || (intended_device_family == "TITAN") || (intended_device_family == "titan") || (intended_device_family == "SIII") || (intended_device_family == "siii"))
|
2478 |
|
|
|| (((intended_device_family == "Stratix IV") || (intended_device_family == "STRATIX IV") || (intended_device_family == "stratix iv") || (intended_device_family == "TGX") || (intended_device_family == "tgx") || (intended_device_family == "StratixIV") || (intended_device_family == "STRATIXIV") || (intended_device_family == "stratixiv") || (intended_device_family == "Stratix IV (GT)") || (intended_device_family == "STRATIX IV (GT)") || (intended_device_family == "stratix iv (gt)") || (intended_device_family == "Stratix IV (GX)") || (intended_device_family == "STRATIX IV (GX)") || (intended_device_family == "stratix iv (gx)") || (intended_device_family == "Stratix IV (E)") || (intended_device_family == "STRATIX IV (E)") || (intended_device_family == "stratix iv (e)") || (intended_device_family == "StratixIV(GT)") || (intended_device_family == "STRATIXIV(GT)") || (intended_device_family == "stratixiv(gt)") || (intended_device_family == "StratixIV(GX)") || (intended_device_family == "STRATIXIV(GX)") || (intended_device_family == "stratixiv(gx)") || (intended_device_family == "StratixIV(E)") || (intended_device_family == "STRATIXIV(E)") || (intended_device_family == "stratixiv(e)") || (intended_device_family == "StratixIIIGX") || (intended_device_family == "STRATIXIIIGX") || (intended_device_family == "stratixiiigx") || (intended_device_family == "Stratix IV (GT/GX/E)") || (intended_device_family == "STRATIX IV (GT/GX/E)") || (intended_device_family == "stratix iv (gt/gx/e)") || (intended_device_family == "Stratix IV (GT/E/GX)") || (intended_device_family == "STRATIX IV (GT/E/GX)") || (intended_device_family == "stratix iv (gt/e/gx)") || (intended_device_family == "Stratix IV (E/GT/GX)") || (intended_device_family == "STRATIX IV (E/GT/GX)") || (intended_device_family == "stratix iv (e/gt/gx)") || (intended_device_family == "Stratix IV (E/GX/GT)") || (intended_device_family == "STRATIX IV (E/GX/GT)") || (intended_device_family == "stratix iv (e/gx/gt)") || (intended_device_family == "StratixIV(GT/GX/E)") || (intended_device_family == "STRATIXIV(GT/GX/E)") || (intended_device_family == "stratixiv(gt/gx/e)") || (intended_device_family == "StratixIV(GT/E/GX)") || (intended_device_family == "STRATIXIV(GT/E/GX)") || (intended_device_family == "stratixiv(gt/e/gx)") || (intended_device_family == "StratixIV(E/GX/GT)") || (intended_device_family == "STRATIXIV(E/GX/GT)") || (intended_device_family == "stratixiv(e/gx/gt)") || (intended_device_family == "StratixIV(E/GT/GX)") || (intended_device_family == "STRATIXIV(E/GT/GX)") || (intended_device_family == "stratixiv(e/gt/gx)") || (intended_device_family == "Stratix IV (GX/E)") || (intended_device_family == "STRATIX IV (GX/E)") || (intended_device_family == "stratix iv (gx/e)") || (intended_device_family == "StratixIV(GX/E)") || (intended_device_family == "STRATIXIV(GX/E)") || (intended_device_family == "stratixiv(gx/e)"))
|
2479 |
|
|
|| ((intended_device_family == "Arria II GX") || (intended_device_family == "ARRIA II GX") || (intended_device_family == "arria ii gx") || (intended_device_family == "ArriaIIGX") || (intended_device_family == "ARRIAIIGX") || (intended_device_family == "arriaiigx") || (intended_device_family == "Arria IIGX") || (intended_device_family == "ARRIA IIGX") || (intended_device_family == "arria iigx") || (intended_device_family == "ArriaII GX") || (intended_device_family == "ARRIAII GX") || (intended_device_family == "arriaii gx") || (intended_device_family == "Arria II") || (intended_device_family == "ARRIA II") || (intended_device_family == "arria ii") || (intended_device_family == "ArriaII") || (intended_device_family == "ARRIAII") || (intended_device_family == "arriaii") || (intended_device_family == "Arria II (GX/E)") || (intended_device_family == "ARRIA II (GX/E)") || (intended_device_family == "arria ii (gx/e)") || (intended_device_family == "ArriaII(GX/E)") || (intended_device_family == "ARRIAII(GX/E)") || (intended_device_family == "arriaii(gx/e)") || (intended_device_family == "PIRANHA") || (intended_device_family == "piranha"))
|
2480 |
|
|
|| ((intended_device_family == "HardCopy IV") || (intended_device_family == "HARDCOPY IV") || (intended_device_family == "hardcopy iv") || (intended_device_family == "HardCopyIV") || (intended_device_family == "HARDCOPYIV") || (intended_device_family == "hardcopyiv") || (intended_device_family == "HardCopy IV (GX)") || (intended_device_family == "HARDCOPY IV (GX)") || (intended_device_family == "hardcopy iv (gx)") || (intended_device_family == "HardCopy IV (E)") || (intended_device_family == "HARDCOPY IV (E)") || (intended_device_family == "hardcopy iv (e)") || (intended_device_family == "HardCopyIV(GX)") || (intended_device_family == "HARDCOPYIV(GX)") || (intended_device_family == "hardcopyiv(gx)") || (intended_device_family == "HardCopyIV(E)") || (intended_device_family == "HARDCOPYIV(E)") || (intended_device_family == "hardcopyiv(e)") || (intended_device_family == "HCXIV") || (intended_device_family == "hcxiv") || (intended_device_family == "HardCopy IV (GX/E)") || (intended_device_family == "HARDCOPY IV (GX/E)") || (intended_device_family == "hardcopy iv (gx/e)") || (intended_device_family == "HardCopy IV (E/GX)") || (intended_device_family == "HARDCOPY IV (E/GX)") || (intended_device_family == "hardcopy iv (e/gx)") || (intended_device_family == "HardCopyIV(GX/E)") || (intended_device_family == "HARDCOPYIV(GX/E)") || (intended_device_family == "hardcopyiv(gx/e)") || (intended_device_family == "HardCopyIV(E/GX)") || (intended_device_family == "HARDCOPYIV(E/GX)") || (intended_device_family == "hardcopyiv(e/gx)"))
|
2481 |
|
|
|| (((intended_device_family == "Stratix V") || (intended_device_family == "STRATIX V") || (intended_device_family == "stratix v") || (intended_device_family == "StratixV") || (intended_device_family == "STRATIXV") || (intended_device_family == "stratixv") || (intended_device_family == "Stratix V (GS)") || (intended_device_family == "STRATIX V (GS)") || (intended_device_family == "stratix v (gs)") || (intended_device_family == "StratixV(GS)") || (intended_device_family == "STRATIXV(GS)") || (intended_device_family == "stratixv(gs)") || (intended_device_family == "Stratix V (GX)") || (intended_device_family == "STRATIX V (GX)") || (intended_device_family == "stratix v (gx)") || (intended_device_family == "StratixV(GX)") || (intended_device_family == "STRATIXV(GX)") || (intended_device_family == "stratixv(gx)") || (intended_device_family == "Stratix V (GS/GX)") || (intended_device_family == "STRATIX V (GS/GX)") || (intended_device_family == "stratix v (gs/gx)") || (intended_device_family == "StratixV(GS/GX)") || (intended_device_family == "STRATIXV(GS/GX)") || (intended_device_family == "stratixv(gs/gx)") || (intended_device_family == "Stratix V (GX/GS)") || (intended_device_family == "STRATIX V (GX/GS)") || (intended_device_family == "stratix v (gx/gs)") || (intended_device_family == "StratixV(GX/GS)") || (intended_device_family == "STRATIXV(GX/GS)") || (intended_device_family == "stratixv(gx/gs)"))
|
2482 |
|
|
) || (((intended_device_family == "Arria II GZ") || (intended_device_family == "ARRIA II GZ") || (intended_device_family == "arria ii gz") || (intended_device_family == "ArriaII GZ") || (intended_device_family == "ARRIAII GZ") || (intended_device_family == "arriaii gz") || (intended_device_family == "Arria IIGZ") || (intended_device_family == "ARRIA IIGZ") || (intended_device_family == "arria iigz") || (intended_device_family == "ArriaIIGZ") || (intended_device_family == "ARRIAIIGZ") || (intended_device_family == "arriaiigz"))
|
2483 |
|
|
) ) || ((intended_device_family == "HardCopy III") || (intended_device_family == "HARDCOPY III") || (intended_device_family == "hardcopy iii") || (intended_device_family == "HardCopyIII") || (intended_device_family == "HARDCOPYIII") || (intended_device_family == "hardcopyiii") || (intended_device_family == "HCX") || (intended_device_family == "hcx"))
|
2484 |
|
|
) ) || (((intended_device_family == "Cyclone II") || (intended_device_family == "CYCLONE II") || (intended_device_family == "cyclone ii") || (intended_device_family == "Cycloneii") || (intended_device_family == "CYCLONEII") || (intended_device_family == "cycloneii") || (intended_device_family == "Magellan") || (intended_device_family == "MAGELLAN") || (intended_device_family == "magellan"))
|
2485 |
|
|
|| (((intended_device_family == "Cyclone III") || (intended_device_family == "CYCLONE III") || (intended_device_family == "cyclone iii") || (intended_device_family == "CycloneIII") || (intended_device_family == "CYCLONEIII") || (intended_device_family == "cycloneiii") || (intended_device_family == "Barracuda") || (intended_device_family == "BARRACUDA") || (intended_device_family == "barracuda") || (intended_device_family == "Cuda") || (intended_device_family == "CUDA") || (intended_device_family == "cuda") || (intended_device_family == "CIII") || (intended_device_family == "ciii"))
|
2486 |
|
|
|| ((intended_device_family == "Cyclone III LS") || (intended_device_family == "CYCLONE III LS") || (intended_device_family == "cyclone iii ls") || (intended_device_family == "CycloneIIILS") || (intended_device_family == "CYCLONEIIILS") || (intended_device_family == "cycloneiiils") || (intended_device_family == "Cyclone III LPS") || (intended_device_family == "CYCLONE III LPS") || (intended_device_family == "cyclone iii lps") || (intended_device_family == "Cyclone LPS") || (intended_device_family == "CYCLONE LPS") || (intended_device_family == "cyclone lps") || (intended_device_family == "CycloneLPS") || (intended_device_family == "CYCLONELPS") || (intended_device_family == "cyclonelps") || (intended_device_family == "Tarpon") || (intended_device_family == "TARPON") || (intended_device_family == "tarpon") || (intended_device_family == "Cyclone IIIE") || (intended_device_family == "CYCLONE IIIE") || (intended_device_family == "cyclone iiie"))
|
2487 |
|
|
|| (((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
|
2488 |
|
|
|| ((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
|
2489 |
|
|
) || (((intended_device_family == "Cyclone IV E") || (intended_device_family == "CYCLONE IV E") || (intended_device_family == "cyclone iv e") || (intended_device_family == "CycloneIV E") || (intended_device_family == "CYCLONEIV E") || (intended_device_family == "cycloneiv e") || (intended_device_family == "Cyclone IVE") || (intended_device_family == "CYCLONE IVE") || (intended_device_family == "cyclone ive") || (intended_device_family == "CycloneIVE") || (intended_device_family == "CYCLONEIVE") || (intended_device_family == "cycloneive"))
|
2490 |
|
|
) ) ) ))
|
2491 |
|
|
? 1 : 0;
|
2492 |
|
|
|
2493 |
|
|
parameter FAMILY_HAS_STRATIXIII_STYLE_RAM = (((((intended_device_family == "Stratix III") || (intended_device_family == "STRATIX III") || (intended_device_family == "stratix iii") || (intended_device_family == "StratixIII") || (intended_device_family == "STRATIXIII") || (intended_device_family == "stratixiii") || (intended_device_family == "Titan") || (intended_device_family == "TITAN") || (intended_device_family == "titan") || (intended_device_family == "SIII") || (intended_device_family == "siii"))
|
2494 |
|
|
|| (((intended_device_family == "Stratix IV") || (intended_device_family == "STRATIX IV") || (intended_device_family == "stratix iv") || (intended_device_family == "TGX") || (intended_device_family == "tgx") || (intended_device_family == "StratixIV") || (intended_device_family == "STRATIXIV") || (intended_device_family == "stratixiv") || (intended_device_family == "Stratix IV (GT)") || (intended_device_family == "STRATIX IV (GT)") || (intended_device_family == "stratix iv (gt)") || (intended_device_family == "Stratix IV (GX)") || (intended_device_family == "STRATIX IV (GX)") || (intended_device_family == "stratix iv (gx)") || (intended_device_family == "Stratix IV (E)") || (intended_device_family == "STRATIX IV (E)") || (intended_device_family == "stratix iv (e)") || (intended_device_family == "StratixIV(GT)") || (intended_device_family == "STRATIXIV(GT)") || (intended_device_family == "stratixiv(gt)") || (intended_device_family == "StratixIV(GX)") || (intended_device_family == "STRATIXIV(GX)") || (intended_device_family == "stratixiv(gx)") || (intended_device_family == "StratixIV(E)") || (intended_device_family == "STRATIXIV(E)") || (intended_device_family == "stratixiv(e)") || (intended_device_family == "StratixIIIGX") || (intended_device_family == "STRATIXIIIGX") || (intended_device_family == "stratixiiigx") || (intended_device_family == "Stratix IV (GT/GX/E)") || (intended_device_family == "STRATIX IV (GT/GX/E)") || (intended_device_family == "stratix iv (gt/gx/e)") || (intended_device_family == "Stratix IV (GT/E/GX)") || (intended_device_family == "STRATIX IV (GT/E/GX)") || (intended_device_family == "stratix iv (gt/e/gx)") || (intended_device_family == "Stratix IV (E/GT/GX)") || (intended_device_family == "STRATIX IV (E/GT/GX)") || (intended_device_family == "stratix iv (e/gt/gx)") || (intended_device_family == "Stratix IV (E/GX/GT)") || (intended_device_family == "STRATIX IV (E/GX/GT)") || (intended_device_family == "stratix iv (e/gx/gt)") || (intended_device_family == "StratixIV(GT/GX/E)") || (intended_device_family == "STRATIXIV(GT/GX/E)") || (intended_device_family == "stratixiv(gt/gx/e)") || (intended_device_family == "StratixIV(GT/E/GX)") || (intended_device_family == "STRATIXIV(GT/E/GX)") || (intended_device_family == "stratixiv(gt/e/gx)") || (intended_device_family == "StratixIV(E/GX/GT)") || (intended_device_family == "STRATIXIV(E/GX/GT)") || (intended_device_family == "stratixiv(e/gx/gt)") || (intended_device_family == "StratixIV(E/GT/GX)") || (intended_device_family == "STRATIXIV(E/GT/GX)") || (intended_device_family == "stratixiv(e/gt/gx)") || (intended_device_family == "Stratix IV (GX/E)") || (intended_device_family == "STRATIX IV (GX/E)") || (intended_device_family == "stratix iv (gx/e)") || (intended_device_family == "StratixIV(GX/E)") || (intended_device_family == "STRATIXIV(GX/E)") || (intended_device_family == "stratixiv(gx/e)"))
|
2495 |
|
|
|| ((intended_device_family == "Arria II GX") || (intended_device_family == "ARRIA II GX") || (intended_device_family == "arria ii gx") || (intended_device_family == "ArriaIIGX") || (intended_device_family == "ARRIAIIGX") || (intended_device_family == "arriaiigx") || (intended_device_family == "Arria IIGX") || (intended_device_family == "ARRIA IIGX") || (intended_device_family == "arria iigx") || (intended_device_family == "ArriaII GX") || (intended_device_family == "ARRIAII GX") || (intended_device_family == "arriaii gx") || (intended_device_family == "Arria II") || (intended_device_family == "ARRIA II") || (intended_device_family == "arria ii") || (intended_device_family == "ArriaII") || (intended_device_family == "ARRIAII") || (intended_device_family == "arriaii") || (intended_device_family == "Arria II (GX/E)") || (intended_device_family == "ARRIA II (GX/E)") || (intended_device_family == "arria ii (gx/e)") || (intended_device_family == "ArriaII(GX/E)") || (intended_device_family == "ARRIAII(GX/E)") || (intended_device_family == "arriaii(gx/e)") || (intended_device_family == "PIRANHA") || (intended_device_family == "piranha"))
|
2496 |
|
|
|| ((intended_device_family == "HardCopy IV") || (intended_device_family == "HARDCOPY IV") || (intended_device_family == "hardcopy iv") || (intended_device_family == "HardCopyIV") || (intended_device_family == "HARDCOPYIV") || (intended_device_family == "hardcopyiv") || (intended_device_family == "HardCopy IV (GX)") || (intended_device_family == "HARDCOPY IV (GX)") || (intended_device_family == "hardcopy iv (gx)") || (intended_device_family == "HardCopy IV (E)") || (intended_device_family == "HARDCOPY IV (E)") || (intended_device_family == "hardcopy iv (e)") || (intended_device_family == "HardCopyIV(GX)") || (intended_device_family == "HARDCOPYIV(GX)") || (intended_device_family == "hardcopyiv(gx)") || (intended_device_family == "HardCopyIV(E)") || (intended_device_family == "HARDCOPYIV(E)") || (intended_device_family == "hardcopyiv(e)") || (intended_device_family == "HCXIV") || (intended_device_family == "hcxiv") || (intended_device_family == "HardCopy IV (GX/E)") || (intended_device_family == "HARDCOPY IV (GX/E)") || (intended_device_family == "hardcopy iv (gx/e)") || (intended_device_family == "HardCopy IV (E/GX)") || (intended_device_family == "HARDCOPY IV (E/GX)") || (intended_device_family == "hardcopy iv (e/gx)") || (intended_device_family == "HardCopyIV(GX/E)") || (intended_device_family == "HARDCOPYIV(GX/E)") || (intended_device_family == "hardcopyiv(gx/e)") || (intended_device_family == "HardCopyIV(E/GX)") || (intended_device_family == "HARDCOPYIV(E/GX)") || (intended_device_family == "hardcopyiv(e/gx)"))
|
2497 |
|
|
|| (((intended_device_family == "Stratix V") || (intended_device_family == "STRATIX V") || (intended_device_family == "stratix v") || (intended_device_family == "StratixV") || (intended_device_family == "STRATIXV") || (intended_device_family == "stratixv") || (intended_device_family == "Stratix V (GS)") || (intended_device_family == "STRATIX V (GS)") || (intended_device_family == "stratix v (gs)") || (intended_device_family == "StratixV(GS)") || (intended_device_family == "STRATIXV(GS)") || (intended_device_family == "stratixv(gs)") || (intended_device_family == "Stratix V (GX)") || (intended_device_family == "STRATIX V (GX)") || (intended_device_family == "stratix v (gx)") || (intended_device_family == "StratixV(GX)") || (intended_device_family == "STRATIXV(GX)") || (intended_device_family == "stratixv(gx)") || (intended_device_family == "Stratix V (GS/GX)") || (intended_device_family == "STRATIX V (GS/GX)") || (intended_device_family == "stratix v (gs/gx)") || (intended_device_family == "StratixV(GS/GX)") || (intended_device_family == "STRATIXV(GS/GX)") || (intended_device_family == "stratixv(gs/gx)") || (intended_device_family == "Stratix V (GX/GS)") || (intended_device_family == "STRATIX V (GX/GS)") || (intended_device_family == "stratix v (gx/gs)") || (intended_device_family == "StratixV(GX/GS)") || (intended_device_family == "STRATIXV(GX/GS)") || (intended_device_family == "stratixv(gx/gs)"))
|
2498 |
|
|
) || (((intended_device_family == "Arria II GZ") || (intended_device_family == "ARRIA II GZ") || (intended_device_family == "arria ii gz") || (intended_device_family == "ArriaII GZ") || (intended_device_family == "ARRIAII GZ") || (intended_device_family == "arriaii gz") || (intended_device_family == "Arria IIGZ") || (intended_device_family == "ARRIA IIGZ") || (intended_device_family == "arria iigz") || (intended_device_family == "ArriaIIGZ") || (intended_device_family == "ARRIAIIGZ") || (intended_device_family == "arriaiigz"))
|
2499 |
|
|
) ) || ((intended_device_family == "HardCopy III") || (intended_device_family == "HARDCOPY III") || (intended_device_family == "hardcopy iii") || (intended_device_family == "HardCopyIII") || (intended_device_family == "HARDCOPYIII") || (intended_device_family == "hardcopyiii") || (intended_device_family == "HCX") || (intended_device_family == "hcx"))
|
2500 |
|
|
) || (((intended_device_family == "Cyclone III") || (intended_device_family == "CYCLONE III") || (intended_device_family == "cyclone iii") || (intended_device_family == "CycloneIII") || (intended_device_family == "CYCLONEIII") || (intended_device_family == "cycloneiii") || (intended_device_family == "Barracuda") || (intended_device_family == "BARRACUDA") || (intended_device_family == "barracuda") || (intended_device_family == "Cuda") || (intended_device_family == "CUDA") || (intended_device_family == "cuda") || (intended_device_family == "CIII") || (intended_device_family == "ciii"))
|
2501 |
|
|
|| ((intended_device_family == "Cyclone III LS") || (intended_device_family == "CYCLONE III LS") || (intended_device_family == "cyclone iii ls") || (intended_device_family == "CycloneIIILS") || (intended_device_family == "CYCLONEIIILS") || (intended_device_family == "cycloneiiils") || (intended_device_family == "Cyclone III LPS") || (intended_device_family == "CYCLONE III LPS") || (intended_device_family == "cyclone iii lps") || (intended_device_family == "Cyclone LPS") || (intended_device_family == "CYCLONE LPS") || (intended_device_family == "cyclone lps") || (intended_device_family == "CycloneLPS") || (intended_device_family == "CYCLONELPS") || (intended_device_family == "cyclonelps") || (intended_device_family == "Tarpon") || (intended_device_family == "TARPON") || (intended_device_family == "tarpon") || (intended_device_family == "Cyclone IIIE") || (intended_device_family == "CYCLONE IIIE") || (intended_device_family == "cyclone iiie"))
|
2502 |
|
|
|| (((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
|
2503 |
|
|
|| ((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
|
2504 |
|
|
) || (((intended_device_family == "Cyclone IV E") || (intended_device_family == "CYCLONE IV E") || (intended_device_family == "cyclone iv e") || (intended_device_family == "CycloneIV E") || (intended_device_family == "CYCLONEIV E") || (intended_device_family == "cycloneiv e") || (intended_device_family == "Cyclone IVE") || (intended_device_family == "CYCLONE IVE") || (intended_device_family == "cyclone ive") || (intended_device_family == "CycloneIVE") || (intended_device_family == "CYCLONEIVE") || (intended_device_family == "cycloneive"))
|
2505 |
|
|
) ) ))
|
2506 |
|
|
? 1 : 0;
|
2507 |
|
|
|
2508 |
|
|
parameter WRITE_SIDE_SYNCHRONIZERS = (wrsync_delaypipe != 0) ? wrsync_delaypipe :
|
2509 |
|
|
(((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
|
2510 |
|
|
&& (clocks_are_synchronized == "FALSE"))
|
2511 |
|
|
? 4 : 3;
|
2512 |
|
|
|
2513 |
|
|
parameter READ_SIDE_SYNCHRONIZERS = (rdsync_delaypipe != 0) ? rdsync_delaypipe :
|
2514 |
|
|
(((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
|
2515 |
|
|
&& (clocks_are_synchronized == "FALSE"))
|
2516 |
|
|
? 4 : 3;
|
2517 |
|
|
|
2518 |
|
|
// LOCAL_PARAMETERS_END
|
2519 |
|
|
|
2520 |
|
|
// INPUT PORT DECLARATION
|
2521 |
|
|
input [lpm_width-1:0] data;
|
2522 |
|
|
input rdclk;
|
2523 |
|
|
input wrclk;
|
2524 |
|
|
input aclr;
|
2525 |
|
|
input rdreq;
|
2526 |
|
|
input wrreq;
|
2527 |
|
|
|
2528 |
|
|
// OUTPUT PORT DECLARATION
|
2529 |
|
|
output rdfull;
|
2530 |
|
|
output wrfull;
|
2531 |
|
|
output rdempty;
|
2532 |
|
|
output wrempty;
|
2533 |
|
|
output [lpm_widthu_r-1:0] rdusedw;
|
2534 |
|
|
output [lpm_widthu-1:0] wrusedw;
|
2535 |
|
|
output [lpm_width_r-1:0] q;
|
2536 |
|
|
|
2537 |
|
|
// INTERNAL WIRE DECLARATION
|
2538 |
|
|
wire w_rdfull_s;
|
2539 |
|
|
wire w_wrfull_s;
|
2540 |
|
|
wire w_rdempty_s;
|
2541 |
|
|
wire w_wrempty_s;
|
2542 |
|
|
wire w_rdfull_a;
|
2543 |
|
|
wire w_wrfull_a;
|
2544 |
|
|
wire w_rdempty_a;
|
2545 |
|
|
wire w_wrempty_a;
|
2546 |
|
|
wire w_rdfull_l;
|
2547 |
|
|
wire w_wrfull_l;
|
2548 |
|
|
wire w_rdempty_l;
|
2549 |
|
|
wire w_wrempty_l;
|
2550 |
|
|
wire [lpm_widthu-1:0] w_rdusedw_s;
|
2551 |
|
|
wire [lpm_widthu-1:0] w_wrusedw_s;
|
2552 |
|
|
wire [lpm_widthu-1:0] w_rdusedw_a;
|
2553 |
|
|
wire [lpm_widthu-1:0] w_wrusedw_a;
|
2554 |
|
|
wire [lpm_widthu_r-1:0] w_rdusedw_l;
|
2555 |
|
|
wire [lpm_widthu-1:0] w_wrusedw_l;
|
2556 |
|
|
wire [lpm_width-1:0] w_q_s;
|
2557 |
|
|
wire [lpm_width-1:0] w_q_a;
|
2558 |
|
|
wire [lpm_width_r-1:0] w_q_l;
|
2559 |
|
|
|
2560 |
|
|
// INTERNAL REGISTER DECLARATION
|
2561 |
|
|
reg feature_family_has_stratixii_style_ram;
|
2562 |
|
|
reg feature_family_stratix;
|
2563 |
|
|
reg use_low_latency_fifo;
|
2564 |
|
|
|
2565 |
|
|
// INTERNAL TRI DECLARATION
|
2566 |
|
|
tri0 aclr;
|
2567 |
|
|
|
2568 |
|
|
// COMPONENT INSTANTIATIONS
|
2569 |
|
|
ALTERA_DEVICE_FAMILIES dev ();
|
2570 |
|
|
|
2571 |
|
|
initial
|
2572 |
|
|
begin
|
2573 |
|
|
feature_family_has_stratixii_style_ram = dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family);
|
2574 |
|
|
feature_family_stratix = dev.FEATURE_FAMILY_STRATIX(intended_device_family);
|
2575 |
|
|
|
2576 |
|
|
use_low_latency_fifo = (((feature_family_has_stratixii_style_ram == 1) &&
|
2577 |
|
|
((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
|
2578 |
|
|
((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
|
2579 |
|
|
((feature_family_stratix == 1) && (use_eab == "ON") &&
|
2580 |
|
|
(((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
|
2581 |
|
|
(clocks_are_synchronized == "FALSE_LOW_LATENCY"))));
|
2582 |
|
|
end
|
2583 |
|
|
|
2584 |
|
|
generate
|
2585 |
|
|
if (clocks_are_synchronized == "TRUE")
|
2586 |
|
|
begin : dcfifo_sync
|
2587 |
|
|
dcfifo_sync #(
|
2588 |
|
|
.lpm_width (lpm_width),
|
2589 |
|
|
.lpm_widthu (lpm_widthu),
|
2590 |
|
|
.lpm_numwords (lpm_numwords),
|
2591 |
|
|
.intended_device_family (intended_device_family),
|
2592 |
|
|
.lpm_showahead (lpm_showahead),
|
2593 |
|
|
.underflow_checking (underflow_checking),
|
2594 |
|
|
.overflow_checking (overflow_checking),
|
2595 |
|
|
.use_eab (use_eab),
|
2596 |
|
|
.add_ram_output_register (add_ram_output_register))
|
2597 |
|
|
SYNC (
|
2598 |
|
|
.data (data),
|
2599 |
|
|
.rdclk (rdclk),
|
2600 |
|
|
.wrclk (wrclk),
|
2601 |
|
|
.aclr (aclr),
|
2602 |
|
|
.rdreq (rdreq),
|
2603 |
|
|
.wrreq (wrreq),
|
2604 |
|
|
.rdfull (w_rdfull_s),
|
2605 |
|
|
.wrfull (w_wrfull_s),
|
2606 |
|
|
.rdempty (w_rdempty_s),
|
2607 |
|
|
.wrempty (w_wrempty_s),
|
2608 |
|
|
.rdusedw (w_rdusedw_s),
|
2609 |
|
|
.wrusedw (w_wrusedw_s),
|
2610 |
|
|
.q (w_q_s));
|
2611 |
|
|
end
|
2612 |
|
|
endgenerate
|
2613 |
|
|
|
2614 |
|
|
generate
|
2615 |
|
|
if (clocks_are_synchronized != "TRUE")
|
2616 |
|
|
begin : dcfifo_async
|
2617 |
|
|
dcfifo_async #(
|
2618 |
|
|
.lpm_width (lpm_width),
|
2619 |
|
|
.lpm_widthu (lpm_widthu),
|
2620 |
|
|
.lpm_numwords (lpm_numwords),
|
2621 |
|
|
.delay_rdusedw (delay_rdusedw),
|
2622 |
|
|
.delay_wrusedw (delay_wrusedw),
|
2623 |
|
|
.rdsync_delaypipe (READ_SIDE_SYNCHRONIZERS),
|
2624 |
|
|
.wrsync_delaypipe (WRITE_SIDE_SYNCHRONIZERS),
|
2625 |
|
|
.intended_device_family (intended_device_family),
|
2626 |
|
|
.lpm_showahead (lpm_showahead),
|
2627 |
|
|
.underflow_checking (underflow_checking),
|
2628 |
|
|
.overflow_checking (overflow_checking),
|
2629 |
|
|
.use_eab (use_eab),
|
2630 |
|
|
.add_ram_output_register (add_ram_output_register))
|
2631 |
|
|
ASYNC (
|
2632 |
|
|
.data (data),
|
2633 |
|
|
.rdclk (rdclk),
|
2634 |
|
|
.wrclk (wrclk),
|
2635 |
|
|
.aclr (aclr),
|
2636 |
|
|
.rdreq (rdreq),
|
2637 |
|
|
.wrreq (wrreq),
|
2638 |
|
|
.rdfull (w_rdfull_a),
|
2639 |
|
|
.wrfull (w_wrfull_a),
|
2640 |
|
|
.rdempty (w_rdempty_a),
|
2641 |
|
|
.wrempty (w_wrempty_a),
|
2642 |
|
|
.rdusedw (w_rdusedw_a),
|
2643 |
|
|
.wrusedw (w_wrusedw_a),
|
2644 |
|
|
.q (w_q_a) );
|
2645 |
|
|
end
|
2646 |
|
|
endgenerate
|
2647 |
|
|
|
2648 |
|
|
dcfifo_low_latency LOWLATENCY (
|
2649 |
|
|
.data (data),
|
2650 |
|
|
.rdclk (rdclk),
|
2651 |
|
|
.wrclk (wrclk),
|
2652 |
|
|
.aclr (aclr),
|
2653 |
|
|
.rdreq (rdreq),
|
2654 |
|
|
.wrreq (wrreq),
|
2655 |
|
|
.rdfull (w_rdfull_l),
|
2656 |
|
|
.wrfull (w_wrfull_l),
|
2657 |
|
|
.rdempty (w_rdempty_l),
|
2658 |
|
|
.wrempty (w_wrempty_l),
|
2659 |
|
|
.rdusedw (w_rdusedw_l),
|
2660 |
|
|
.wrusedw (w_wrusedw_l),
|
2661 |
|
|
.q (w_q_l) );
|
2662 |
|
|
defparam
|
2663 |
|
|
LOWLATENCY.lpm_width = lpm_width,
|
2664 |
|
|
LOWLATENCY.lpm_widthu = lpm_widthu,
|
2665 |
|
|
LOWLATENCY.lpm_width_r = lpm_width_r,
|
2666 |
|
|
LOWLATENCY.lpm_widthu_r = lpm_widthu_r,
|
2667 |
|
|
LOWLATENCY.lpm_numwords = lpm_numwords,
|
2668 |
|
|
LOWLATENCY.delay_rdusedw = delay_rdusedw,
|
2669 |
|
|
LOWLATENCY.delay_wrusedw = delay_wrusedw,
|
2670 |
|
|
LOWLATENCY.rdsync_delaypipe = (READ_SIDE_SYNCHRONIZERS > 3 ? READ_SIDE_SYNCHRONIZERS - 2 : 1),
|
2671 |
|
|
LOWLATENCY.wrsync_delaypipe = (WRITE_SIDE_SYNCHRONIZERS > 3 ? WRITE_SIDE_SYNCHRONIZERS - 2 : 1),
|
2672 |
|
|
LOWLATENCY.intended_device_family = intended_device_family,
|
2673 |
|
|
LOWLATENCY.lpm_showahead = lpm_showahead,
|
2674 |
|
|
LOWLATENCY.underflow_checking = underflow_checking,
|
2675 |
|
|
LOWLATENCY.overflow_checking = overflow_checking,
|
2676 |
|
|
LOWLATENCY.add_usedw_msb_bit = add_usedw_msb_bit,
|
2677 |
|
|
LOWLATENCY.write_aclr_synch = write_aclr_synch,
|
2678 |
|
|
LOWLATENCY.use_eab = use_eab,
|
2679 |
|
|
LOWLATENCY.clocks_are_synchronized = clocks_are_synchronized,
|
2680 |
|
|
LOWLATENCY.add_ram_output_register = add_ram_output_register,
|
2681 |
|
|
LOWLATENCY.lpm_hint = lpm_hint;
|
2682 |
|
|
|
2683 |
|
|
// INITIAL CONSTRUCT BLOCK
|
2684 |
|
|
initial
|
2685 |
|
|
begin
|
2686 |
|
|
if(((wrsync_delaypipe == 0) || (rdsync_delaypipe == 0)) && (clocks_are_synchronized == "FALSE"))
|
2687 |
|
|
begin
|
2688 |
|
|
if ((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
|
2689 |
|
|
begin
|
2690 |
|
|
$display ("Warning! Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2.");
|
2691 |
|
|
$display("Time: %0t Instance: %m", $time);
|
2692 |
|
|
end
|
2693 |
|
|
end
|
2694 |
|
|
end
|
2695 |
|
|
|
2696 |
|
|
// CONTINOUS ASSIGNMENT
|
2697 |
|
|
assign rdfull = (use_low_latency_fifo == 1) ? w_rdfull_l :
|
2698 |
|
|
(clocks_are_synchronized == "TRUE") ? w_rdfull_s : w_rdfull_a;
|
2699 |
|
|
|
2700 |
|
|
assign wrfull = (use_low_latency_fifo == 1) ? w_wrfull_l :
|
2701 |
|
|
(clocks_are_synchronized == "TRUE") ? w_wrfull_s : w_wrfull_a;
|
2702 |
|
|
|
2703 |
|
|
assign rdempty = (use_low_latency_fifo == 1) ? w_rdempty_l :
|
2704 |
|
|
(clocks_are_synchronized == "TRUE") ? w_rdempty_s : w_rdempty_a;
|
2705 |
|
|
|
2706 |
|
|
assign wrempty = (use_low_latency_fifo == 1) ? w_wrempty_l :
|
2707 |
|
|
(clocks_are_synchronized == "TRUE") ? w_wrempty_s : w_wrempty_a;
|
2708 |
|
|
|
2709 |
|
|
assign rdusedw = (use_low_latency_fifo == 1) ? w_rdusedw_l :
|
2710 |
|
|
(clocks_are_synchronized == "TRUE") ? w_rdusedw_s : w_rdusedw_a;
|
2711 |
|
|
|
2712 |
|
|
assign wrusedw = (use_low_latency_fifo == 1) ? w_wrusedw_l :
|
2713 |
|
|
(clocks_are_synchronized == "TRUE") ? w_wrusedw_s : w_wrusedw_a;
|
2714 |
|
|
|
2715 |
|
|
assign q = (use_low_latency_fifo == 1) ? w_q_l :
|
2716 |
|
|
(clocks_are_synchronized == "TRUE") ? w_q_s : w_q_a;
|
2717 |
|
|
|
2718 |
|
|
endmodule // dcfifo_mixed_widths
|
2719 |
|
|
// END OF MODULE
|
2720 |
|
|
|
2721 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
2722 |
|
|
//
|
2723 |
|
|
// Module Name : dcfifo
|
2724 |
|
|
//
|
2725 |
|
|
// Description : Dual Clocks FIFO
|
2726 |
|
|
//
|
2727 |
|
|
// Limitation :
|
2728 |
|
|
//
|
2729 |
|
|
// Results expected:
|
2730 |
|
|
//
|
2731 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
2732 |
|
|
|
2733 |
|
|
// BEGINNING OF MODULE
|
2734 |
|
|
`timescale 1 ps / 1 ps
|
2735 |
|
|
|
2736 |
|
|
// MODULE DECLARATION
|
2737 |
|
|
module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
|
2738 |
|
|
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
|
2739 |
|
|
|
2740 |
|
|
// GLOBAL PARAMETER DECLARATION
|
2741 |
|
|
parameter lpm_width = 1;
|
2742 |
|
|
parameter lpm_widthu = 1;
|
2743 |
|
|
parameter lpm_numwords = 2;
|
2744 |
|
|
parameter delay_rdusedw = 1;
|
2745 |
|
|
parameter delay_wrusedw = 1;
|
2746 |
|
|
parameter rdsync_delaypipe = 0;
|
2747 |
|
|
parameter wrsync_delaypipe = 0;
|
2748 |
|
|
parameter intended_device_family = "Stratix";
|
2749 |
|
|
parameter lpm_showahead = "OFF";
|
2750 |
|
|
parameter underflow_checking = "ON";
|
2751 |
|
|
parameter overflow_checking = "ON";
|
2752 |
|
|
parameter clocks_are_synchronized = "FALSE";
|
2753 |
|
|
parameter use_eab = "ON";
|
2754 |
|
|
parameter add_ram_output_register = "OFF";
|
2755 |
|
|
parameter lpm_hint = "USE_EAB=ON";
|
2756 |
|
|
parameter lpm_type = "dcfifo";
|
2757 |
|
|
parameter add_usedw_msb_bit = "OFF";
|
2758 |
|
|
parameter write_aclr_synch = "OFF";
|
2759 |
|
|
|
2760 |
|
|
// LOCAL_PARAMETERS_BEGIN
|
2761 |
|
|
|
2762 |
|
|
parameter add_width = 1;
|
2763 |
|
|
parameter ram_block_type = "AUTO";
|
2764 |
|
|
|
2765 |
|
|
// LOCAL_PARAMETERS_END
|
2766 |
|
|
|
2767 |
|
|
// INPUT PORT DECLARATION
|
2768 |
|
|
input [lpm_width-1:0] data;
|
2769 |
|
|
input rdclk;
|
2770 |
|
|
input wrclk;
|
2771 |
|
|
input aclr;
|
2772 |
|
|
input rdreq;
|
2773 |
|
|
input wrreq;
|
2774 |
|
|
|
2775 |
|
|
// OUTPUT PORT DECLARATION
|
2776 |
|
|
output rdfull;
|
2777 |
|
|
output wrfull;
|
2778 |
|
|
output rdempty;
|
2779 |
|
|
output wrempty;
|
2780 |
|
|
output [lpm_widthu-1:0] rdusedw;
|
2781 |
|
|
output [lpm_widthu-1:0] wrusedw;
|
2782 |
|
|
output [lpm_width-1:0] q;
|
2783 |
|
|
|
2784 |
|
|
// INTERNAL WIRE DECLARATION
|
2785 |
|
|
wire w_rdfull;
|
2786 |
|
|
wire w_wrfull;
|
2787 |
|
|
wire w_rdempty;
|
2788 |
|
|
wire w_wrempty;
|
2789 |
|
|
wire [lpm_widthu-1:0] w_rdusedw;
|
2790 |
|
|
wire [lpm_widthu-1:0] w_wrusedw;
|
2791 |
|
|
wire [lpm_width-1:0] w_q;
|
2792 |
|
|
|
2793 |
|
|
// INTERNAL TRI DECLARATION
|
2794 |
|
|
tri0 aclr;
|
2795 |
|
|
|
2796 |
|
|
dcfifo_mixed_widths DCFIFO_MW (
|
2797 |
|
|
.data (data),
|
2798 |
|
|
.rdclk (rdclk),
|
2799 |
|
|
.wrclk (wrclk),
|
2800 |
|
|
.aclr (aclr),
|
2801 |
|
|
.rdreq (rdreq),
|
2802 |
|
|
.wrreq (wrreq),
|
2803 |
|
|
.rdfull (w_rdfull),
|
2804 |
|
|
.wrfull (w_wrfull),
|
2805 |
|
|
.rdempty (w_rdempty),
|
2806 |
|
|
.wrempty (w_wrempty),
|
2807 |
|
|
.rdusedw (w_rdusedw),
|
2808 |
|
|
.wrusedw (w_wrusedw),
|
2809 |
|
|
.q (w_q) );
|
2810 |
|
|
defparam
|
2811 |
|
|
DCFIFO_MW.lpm_width = lpm_width,
|
2812 |
|
|
DCFIFO_MW.lpm_widthu = lpm_widthu,
|
2813 |
|
|
DCFIFO_MW.lpm_width_r = lpm_width,
|
2814 |
|
|
DCFIFO_MW.lpm_widthu_r = lpm_widthu,
|
2815 |
|
|
DCFIFO_MW.lpm_numwords = lpm_numwords,
|
2816 |
|
|
DCFIFO_MW.delay_rdusedw = delay_rdusedw,
|
2817 |
|
|
DCFIFO_MW.delay_wrusedw = delay_wrusedw,
|
2818 |
|
|
DCFIFO_MW.rdsync_delaypipe = rdsync_delaypipe,
|
2819 |
|
|
DCFIFO_MW.wrsync_delaypipe = wrsync_delaypipe,
|
2820 |
|
|
DCFIFO_MW.intended_device_family = intended_device_family,
|
2821 |
|
|
DCFIFO_MW.lpm_showahead = lpm_showahead,
|
2822 |
|
|
DCFIFO_MW.underflow_checking = underflow_checking,
|
2823 |
|
|
DCFIFO_MW.overflow_checking = overflow_checking,
|
2824 |
|
|
DCFIFO_MW.clocks_are_synchronized = clocks_are_synchronized,
|
2825 |
|
|
DCFIFO_MW.use_eab = use_eab,
|
2826 |
|
|
DCFIFO_MW.add_ram_output_register = add_ram_output_register,
|
2827 |
|
|
DCFIFO_MW.add_width = add_width,
|
2828 |
|
|
DCFIFO_MW.ram_block_type = ram_block_type,
|
2829 |
|
|
DCFIFO_MW.add_usedw_msb_bit = add_usedw_msb_bit,
|
2830 |
|
|
DCFIFO_MW.write_aclr_synch = write_aclr_synch,
|
2831 |
|
|
DCFIFO_MW.lpm_hint = lpm_hint;
|
2832 |
|
|
|
2833 |
|
|
// CONTINOUS ASSIGNMENT
|
2834 |
|
|
assign rdfull = w_rdfull;
|
2835 |
|
|
assign wrfull = w_wrfull;
|
2836 |
|
|
assign rdempty = w_rdempty;
|
2837 |
|
|
assign wrempty = w_wrempty;
|
2838 |
|
|
assign rdusedw = w_rdusedw;
|
2839 |
|
|
assign wrusedw = w_wrusedw;
|
2840 |
|
|
assign q = w_q;
|
2841 |
|
|
|
2842 |
|
|
endmodule // dcfifo
|
2843 |
|
|
// END OF MODULE
|
2844 |
|
|
|