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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 22

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Line No. Rev Author Line
1 21 edn_walter 
#include <stdio.h>
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#include "svdpi.h"
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#include "../dpiheader.h"
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int ptp_drv_bfm_c(double fw_delay)
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{
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  int cpu_addr_i;
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  int cpu_data_i;
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  int cpu_data_o;
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11 22 edn_walter 
  // LOAD RTC PERIOD AND ACC_MODULO
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  cpu_addr_i = 0x00000020;
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  cpu_data_i = 0x8;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000024;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000028;
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  cpu_data_i = 0x3B9ACA00;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x0000002C;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x4;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  // RESET RTC
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x10;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  // LOAD RTC SEC AND NS
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  cpu_addr_i = 0x00000010;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000014;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000018;
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  cpu_data_i = 0x3B9AC9F6;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x0000001C;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x8;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  // LOAD RTC ADJ
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  cpu_addr_i = 0x00000030;
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  cpu_data_i = 0x100;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000038;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x0000003C;
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  cpu_data_i = 0x20;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x2;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  // READ RTC SEC AND NS
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0X00000040;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X00000044;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X00000048;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X0000004C;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  // READ BACK ALL REGISTERS
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  for (;;)
90 21 edn_walter 
  {
91 22 edn_walter 
    int t;
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    for (t=0; t<=0x5c; t=t+4)
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    {
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      cpu_addr_i = t;
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      cpu_rd(cpu_addr_i, &cpu_data_o);
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97 22 edn_walter 
      cpu_hd(10);
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    }
99 21 edn_walter 
  }
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  return(0); /* Return success (required by tasks) */
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}

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