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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 23

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#include <stdio.h>
 
#include "svdpi.h"
#include "../dpiheader.h"
int ptp_drv_bfm_c(double fw_delay)
{
  int cpu_addr_i;
  int cpu_data_i;
  int cpu_data_o;
 
  // LOAD RTC PERIOD AND ACC_MODULO
  cpu_addr_i = 0x00000020;
  cpu_data_i = 0x8;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000024;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000028;
  cpu_data_i = 0x3B9ACA00;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x0000002C;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x4;
  cpu_wr(cpu_addr_i, cpu_data_i);
  // RESET RTC
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x10;
  cpu_wr(cpu_addr_i, cpu_data_i);
  // LOAD RTC SEC AND NS
  cpu_addr_i = 0x00000010;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000014;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000018;
  cpu_data_i = 0x3B9AC9F6;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x0000001C;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x8;
  cpu_wr(cpu_addr_i, cpu_data_i);
  // LOAD RTC ADJ
  cpu_addr_i = 0x00000030;
  cpu_data_i = 0x100;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000038;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x0000003C;
  cpu_data_i = 0x20;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x2;
  cpu_wr(cpu_addr_i, cpu_data_i);
  // READ RTC SEC AND NS
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X00000040;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X00000044;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X00000048;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X0000004C;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  // READ RTC SEC AND NS
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_addr_i = 0x00000000;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X00000040;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X00000044;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X00000048;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  cpu_addr_i = 0X0000004C;
  cpu_rd(cpu_addr_i, &cpu_data_o);
 
  // READ BACK ALL REGISTERS
  for (;;)
  {
    int t;
    for (t=0; t<=0x5c; t=t+4)
    {
      cpu_addr_i = t;
      cpu_rd(cpu_addr_i, &cpu_data_o);
 
      cpu_hd(10);
    }
  }
 
  return(0); /* Return success (required by tasks) */
}

Line No.	Rev	Author	Line
1	21	edn_walter	`#include <stdio.h>`
2
3			`#include "svdpi.h"`
4			`#include "../dpiheader.h"`
5			`int ptp_drv_bfm_c(double fw_delay)`
6			`{`
7			`int cpu_addr_i;`
8			`int cpu_data_i;`
9			`int cpu_data_o;`
10
11	22	edn_walter	`// LOAD RTC PERIOD AND ACC_MODULO`
12			`cpu_addr_i = 0x00000020;`
13			`cpu_data_i = 0x8;`
14			`cpu_wr(cpu_addr_i, cpu_data_i);`
15			`cpu_addr_i = 0x00000024;`
16			`cpu_data_i = 0x0;`
17			`cpu_wr(cpu_addr_i, cpu_data_i);`
18			`cpu_addr_i = 0x00000028;`
19			`cpu_data_i = 0x3B9ACA00;`
20			`cpu_wr(cpu_addr_i, cpu_data_i);`
21			`cpu_addr_i = 0x0000002C;`
22			`cpu_data_i = 0x0;`
23			`cpu_wr(cpu_addr_i, cpu_data_i);`
24			`cpu_addr_i = 0x00000000;`
25	23	edn_walter	`cpu_data_i = 0x0;`
26			`cpu_wr(cpu_addr_i, cpu_data_i);`
27			`cpu_addr_i = 0x00000000;`
28	22	edn_walter	`cpu_data_i = 0x4;`
29			`cpu_wr(cpu_addr_i, cpu_data_i);`
30	23	edn_walter	`// RESET RTC`
31	22	edn_walter	`cpu_addr_i = 0x00000000;`
32			`cpu_data_i = 0x0;`
33			`cpu_wr(cpu_addr_i, cpu_data_i);`
34			`cpu_addr_i = 0x00000000;`
35			`cpu_data_i = 0x10;`
36			`cpu_wr(cpu_addr_i, cpu_data_i);`
37			`// LOAD RTC SEC AND NS`
38			`cpu_addr_i = 0x00000010;`
39			`cpu_data_i = 0x0;`
40			`cpu_wr(cpu_addr_i, cpu_data_i);`
41			`cpu_addr_i = 0x00000014;`
42			`cpu_data_i = 0x1;`
43			`cpu_wr(cpu_addr_i, cpu_data_i);`
44			`cpu_addr_i = 0x00000018;`
45			`cpu_data_i = 0x3B9AC9F6;`
46			`cpu_wr(cpu_addr_i, cpu_data_i);`
47			`cpu_addr_i = 0x0000001C;`
48			`cpu_data_i = 0x0;`
49			`cpu_wr(cpu_addr_i, cpu_data_i);`
50			`cpu_addr_i = 0x00000000;`
51	23	edn_walter	`cpu_data_i = 0x0;`
52	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
53			`cpu_addr_i = 0x00000000;`
54	23	edn_walter	`cpu_data_i = 0x8;`
55	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
56			`// LOAD RTC ADJ`
57			`cpu_addr_i = 0x00000030;`
58			`cpu_data_i = 0x100;`
59			`cpu_wr(cpu_addr_i, cpu_data_i);`
60			`cpu_addr_i = 0x00000038;`
61			`cpu_data_i = 0x1;`
62			`cpu_wr(cpu_addr_i, cpu_data_i);`
63			`cpu_addr_i = 0x0000003C;`
64			`cpu_data_i = 0x20;`
65			`cpu_wr(cpu_addr_i, cpu_data_i);`
66			`cpu_addr_i = 0x00000000;`
67	23	edn_walter	`cpu_data_i = 0x0;`
68			`cpu_wr(cpu_addr_i, cpu_data_i);`
69			`cpu_addr_i = 0x00000000;`
70	22	edn_walter	`cpu_data_i = 0x2;`
71			`cpu_wr(cpu_addr_i, cpu_data_i);`
72	23	edn_walter	`// READ RTC SEC AND NS`
73	22	edn_walter	`cpu_addr_i = 0x00000000;`
74			`cpu_data_i = 0x0;`
75			`cpu_wr(cpu_addr_i, cpu_data_i);`
76			`cpu_addr_i = 0x00000000;`
77			`cpu_data_i = 0x1;`
78			`cpu_wr(cpu_addr_i, cpu_data_i);`
79	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
80			`cpu_addr_i = 0X00000040;`
81			`cpu_rd(cpu_addr_i, &cpu_data_o);`
82			`cpu_addr_i = 0X00000044;`
83			`cpu_rd(cpu_addr_i, &cpu_data_o);`
84			`cpu_addr_i = 0X00000048;`
85			`cpu_rd(cpu_addr_i, &cpu_data_o);`
86			`cpu_addr_i = 0X0000004C;`
87			`cpu_rd(cpu_addr_i, &cpu_data_o);`
88			`// READ RTC SEC AND NS`
89	22	edn_walter	`cpu_addr_i = 0x00000000;`
90			`cpu_data_i = 0x0;`
91			`cpu_wr(cpu_addr_i, cpu_data_i);`
92	23	edn_walter	`cpu_addr_i = 0x00000000;`
93			`cpu_data_i = 0x1;`
94			`cpu_wr(cpu_addr_i, cpu_data_i);`
95			`cpu_rd(cpu_addr_i, &cpu_data_o);`
96	22	edn_walter	`cpu_addr_i = 0X00000040;`
97			`cpu_rd(cpu_addr_i, &cpu_data_o);`
98			`cpu_addr_i = 0X00000044;`
99			`cpu_rd(cpu_addr_i, &cpu_data_o);`
100			`cpu_addr_i = 0X00000048;`
101			`cpu_rd(cpu_addr_i, &cpu_data_o);`
102			`cpu_addr_i = 0X0000004C;`
103			`cpu_rd(cpu_addr_i, &cpu_data_o);`
104
105			`// READ BACK ALL REGISTERS`
106			`for (;;)`
107	21	edn_walter	`{`
108	22	edn_walter	`int t;`
109			`for (t=0; t<=0x5c; t=t+4)`
110			`{`
111			`cpu_addr_i = t;`
112	21	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
113
114	22	edn_walter	`cpu_hd(10);`
115			`}`
116	21	edn_walter	`}`
117
118			`return(0); /* Return success (required by tasks) */`
119			`}`

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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 23