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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 24

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Line No. Rev Author Line
1 21 edn_walter 
#include <stdio.h>
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#include "svdpi.h"
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#include "../dpiheader.h"
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int ptp_drv_bfm_c(double fw_delay)
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{
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  int cpu_addr_i;
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  int cpu_data_i;
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  int cpu_data_o;
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11 22 edn_walter 
  // LOAD RTC PERIOD AND ACC_MODULO
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  cpu_addr_i = 0x00000020;
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  cpu_data_i = 0x8;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000024;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000028;
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  cpu_data_i = 0x3B9ACA00;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x0000002C;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
25 23 edn_walter 
  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x4;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  // RESET RTC
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
35 24 edn_walter 
  cpu_data_i = 0xA10;
36 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
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  // LOAD RTC SEC AND NS
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  cpu_addr_i = 0x00000010;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000014;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000018;
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  cpu_data_i = 0x3B9AC9F6;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x0000001C;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
51 23 edn_walter 
  cpu_data_i = 0x0;
52 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x8;
55 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
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  // LOAD RTC ADJ
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  cpu_addr_i = 0x00000030;
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  cpu_data_i = 0x100;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000038;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x0000003C;
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  cpu_data_i = 0x20;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
67 23 edn_walter 
  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
70 22 edn_walter 
  cpu_data_i = 0x2;
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  cpu_wr(cpu_addr_i, cpu_data_i);
72 23 edn_walter 
  // READ RTC SEC AND NS
73 22 edn_walter 
  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
79 24 edn_walter 
  do {
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    cpu_addr_i = 0x00000000;
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    cpu_rd(cpu_addr_i, &cpu_data_o);
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    //printf("%08x\n", (cpu_data_o & 0x1));
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  } while ((cpu_data_o & 0x1) == 0x0);
84 23 edn_walter 
  cpu_addr_i = 0X00000040;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X00000044;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X00000048;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X0000004C;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  // READ RTC SEC AND NS
93 22 edn_walter 
  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
96 23 edn_walter 
  cpu_addr_i = 0x00000000;
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  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
99 24 edn_walter 
  do {
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    cpu_addr_i = 0x00000000;
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    cpu_rd(cpu_addr_i, &cpu_data_o);
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    //printf("%08x\n", (cpu_data_o & 0x1));
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  } while ((cpu_data_o & 0x1) == 0x0);
104 22 edn_walter 
  cpu_addr_i = 0X00000040;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X00000044;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X00000048;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  cpu_addr_i = 0X0000004C;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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113 24 edn_walter 
  int i;
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  // POLL TSU RX STATUS
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  int rx_queue_num;
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  do {
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    cpu_addr_i = 0x00000004;
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    cpu_rd(cpu_addr_i, &cpu_data_o);
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    rx_queue_num = cpu_data_o;
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    //printf("%08x\n", rx_queue_num);
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  } while (!(rx_queue_num > 0x2));
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  // READ TSU RX FIFO
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  for (i=rx_queue_num; i>=0; i--) {
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      cpu_addr_i = 0x00000000;
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      cpu_data_i = 0x0;
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      cpu_wr(cpu_addr_i, cpu_data_i);
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      cpu_addr_i = 0x00000000;
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      cpu_data_i = 0x400;
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      cpu_wr(cpu_addr_i, cpu_data_i);
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      cpu_addr_i = 0x00000050;
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      cpu_rd(cpu_addr_i, &cpu_data_o);
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      cpu_addr_i = 0x00000054;
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      cpu_rd(cpu_addr_i, &cpu_data_o);
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  }
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  // POLL TSU TX STATUS
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  int tx_queue_num;
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  do {
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    cpu_addr_i = 0x00000008;
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    cpu_rd(cpu_addr_i, &cpu_data_o);
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    tx_queue_num = cpu_data_o;
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    //printf("%08x\n", tx_queue_num);
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  } while (!(tx_queue_num > 0x2));
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  // READ TSU TX FIFO
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  for (i=tx_queue_num; i>=0; i--) {
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      cpu_addr_i = 0x00000000;
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      cpu_data_i = 0x0;
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      cpu_wr(cpu_addr_i, cpu_data_i);
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      cpu_addr_i = 0x00000000;
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      cpu_data_i = 0x100;
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      cpu_wr(cpu_addr_i, cpu_data_i);
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      cpu_addr_i = 0x00000058;
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      cpu_rd(cpu_addr_i, &cpu_data_o);
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      cpu_addr_i = 0x0000005C;
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      cpu_rd(cpu_addr_i, &cpu_data_o);
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  }
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157 22 edn_walter 
  // READ BACK ALL REGISTERS
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  for (;;)
159 21 edn_walter 
  {
160 22 edn_walter 
    int t;
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    for (t=0; t<=0x5c; t=t+4)
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    {
163 24 edn_walter 
      cpu_hd(10);
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165 22 edn_walter 
      cpu_addr_i = t;
166 21 edn_walter 
      cpu_rd(cpu_addr_i, &cpu_data_o);
167 22 edn_walter 
    }
168 21 edn_walter 
  }
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  return(0); /* Return success (required by tasks) */
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}

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