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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 34

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1 34 edn_walter 
/*
2 
 * $ptp_drv_bfm.c
3 
 *
4 
 * Copyright (c) 2012, BBY&HW. All rights reserved.
5 
 *
6 
 * This library is free software; you can redistribute it and/or
7 
 * modify it under the terms of the GNU Lesser General Public
8 
 * License as published by the Free Software Foundation; either
9 
 * version 2.1 of the License, or (at your option) any later version.
10 
 *
11 
 * This library is distributed in the hope that it will be useful,
12 
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
 * Lesser General Public License for more details.
15 
 *
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 * You should have received a copy of the GNU Lesser General Public
17 
 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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 * MA 02110-1301  USA
20 
 */
21 
 
22 21 edn_walter 
#include <stdio.h>
23 
 
24 
#include "svdpi.h"
25 
#include "../dpiheader.h"
26 33 edn_walter 
 
27 
// define RTC address values
28 
#define RTC_CTRL            0x00000000
29 
#define RTC_NULL_0x4        0x00000004
30 
#define RTC_NULL_0x8        0x00000008
31 
#define RTC_NULL_0xC        0x0000000C
32 
#define RTC_TIME_SEC_H_LOAD 0x00000010
33 
#define RTC_TIME_SEC_L_LOAD 0x00000014
34 
#define RTC_TIME_NSC_H_LOAD 0x00000018
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#define RTC_TIME_NSC_L_LOAD 0x0000001C
36 
#define RTC_PERIOD_H_LOAD   0x00000020
37 
#define RTC_PERIOD_L_LOAD   0x00000024
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#define RTC_ACCMOD_H_LOAD   0x00000028
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#define RTC_ACCMOD_L_LOAD   0x0000002C
40 
#define RTC_ADJNUM_LOAD     0x00000030
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#define RTC_NULL_0x34       0x00000034
42 
#define RTC_ADJPER_H_LOAD   0x00000038
43 
#define RTC_ADJPER_L_LOAD   0x0000003C
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#define RTC_TIME_SEC_H_READ 0x00000040
45 
#define RTC_TIME_SEC_L_READ 0x00000044
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#define RTC_TIME_NSC_H_READ 0x00000048
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#define RTC_TIME_NSC_L_READ 0x0000004C
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// define RTC data values
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#define RTC_SET_CTRL_0 0x0
50 
#define RTC_GET_TIME   0x1
51 
#define RTC_SET_ADJ    0x2
52 
#define RTC_SET_PERIOD 0x4
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#define RTC_SET_TIME   0x8
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#define RTC_SET_RESET  0x10
55 
#define RTC_ACCMOD_H   0x3B9ACA00  // 1,000,000,000 for 30bit
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#define RTC_ACCMOD_L   0x0         // 256 for 8bit
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#define RTC_PERIOD_H   0x8  // 8ns for 125MHz rtc_clk
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#define RTC_PERIOD_L   0x0
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60 
// define TSU address values
61 
#define TSU_CTRL         0x00000050
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#define TSU_RXQUE_STATUS 0x00000054
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#define TSU_TXQUE_STATUS 0x00000058
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#define TSU_NULL_0x5C    0x0000005C
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#define TSU_RXQUE_DATA_H 0x00000060
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#define TSU_RXQUE_DATA_L 0x00000064
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#define TSU_TXQUE_DATA_H 0x00000068
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#define TSU_TXQUE_DATA_L 0x0000006C
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// define TSU data values
70 
#define TSU_SET_CTRL_0 0x0
71 
#define TSU_GET_TXQUE  0x1
72 
#define TSU_GET_RXQUE  0x4
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#define TSU_SET_RESET  0xA
74 
 
75 21 edn_walter 
int ptp_drv_bfm_c(double fw_delay)
76 
{
77 26 edn_walter 
  unsigned int cpu_addr_i;
78 
  unsigned int cpu_data_i;
79 
  unsigned int cpu_data_o;
80 21 edn_walter 
 
81 22 edn_walter 
  // LOAD RTC PERIOD AND ACC_MODULO
82 33 edn_walter 
  cpu_addr_i = RTC_PERIOD_H_LOAD;
83 
  cpu_data_i = RTC_PERIOD_H;
84 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
85 33 edn_walter 
  cpu_addr_i = RTC_PERIOD_L_LOAD;
86 
  cpu_data_i = RTC_PERIOD_L;
87 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
88 33 edn_walter 
  cpu_addr_i = RTC_ACCMOD_H_LOAD;
89 
  cpu_data_i = RTC_ACCMOD_H;
90 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
91 33 edn_walter 
  cpu_addr_i = RTC_ACCMOD_L_LOAD;
92 
  cpu_data_i = RTC_ACCMOD_L;
93 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
94 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
95 
  cpu_data_i = RTC_SET_CTRL_0;
96 23 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
97 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
98 
  cpu_data_i = RTC_SET_PERIOD;
99 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
100 33 edn_walter 
  // RESET RTC AND TSU
101 
  cpu_addr_i = RTC_CTRL;
102 
  cpu_data_i = RTC_SET_CTRL_0;
103 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
104 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
105 
  cpu_data_i = RTC_SET_RESET;
106 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
107 33 edn_walter 
  cpu_addr_i = TSU_CTRL;
108 
  cpu_data_i = TSU_SET_CTRL_0;
109 
  cpu_wr(cpu_addr_i, cpu_data_i);
110 
  cpu_addr_i = TSU_CTRL;
111 
  cpu_data_i = TSU_SET_RESET;
112 
  cpu_wr(cpu_addr_i, cpu_data_i);
113 26 edn_walter 
  // READ RTC SEC AND NS
114 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
115 
  cpu_data_i = RTC_SET_CTRL_0;
116 26 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
117 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
118 
  cpu_data_i = RTC_GET_TIME;
119 26 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
120 
  do {
121 33 edn_walter 
    cpu_addr_i = RTC_CTRL;
122 26 edn_walter 
    cpu_rd(cpu_addr_i, &cpu_data_o);
123 
    //printf("%08x\n", (cpu_data_o & 0x1));
124 33 edn_walter 
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
125 
  cpu_addr_i = RTC_TIME_SEC_H_READ;
126 26 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
127 
  printf("\ntime: \n%08x\n", cpu_data_o);
128 33 edn_walter 
  cpu_addr_i = RTC_TIME_SEC_L_READ;
129 26 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
130 
  printf("%08x\n", cpu_data_o);
131 33 edn_walter 
  cpu_addr_i = RTC_TIME_NSC_H_READ;
132 26 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
133 
  printf("%08x\n", cpu_data_o);
134 33 edn_walter 
  cpu_addr_i = RTC_TIME_NSC_L_READ;
135 26 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
136 
  printf("%08x\n", cpu_data_o);
137 22 edn_walter 
  // LOAD RTC SEC AND NS
138 33 edn_walter 
  cpu_addr_i = RTC_TIME_SEC_H_LOAD;
139 22 edn_walter 
  cpu_data_i = 0x0;
140 
  cpu_wr(cpu_addr_i, cpu_data_i);
141 33 edn_walter 
  cpu_addr_i = RTC_TIME_SEC_L_LOAD;
142 22 edn_walter 
  cpu_data_i = 0x1;
143 
  cpu_wr(cpu_addr_i, cpu_data_i);
144 33 edn_walter 
  cpu_addr_i = RTC_TIME_NSC_H_LOAD;
145 
  cpu_data_i = RTC_ACCMOD_H - 0xA;
146 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
147 33 edn_walter 
  cpu_addr_i = RTC_TIME_NSC_L_LOAD;
148 22 edn_walter 
  cpu_data_i = 0x0;
149 
  cpu_wr(cpu_addr_i, cpu_data_i);
150 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
151 
  cpu_data_i = RTC_SET_CTRL_0;
152 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
153 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
154 
  cpu_data_i = RTC_SET_TIME;
155 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
156 
  // LOAD RTC ADJ
157 33 edn_walter 
  cpu_addr_i = RTC_ADJNUM_LOAD;
158 22 edn_walter 
  cpu_data_i = 0x100;
159 
  cpu_wr(cpu_addr_i, cpu_data_i);
160 33 edn_walter 
  cpu_addr_i = RTC_ADJPER_H_LOAD;
161 22 edn_walter 
  cpu_data_i = 0x1;
162 
  cpu_wr(cpu_addr_i, cpu_data_i);
163 33 edn_walter 
  cpu_addr_i = RTC_ADJPER_L_LOAD;
164 22 edn_walter 
  cpu_data_i = 0x20;
165 
  cpu_wr(cpu_addr_i, cpu_data_i);
166 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
167 
  cpu_data_i = RTC_SET_CTRL_0;
168 23 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
169 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
170 
  cpu_data_i = RTC_SET_ADJ;
171 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
172 23 edn_walter 
  // READ RTC SEC AND NS
173 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
174 
  cpu_data_i = RTC_SET_CTRL_0;
175 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
176 33 edn_walter 
  cpu_addr_i = RTC_CTRL;
177 
  cpu_data_i = RTC_GET_TIME;
178 22 edn_walter 
  cpu_wr(cpu_addr_i, cpu_data_i);
179 24 edn_walter 
  do {
180 33 edn_walter 
    cpu_addr_i = RTC_CTRL;
181 24 edn_walter 
    cpu_rd(cpu_addr_i, &cpu_data_o);
182 
    //printf("%08x\n", (cpu_data_o & 0x1));
183 33 edn_walter 
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
184 
  cpu_addr_i = RTC_TIME_SEC_H_READ;
185 23 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
186 26 edn_walter 
  printf("\ntime: \n%08x\n", cpu_data_o);
187 33 edn_walter 
  cpu_addr_i = RTC_TIME_SEC_L_READ;
188 23 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
189 26 edn_walter 
  printf("%08x\n", cpu_data_o);
190 33 edn_walter 
  cpu_addr_i = RTC_TIME_NSC_H_READ;
191 23 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
192 26 edn_walter 
  printf("%08x\n", cpu_data_o);
193 33 edn_walter 
  cpu_addr_i = RTC_TIME_NSC_L_READ;
194 23 edn_walter 
  cpu_rd(cpu_addr_i, &cpu_data_o);
195 26 edn_walter 
  printf("%08x\n", cpu_data_o);
196 22 edn_walter 
 
197 24 edn_walter 
  int i;
198 33 edn_walter 
  int rx_queue_num;
199 
  int tx_queue_num;
200 
  while (1) {
201 24 edn_walter 
  // POLL TSU RX STATUS
202 33 edn_walter 
  cpu_addr_i = TSU_RXQUE_STATUS;
203 
  cpu_rd(cpu_addr_i, &cpu_data_o);
204 
  rx_queue_num = cpu_data_o;
205 
  //printf("%08x\n", rx_queue_num);
206 
  if (rx_queue_num > 0x0) {
207 
    // READ TSU RX FIFO
208 
    for (i=rx_queue_num; i>0; i--) {
209 
      cpu_addr_i = TSU_CTRL;
210 
      cpu_data_i = TSU_SET_CTRL_0;
211 24 edn_walter 
      cpu_wr(cpu_addr_i, cpu_data_i);
212 33 edn_walter 
      cpu_addr_i = TSU_CTRL;
213 
      cpu_data_i = TSU_GET_RXQUE;
214 24 edn_walter 
      cpu_wr(cpu_addr_i, cpu_data_i);
215 31 edn_walter 
      do {
216 33 edn_walter 
        cpu_addr_i = TSU_CTRL;
217 31 edn_walter 
        cpu_rd(cpu_addr_i, &cpu_data_o);
218 
        //printf("%08x\n", (cpu_data_o & 0x1));
219 33 edn_walter 
      } while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
220 
      cpu_addr_i = TSU_RXQUE_DATA_H;
221 24 edn_walter 
      cpu_rd(cpu_addr_i, &cpu_data_o);
222 26 edn_walter 
      printf("\nRx stamp: \n%08x\n", cpu_data_o);
223 33 edn_walter 
      cpu_addr_i = TSU_RXQUE_DATA_L;
224 24 edn_walter 
      cpu_rd(cpu_addr_i, &cpu_data_o);
225 26 edn_walter 
      printf("%08x\n", cpu_data_o);
226 33 edn_walter 
    }
227 24 edn_walter 
  }
228 
  // POLL TSU TX STATUS
229 33 edn_walter 
  cpu_addr_i = TSU_TXQUE_STATUS;
230 
  cpu_rd(cpu_addr_i, &cpu_data_o);
231 
  tx_queue_num = cpu_data_o;
232 
  //printf("%08x\n", tx_queue_num);
233 
  if (tx_queue_num > 0x0) {
234 
    // READ TSU TX FIFO
235 
    for (i=tx_queue_num; i>0; i--) {
236 
      cpu_addr_i = TSU_CTRL;
237 
      cpu_data_i = TSU_SET_CTRL_0;
238 24 edn_walter 
      cpu_wr(cpu_addr_i, cpu_data_i);
239 33 edn_walter 
      cpu_addr_i = TSU_CTRL;
240 
      cpu_data_i = TSU_GET_TXQUE;
241 24 edn_walter 
      cpu_wr(cpu_addr_i, cpu_data_i);
242 31 edn_walter 
      do {
243 33 edn_walter 
        cpu_addr_i = TSU_CTRL;
244 31 edn_walter 
        cpu_rd(cpu_addr_i, &cpu_data_o);
245 
        //printf("%08x\n", (cpu_data_o & 0x1));
246 33 edn_walter 
      } while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
247 
      cpu_addr_i = TSU_TXQUE_DATA_H;
248 24 edn_walter 
      cpu_rd(cpu_addr_i, &cpu_data_o);
249 26 edn_walter 
      printf("\nTx stamp: \n%08x\n", cpu_data_o);
250 33 edn_walter 
      cpu_addr_i = TSU_TXQUE_DATA_L;
251 24 edn_walter 
      cpu_rd(cpu_addr_i, &cpu_data_o);
252 26 edn_walter 
      printf("%08x\n", cpu_data_o);
253 33 edn_walter 
    }
254 24 edn_walter 
  }
255 33 edn_walter 
  }
256 24 edn_walter 
 
257 22 edn_walter 
  // READ BACK ALL REGISTERS
258 
  for (;;)
259 21 edn_walter 
  {
260 22 edn_walter 
    int t;
261 
    for (t=0; t<=0x5c; t=t+4)
262 
    {
263 24 edn_walter 
      cpu_hd(10);
264 
 
265 22 edn_walter 
      cpu_addr_i = t;
266 21 edn_walter 
      cpu_rd(cpu_addr_i, &cpu_data_o);
267 22 edn_walter 
    }
268 21 edn_walter 
  }
269 
 
270 
  return(0); /* Return success (required by tasks) */
271 
}

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