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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 38

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/*
 * ptp_drv_bfm.c
 *
 * Copyright (c) 2012, BABY&HW. All rights reserved.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301  USA
 */
 
#include <stdio.h>
 
#include "svdpi.h"
#include "../dpiheader.h"
 
// define RTC address values
#define RTC_CTRL       0x00000000
#define RTC_NULL_0x4   0x00000004
#define RTC_NULL_0x8   0x00000008
#define RTC_NULL_0xC   0x0000000C
#define RTC_TIME_SEC_H 0x00000010
#define RTC_TIME_SEC_L 0x00000014
#define RTC_TIME_NSC_H 0x00000018
#define RTC_TIME_NSC_L 0x0000001C
#define RTC_PERIOD_H   0x00000020
#define RTC_PERIOD_L   0x00000024
#define RTC_ADJPER_H   0x00000028
#define RTC_ADJPER_L   0x0000002C
#define RTC_ADJNUM     0x00000030
#define RTC_NULL_0x34  0x00000034
#define RTC_NULL_0x38  0x00000038
#define RTC_NULL_0x3C  0x0000003C
// define RTC control values
#define RTC_SET_CTRL_0   0x00
#define RTC_GET_TIME     0x01
#define RTC_SET_ADJ      0x02
#define RTC_SET_PERIOD   0x04
#define RTC_SET_TIME     0x08
#define RTC_SET_RESET    0x10
// define RTC data values
#define RTC_SET_PERIOD_H 0x8         // 8ns for 125MHz rtc_clk
#define RTC_SET_PERIOD_L 0x0
// define RTC constant
#define RTC_ACCMOD_H     0x3B9ACA00  // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L     0x0         // 256 for 8bit
 
// define TSU address values
#define TSU_CTRL          0x00000040
#define TSU_RXQUE_STATUS  0x00000044
#define TSU_TXQUE_STATUS  0x00000048
#define TSU_NULL_0x4C     0x0000004C
#define TSU_NULL_0x50     0x00000050
#define TSU_NULL_0x54     0x00000054
#define TSU_NULL_0x58     0x00000058
#define TSU_NULL_0x5C     0x0000005C
#define TSU_RXQUE_DATA_HH 0x00000060
#define TSU_RXQUE_DATA_HL 0x00000064
#define TSU_RXQUE_DATA_LH 0x00000068
#define TSU_RXQUE_DATA_LL 0x0000006C
#define TSU_TXQUE_DATA_HH 0x00000070
#define TSU_TXQUE_DATA_HL 0x00000074
#define TSU_TXQUE_DATA_LH 0x00000078
#define TSU_TXQUE_DATA_LL 0x0000007C
// define TSU control values
#define TSU_SET_CTRL_0 0x00
#define TSU_GET_TXQUE  0x01
#define TSU_SET_TXRST  0x02
#define TSU_GET_RXQUE  0x04
#define TSU_SET_RXRST  0x08
 
int ptp_drv_bfm_c(double fw_delay)
{
  unsigned int cpu_addr_i;
  unsigned int cpu_data_i;
  unsigned int cpu_data_o;
 
  // LOAD RTC PERIOD
  cpu_addr_i = RTC_PERIOD_H;
  cpu_data_i = RTC_SET_PERIOD_H;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_PERIOD_L;
  cpu_data_i = RTC_SET_PERIOD_L;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_PERIOD;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // RESET RTC
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_RESET;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ RTC SEC AND NS
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_GET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("\ntime: \n%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  // LOAD RTC SEC AND NS
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_data_i = RTC_ACCMOD_H - 0xA;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // LOAD RTC ADJ
  cpu_addr_i = RTC_ADJNUM;
  cpu_data_i = 0x100;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_ADJPER_H;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_ADJPER_L;
  cpu_data_i = 0x20;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_ADJ;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_SET_ADJ) == 0x0);
 
  // READ RTC SEC AND NS
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_GET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("\ntime: \n%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  int i;
  int rx_queue_num;
  int tx_queue_num;
 
  // RESET TSU
  cpu_addr_i = TSU_CTRL;
  cpu_data_i = TSU_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_CTRL;
  cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ TSU
  while (1) {
 
    // POLL TSU RX STATUS
    cpu_addr_i = TSU_RXQUE_STATUS;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    rx_queue_num = cpu_data_o;
    //printf("%08x\n", rx_queue_num);
 
    if (rx_queue_num > 0x0) {
      for (i=rx_queue_num; i>0; i--) {
 
        // READ TSU RX FIFO
        cpu_addr_i = TSU_CTRL;
        cpu_data_i = TSU_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = TSU_CTRL;
        cpu_data_i = TSU_GET_RXQUE;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = TSU_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
 
        cpu_addr_i = TSU_RXQUE_DATA_HH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\nRx stamp: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_HL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_LH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_LL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        // READ RTC SEC AND NS
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_GET_TIME;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = RTC_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
        cpu_addr_i = RTC_TIME_SEC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\ntime: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_SEC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
      }
    }
 
    // POLL TSU TX STATUS
    cpu_addr_i = TSU_TXQUE_STATUS;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    tx_queue_num = cpu_data_o;
    //printf("%08x\n", tx_queue_num);
 
    if (tx_queue_num > 0x0) {
      for (i=tx_queue_num; i>0; i--) {
 
        // READ TSU TX FIFO
        cpu_addr_i = TSU_CTRL;
        cpu_data_i = TSU_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = TSU_CTRL;
        cpu_data_i = TSU_GET_TXQUE;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = TSU_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
 
        cpu_addr_i = TSU_TXQUE_DATA_HH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\nTx stamp: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_TXQUE_DATA_HL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_TXQUE_DATA_LH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
         cpu_addr_i = TSU_TXQUE_DATA_LL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        // READ RTC SEC AND NS
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_GET_TIME;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = RTC_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
        cpu_addr_i = RTC_TIME_SEC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\ntime: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_SEC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
      }
    }
  }
 
  // READ BACK ALL REGISTERS
  for (;;)
  {
    int t;
    for (t=0; t<=0xff; t=t+4)
    {
      cpu_hd(10);
 
      cpu_addr_i = t;
      cpu_rd(cpu_addr_i, &cpu_data_o);
    }
  }
 
  return(0); /* Return success (required by tasks) */
}

Line No.	Rev	Author	Line
1	34	edn_walter	`/*`
2	38	edn_walter	`* ptp_drv_bfm.c`
3	34	edn_walter	`*`
4	37	edn_walter	`* Copyright (c) 2012, BABY&HW. All rights reserved.`
5	34	edn_walter	`*`
6			`* This library is free software; you can redistribute it and/or`
7			`* modify it under the terms of the GNU Lesser General Public`
8			`* License as published by the Free Software Foundation; either`
9			`* version 2.1 of the License, or (at your option) any later version.`
10			`*`
11			`* This library is distributed in the hope that it will be useful,`
12			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`* Lesser General Public License for more details.`
15			`*`
16			`* You should have received a copy of the GNU Lesser General Public`
17			`* License along with this library; if not, write to the Free Software`
18			`* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,`
19			`* MA 02110-1301 USA`
20			`*/`
21
22	21	edn_walter	`#include <stdio.h>`
23
24			`#include "svdpi.h"`
25			`#include "../dpiheader.h"`
26	33	edn_walter
27			`// define RTC address values`
28	38	edn_walter	`#define RTC_CTRL 0x00000000`
29			`#define RTC_NULL_0x4 0x00000004`
30			`#define RTC_NULL_0x8 0x00000008`
31			`#define RTC_NULL_0xC 0x0000000C`
32			`#define RTC_TIME_SEC_H 0x00000010`
33			`#define RTC_TIME_SEC_L 0x00000014`
34			`#define RTC_TIME_NSC_H 0x00000018`
35			`#define RTC_TIME_NSC_L 0x0000001C`
36			`#define RTC_PERIOD_H 0x00000020`
37			`#define RTC_PERIOD_L 0x00000024`
38			`#define RTC_ADJPER_H 0x00000028`
39			`#define RTC_ADJPER_L 0x0000002C`
40			`#define RTC_ADJNUM 0x00000030`
41			`#define RTC_NULL_0x34 0x00000034`
42			`#define RTC_NULL_0x38 0x00000038`
43			`#define RTC_NULL_0x3C 0x0000003C`
44			`// define RTC control values`
45			`#define RTC_SET_CTRL_0 0x00`
46			`#define RTC_GET_TIME 0x01`
47			`#define RTC_SET_ADJ 0x02`
48			`#define RTC_SET_PERIOD 0x04`
49			`#define RTC_SET_TIME 0x08`
50			`#define RTC_SET_RESET 0x10`
51	33	edn_walter	`// define RTC data values`
52	38	edn_walter	`#define RTC_SET_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk`
53			`#define RTC_SET_PERIOD_L 0x0`
54			`// define RTC constant`
55			`#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit`
56			`#define RTC_ACCMOD_L 0x0 // 256 for 8bit`
57	33	edn_walter
58			`// define TSU address values`
59	38	edn_walter	`#define TSU_CTRL 0x00000040`
60			`#define TSU_RXQUE_STATUS 0x00000044`
61			`#define TSU_TXQUE_STATUS 0x00000048`
62			`#define TSU_NULL_0x4C 0x0000004C`
63			`#define TSU_NULL_0x50 0x00000050`
64			`#define TSU_NULL_0x54 0x00000054`
65			`#define TSU_NULL_0x58 0x00000058`
66	37	edn_walter	`#define TSU_NULL_0x5C 0x0000005C`
67			`#define TSU_RXQUE_DATA_HH 0x00000060`
68			`#define TSU_RXQUE_DATA_HL 0x00000064`
69			`#define TSU_RXQUE_DATA_LH 0x00000068`
70			`#define TSU_RXQUE_DATA_LL 0x0000006C`
71			`#define TSU_TXQUE_DATA_HH 0x00000070`
72			`#define TSU_TXQUE_DATA_HL 0x00000074`
73			`#define TSU_TXQUE_DATA_LH 0x00000078`
74			`#define TSU_TXQUE_DATA_LL 0x0000007C`
75	38	edn_walter	`// define TSU control values`
76			`#define TSU_SET_CTRL_0 0x00`
77			`#define TSU_GET_TXQUE 0x01`
78			`#define TSU_SET_TXRST 0x02`
79			`#define TSU_GET_RXQUE 0x04`
80			`#define TSU_SET_RXRST 0x08`
81	33	edn_walter
82	21	edn_walter	`int ptp_drv_bfm_c(double fw_delay)`
83			`{`
84	26	edn_walter	`unsigned int cpu_addr_i;`
85			`unsigned int cpu_data_i;`
86			`unsigned int cpu_data_o;`
87	21	edn_walter
88	38	edn_walter	`// LOAD RTC PERIOD`
89			`cpu_addr_i = RTC_PERIOD_H;`
90			`cpu_data_i = RTC_SET_PERIOD_H;`
91	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
92	37	edn_walter
93	38	edn_walter	`cpu_addr_i = RTC_PERIOD_L;`
94			`cpu_data_i = RTC_SET_PERIOD_L;`
95	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
96	37	edn_walter
97	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
98			`cpu_data_i = RTC_SET_CTRL_0;`
99	23	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
100	37	edn_walter
101	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
102			`cpu_data_i = RTC_SET_PERIOD;`
103	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
104	37	edn_walter
105			`// RESET RTC`
106	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
107			`cpu_data_i = RTC_SET_CTRL_0;`
108	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
109	37	edn_walter
110	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
111			`cpu_data_i = RTC_SET_RESET;`
112	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
113	37	edn_walter
114	26	edn_walter	`// READ RTC SEC AND NS`
115	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
116			`cpu_data_i = RTC_SET_CTRL_0;`
117	26	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
118	37	edn_walter
119	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
120			`cpu_data_i = RTC_GET_TIME;`
121	26	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
122	37	edn_walter
123	26	edn_walter	`do {`
124	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
125	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
126	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
127	33	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
128	37	edn_walter
129	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
130	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
131			`printf("\ntime: \n%08x\n", cpu_data_o);`
132	37	edn_walter
133	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
134	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
135			`printf("%08x\n", cpu_data_o);`
136	37	edn_walter
137	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
138	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
139			`printf("%08x\n", cpu_data_o);`
140	37	edn_walter
141	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
142	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
143			`printf("%08x\n", cpu_data_o);`
144	37	edn_walter
145	22	edn_walter	`// LOAD RTC SEC AND NS`
146	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
147	22	edn_walter	`cpu_data_i = 0x0;`
148			`cpu_wr(cpu_addr_i, cpu_data_i);`
149	37	edn_walter
150	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
151	22	edn_walter	`cpu_data_i = 0x1;`
152			`cpu_wr(cpu_addr_i, cpu_data_i);`
153	37	edn_walter
154	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
155	33	edn_walter	`cpu_data_i = RTC_ACCMOD_H - 0xA;`
156	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
157	37	edn_walter
158	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
159	22	edn_walter	`cpu_data_i = 0x0;`
160			`cpu_wr(cpu_addr_i, cpu_data_i);`
161	37	edn_walter
162	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
163			`cpu_data_i = RTC_SET_CTRL_0;`
164	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
165	37	edn_walter
166	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
167			`cpu_data_i = RTC_SET_TIME;`
168	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
169	37	edn_walter
170	22	edn_walter	`// LOAD RTC ADJ`
171	38	edn_walter	`cpu_addr_i = RTC_ADJNUM;`
172	22	edn_walter	`cpu_data_i = 0x100;`
173			`cpu_wr(cpu_addr_i, cpu_data_i);`
174	37	edn_walter
175	38	edn_walter	`cpu_addr_i = RTC_ADJPER_H;`
176	22	edn_walter	`cpu_data_i = 0x1;`
177			`cpu_wr(cpu_addr_i, cpu_data_i);`
178	37	edn_walter
179	38	edn_walter	`cpu_addr_i = RTC_ADJPER_L;`
180	22	edn_walter	`cpu_data_i = 0x20;`
181			`cpu_wr(cpu_addr_i, cpu_data_i);`
182	37	edn_walter
183	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
184			`cpu_data_i = RTC_SET_CTRL_0;`
185	23	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
186	37	edn_walter
187	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
188			`cpu_data_i = RTC_SET_ADJ;`
189	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
190	37	edn_walter
191	38	edn_walter	`do {`
192			`cpu_addr_i = RTC_CTRL;`
193			`cpu_rd(cpu_addr_i, &cpu_data_o);`
194			`//printf("%08x\n", cpu_data_o);`
195			`} while ((cpu_data_o & RTC_SET_ADJ) == 0x0);`
196
197	23	edn_walter	`// READ RTC SEC AND NS`
198	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
199			`cpu_data_i = RTC_SET_CTRL_0;`
200	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
201	37	edn_walter
202	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
203			`cpu_data_i = RTC_GET_TIME;`
204	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
205	37	edn_walter
206	24	edn_walter	`do {`
207	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
208	24	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
209	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
210	33	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
211	37	edn_walter
212	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
213	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
214	26	edn_walter	`printf("\ntime: \n%08x\n", cpu_data_o);`
215	37	edn_walter
216	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
217	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
218	26	edn_walter	`printf("%08x\n", cpu_data_o);`
219	37	edn_walter
220	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
221	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
222	26	edn_walter	`printf("%08x\n", cpu_data_o);`
223	37	edn_walter
224	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
225	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
226	26	edn_walter	`printf("%08x\n", cpu_data_o);`
227	22	edn_walter
228	24	edn_walter	`int i;`
229	33	edn_walter	`int rx_queue_num;`
230			`int tx_queue_num;`
231	37	edn_walter
232			`// RESET TSU`
233			`cpu_addr_i = TSU_CTRL;`
234			`cpu_data_i = TSU_SET_CTRL_0;`
235			`cpu_wr(cpu_addr_i, cpu_data_i);`
236
237			`cpu_addr_i = TSU_CTRL;`
238			`cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;`
239			`cpu_wr(cpu_addr_i, cpu_data_i);`
240
241			`// READ TSU`
242	33	edn_walter	`while (1) {`
243	37	edn_walter
244			`// POLL TSU RX STATUS`
245			`cpu_addr_i = TSU_RXQUE_STATUS;`
246			`cpu_rd(cpu_addr_i, &cpu_data_o);`
247			`rx_queue_num = cpu_data_o;`
248			`//printf("%08x\n", rx_queue_num);`
249
250			`if (rx_queue_num > 0x0) {`
251			`for (i=rx_queue_num; i>0; i--) {`
252
253			`// READ TSU RX FIFO`
254	33	edn_walter	`cpu_addr_i = TSU_CTRL;`
255	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
256			`cpu_wr(cpu_addr_i, cpu_data_i);`
257
258			`cpu_addr_i = TSU_CTRL;`
259			`cpu_data_i = TSU_GET_RXQUE;`
260			`cpu_wr(cpu_addr_i, cpu_data_i);`
261
262			`do {`
263			`cpu_addr_i = TSU_CTRL;`
264			`cpu_rd(cpu_addr_i, &cpu_data_o);`
265	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
266	37	edn_walter	`} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);`
267
268			`cpu_addr_i = TSU_RXQUE_DATA_HH;`
269	31	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
270	37	edn_walter	`printf("\nRx stamp: \n%08x\n", cpu_data_o);`
271
272			`cpu_addr_i = TSU_RXQUE_DATA_HL;`
273			`cpu_rd(cpu_addr_i, &cpu_data_o);`
274			`printf("%08x\n", cpu_data_o);`
275
276			`cpu_addr_i = TSU_RXQUE_DATA_LH;`
277			`cpu_rd(cpu_addr_i, &cpu_data_o);`
278			`printf("%08x\n", cpu_data_o);`
279
280			`cpu_addr_i = TSU_RXQUE_DATA_LL;`
281			`cpu_rd(cpu_addr_i, &cpu_data_o);`
282			`printf("%08x\n", cpu_data_o);`
283
284			`// READ RTC SEC AND NS`
285			`cpu_addr_i = RTC_CTRL;`
286			`cpu_data_i = RTC_SET_CTRL_0;`
287			`cpu_wr(cpu_addr_i, cpu_data_i);`
288
289			`cpu_addr_i = RTC_CTRL;`
290			`cpu_data_i = RTC_GET_TIME;`
291			`cpu_wr(cpu_addr_i, cpu_data_i);`
292
293			`do {`
294			`cpu_addr_i = RTC_CTRL;`
295			`cpu_rd(cpu_addr_i, &cpu_data_o);`
296	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
297	37	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
298
299	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
300	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
301			`printf("\ntime: \n%08x\n", cpu_data_o);`
302
303	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
304	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
305			`printf("%08x\n", cpu_data_o);`
306
307	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
308	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
309			`printf("%08x\n", cpu_data_o);`
310
311	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
312	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
313			`printf("%08x\n", cpu_data_o);`
314			`}`
315	33	edn_walter	`}`
316	37	edn_walter
317			`// POLL TSU TX STATUS`
318			`cpu_addr_i = TSU_TXQUE_STATUS;`
319			`cpu_rd(cpu_addr_i, &cpu_data_o);`
320			`tx_queue_num = cpu_data_o;`
321			`//printf("%08x\n", tx_queue_num);`
322
323			`if (tx_queue_num > 0x0) {`
324			`for (i=tx_queue_num; i>0; i--) {`
325
326			`// READ TSU TX FIFO`
327	33	edn_walter	`cpu_addr_i = TSU_CTRL;`
328	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
329			`cpu_wr(cpu_addr_i, cpu_data_i);`
330
331			`cpu_addr_i = TSU_CTRL;`
332			`cpu_data_i = TSU_GET_TXQUE;`
333			`cpu_wr(cpu_addr_i, cpu_data_i);`
334
335			`do {`
336			`cpu_addr_i = TSU_CTRL;`
337			`cpu_rd(cpu_addr_i, &cpu_data_o);`
338	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
339	37	edn_walter	`} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);`
340
341			`cpu_addr_i = TSU_TXQUE_DATA_HH;`
342	31	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
343	37	edn_walter	`printf("\nTx stamp: \n%08x\n", cpu_data_o);`
344
345			`cpu_addr_i = TSU_TXQUE_DATA_HL;`
346			`cpu_rd(cpu_addr_i, &cpu_data_o);`
347			`printf("%08x\n", cpu_data_o);`
348
349			`cpu_addr_i = TSU_TXQUE_DATA_LH;`
350			`cpu_rd(cpu_addr_i, &cpu_data_o);`
351			`printf("%08x\n", cpu_data_o);`
352
353			`cpu_addr_i = TSU_TXQUE_DATA_LL;`
354			`cpu_rd(cpu_addr_i, &cpu_data_o);`
355			`printf("%08x\n", cpu_data_o);`
356
357			`// READ RTC SEC AND NS`
358			`cpu_addr_i = RTC_CTRL;`
359			`cpu_data_i = RTC_SET_CTRL_0;`
360			`cpu_wr(cpu_addr_i, cpu_data_i);`
361
362			`cpu_addr_i = RTC_CTRL;`
363			`cpu_data_i = RTC_GET_TIME;`
364			`cpu_wr(cpu_addr_i, cpu_data_i);`
365
366			`do {`
367			`cpu_addr_i = RTC_CTRL;`
368			`cpu_rd(cpu_addr_i, &cpu_data_o);`
369	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
370	37	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
371
372	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
373	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
374			`printf("\ntime: \n%08x\n", cpu_data_o);`
375
376	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
377	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
378			`printf("%08x\n", cpu_data_o);`
379
380	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
381	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
382			`printf("%08x\n", cpu_data_o);`
383
384	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
385	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
386			`printf("%08x\n", cpu_data_o);`
387			`}`
388	33	edn_walter	`}`
389	24	edn_walter	`}`
390
391	22	edn_walter	`// READ BACK ALL REGISTERS`
392			`for (;;)`
393	21	edn_walter	`{`
394	22	edn_walter	`int t;`
395	37	edn_walter	`for (t=0; t<=0xff; t=t+4)`
396	22	edn_walter	`{`
397	24	edn_walter	`cpu_hd(10);`
398
399	22	edn_walter	`cpu_addr_i = t;`
400	21	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
401	22	edn_walter	`}`
402	21	edn_walter	`}`
403
404			`return(0); /* Return success (required by tasks) */`
405			`}`

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