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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 44

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/*
 * ptp_drv_bfm.c
 *
 * Copyright (c) 2012, BABY&HW. All rights reserved.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301  USA
 */
 
#include <stdio.h>
 
#include "svdpi.h"
#include "../dpiheader.h"
 
// define RTC address values
#define RTC_CTRL       0x00000000
#define RTC_NULL_0x04  0x00000004
#define RTC_NULL_0x08  0x00000008
#define RTC_NULL_0x0C  0x0000000C
#define RTC_TIME_SEC_H 0x00000010
#define RTC_TIME_SEC_L 0x00000014
#define RTC_TIME_NSC_H 0x00000018
#define RTC_TIME_NSC_L 0x0000001C
#define RTC_PERIOD_H   0x00000020
#define RTC_PERIOD_L   0x00000024
#define RTC_ADJPER_H   0x00000028
#define RTC_ADJPER_L   0x0000002C
#define RTC_ADJNUM     0x00000030
#define RTC_NULL_0x34  0x00000034
#define RTC_NULL_0x38  0x00000038
#define RTC_NULL_0x3C  0x0000003C
// define RTC control values
#define RTC_SET_CTRL_0 0x00
#define RTC_GET_TIME   0x01
#define RTC_SET_ADJ    0x02
#define RTC_SET_PERIOD 0x04
#define RTC_SET_TIME   0x08
#define RTC_SET_RESET  0x10
// define RTC data values
#define RTC_SET_PERIOD_H 0x8     // 8ns for 125MHz rtc_clk
#define RTC_SET_PERIOD_L 0x0
// define RTC constant
#define RTC_ACCMOD_H 0x3B9ACA00  // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0         // 256 for 8bit
 
// define TSU address values
#define TSU_RXCTRL        0x00000040
#define TSU_RXQUE_STATUS  0x00000044
#define TSU_NULL_0x48     0x00000048
#define TSU_NULL_0x4C     0x0000004C
#define TSU_RXQUE_DATA_HH 0x00000050
#define TSU_RXQUE_DATA_HL 0x00000054
#define TSU_RXQUE_DATA_LH 0x00000058
#define TSU_RXQUE_DATA_LL 0x0000005C
#define TSU_TXCTRL        0x00000060
#define TSU_TXQUE_STATUS  0x00000064
#define TSU_NULL_0x68     0x00000068
#define TSU_NULL_0x6C     0x0000006C
#define TSU_TXQUE_DATA_HH 0x00000070
#define TSU_TXQUE_DATA_HL 0x00000074
#define TSU_TXQUE_DATA_LH 0x00000078
#define TSU_TXQUE_DATA_LL 0x0000007C
// define TSU control values
#define TSU_SET_CTRL_0  0x00
#define TSU_GET_RXQUE   0x01
#define TSU_SET_RXRST   0x02
#define TSU_SET_RXMSGID 0xFF000000  // FF to enable 0x0 to 0x7
#define TSU_GET_TXQUE   0x01
#define TSU_SET_TXRST   0x02
#define TSU_SET_TXMSGID 0xFF000000  // FF to enable 0x0 to 0x7
 
int ptp_drv_bfm_c(double fw_delay)
{
  unsigned int cpu_addr_i;
  unsigned int cpu_data_i;
  unsigned int cpu_data_o;
 
  // LOAD RTC PERIOD
  cpu_addr_i = RTC_PERIOD_H;
  cpu_data_i = RTC_SET_PERIOD_H;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_PERIOD_L;
  cpu_data_i = RTC_SET_PERIOD_L;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_PERIOD;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // RESET RTC
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_RESET;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ RTC SEC AND NS
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_GET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("\ntime: \n%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  // LOAD RTC SEC AND NS
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_data_i = RTC_ACCMOD_H - 0xA;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // LOAD RTC ADJ
  cpu_addr_i = RTC_ADJNUM;
  cpu_data_i = 0x100;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_ADJPER_H;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_ADJPER_L;
  cpu_data_i = 0x20;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_ADJ;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_SET_ADJ) == 0x0);
 
  // READ RTC SEC AND NS
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_GET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("\ntime: \n%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  int i;
  int rx_queue_num;
  int tx_queue_num;
 
  // CONFIG TSU
  cpu_addr_i = TSU_RXQUE_STATUS;
  cpu_data_i = TSU_SET_RXMSGID;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_TXQUE_STATUS;
  cpu_data_i = TSU_SET_TXMSGID;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // RESET TSU
  cpu_addr_i = TSU_RXCTRL;
  cpu_data_i = TSU_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_RXCTRL;
  cpu_data_i = TSU_SET_RXRST;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_TXCTRL;
  cpu_data_i = TSU_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_TXCTRL;
  cpu_data_i = TSU_SET_TXRST;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ TSU
  while (1) {
 
    // POLL TSU RX STATUS
    cpu_addr_i = TSU_RXQUE_STATUS;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    rx_queue_num = cpu_data_o & 0x00FFFFFF;
    //printf("%08x\n", rx_queue_num);
 
    if (rx_queue_num > 0x0) {
      for (i=rx_queue_num; i>0; i--) {
 
        // READ TSU RX FIFO
        cpu_addr_i = TSU_RXCTRL;
        cpu_data_i = TSU_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = TSU_RXCTRL;
        cpu_data_i = TSU_GET_RXQUE;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = TSU_RXCTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
 
        cpu_addr_i = TSU_RXQUE_DATA_HH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\nRx stamp: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_HL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_LH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_LL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        // READ RTC SEC AND NS
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_GET_TIME;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = RTC_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
        cpu_addr_i = RTC_TIME_SEC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\ntime: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_SEC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
      }
    }
 
    // POLL TSU TX STATUS
    cpu_addr_i = TSU_TXQUE_STATUS;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    tx_queue_num = cpu_data_o & 0x00FFFFFF;
    //printf("%08x\n", tx_queue_num);
 
    if (tx_queue_num > 0x0) {
      for (i=tx_queue_num; i>0; i--) {
 
        // READ TSU TX FIFO
        cpu_addr_i = TSU_TXCTRL;
        cpu_data_i = TSU_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = TSU_TXCTRL;
        cpu_data_i = TSU_GET_TXQUE;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = TSU_TXCTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
 
        cpu_addr_i = TSU_TXQUE_DATA_HH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\nTx stamp: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_TXQUE_DATA_HL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_TXQUE_DATA_LH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
         cpu_addr_i = TSU_TXQUE_DATA_LL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        // READ RTC SEC AND NS
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_GET_TIME;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = RTC_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
        cpu_addr_i = RTC_TIME_SEC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\ntime: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_SEC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
      }
    }
  }
 
  // READ BACK ALL REGISTERS
  for (;;)
  {
    int t;
    for (t=0; t<=0xff; t=t+4)
    {
      cpu_hd(10);
 
      cpu_addr_i = t;
      cpu_rd(cpu_addr_i, &cpu_data_o);
    }
  }
 
  return(0); /* Return success (required by tasks) */
}

Line No.	Rev	Author	Line
1	34	edn_walter	`/*`
2	38	edn_walter	`* ptp_drv_bfm.c`
3	34	edn_walter	`*`
4	37	edn_walter	`* Copyright (c) 2012, BABY&HW. All rights reserved.`
5	34	edn_walter	`*`
6			`* This library is free software; you can redistribute it and/or`
7			`* modify it under the terms of the GNU Lesser General Public`
8			`* License as published by the Free Software Foundation; either`
9			`* version 2.1 of the License, or (at your option) any later version.`
10			`*`
11			`* This library is distributed in the hope that it will be useful,`
12			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`* Lesser General Public License for more details.`
15			`*`
16			`* You should have received a copy of the GNU Lesser General Public`
17			`* License along with this library; if not, write to the Free Software`
18			`* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,`
19			`* MA 02110-1301 USA`
20			`*/`
21
22	21	edn_walter	`#include <stdio.h>`
23
24			`#include "svdpi.h"`
25			`#include "../dpiheader.h"`
26	33	edn_walter
27			`// define RTC address values`
28	38	edn_walter	`#define RTC_CTRL 0x00000000`
29	39	edn_walter	`#define RTC_NULL_0x04 0x00000004`
30			`#define RTC_NULL_0x08 0x00000008`
31			`#define RTC_NULL_0x0C 0x0000000C`
32	38	edn_walter	`#define RTC_TIME_SEC_H 0x00000010`
33			`#define RTC_TIME_SEC_L 0x00000014`
34			`#define RTC_TIME_NSC_H 0x00000018`
35			`#define RTC_TIME_NSC_L 0x0000001C`
36			`#define RTC_PERIOD_H 0x00000020`
37			`#define RTC_PERIOD_L 0x00000024`
38			`#define RTC_ADJPER_H 0x00000028`
39			`#define RTC_ADJPER_L 0x0000002C`
40			`#define RTC_ADJNUM 0x00000030`
41			`#define RTC_NULL_0x34 0x00000034`
42			`#define RTC_NULL_0x38 0x00000038`
43			`#define RTC_NULL_0x3C 0x0000003C`
44			`// define RTC control values`
45	39	edn_walter	`#define RTC_SET_CTRL_0 0x00`
46			`#define RTC_GET_TIME 0x01`
47			`#define RTC_SET_ADJ 0x02`
48			`#define RTC_SET_PERIOD 0x04`
49			`#define RTC_SET_TIME 0x08`
50			`#define RTC_SET_RESET 0x10`
51	33	edn_walter	`// define RTC data values`
52	39	edn_walter	`#define RTC_SET_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk`
53	38	edn_walter	`#define RTC_SET_PERIOD_L 0x0`
54			`// define RTC constant`
55	39	edn_walter	`#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit`
56			`#define RTC_ACCMOD_L 0x0 // 256 for 8bit`
57	33	edn_walter
58			`// define TSU address values`
59	39	edn_walter	`#define TSU_RXCTRL 0x00000040`
60	38	edn_walter	`#define TSU_RXQUE_STATUS 0x00000044`
61	39	edn_walter	`#define TSU_NULL_0x48 0x00000048`
62	38	edn_walter	`#define TSU_NULL_0x4C 0x0000004C`
63	39	edn_walter	`#define TSU_RXQUE_DATA_HH 0x00000050`
64			`#define TSU_RXQUE_DATA_HL 0x00000054`
65			`#define TSU_RXQUE_DATA_LH 0x00000058`
66			`#define TSU_RXQUE_DATA_LL 0x0000005C`
67			`#define TSU_TXCTRL 0x00000060`
68			`#define TSU_TXQUE_STATUS 0x00000064`
69			`#define TSU_NULL_0x68 0x00000068`
70			`#define TSU_NULL_0x6C 0x0000006C`
71	37	edn_walter	`#define TSU_TXQUE_DATA_HH 0x00000070`
72			`#define TSU_TXQUE_DATA_HL 0x00000074`
73			`#define TSU_TXQUE_DATA_LH 0x00000078`
74			`#define TSU_TXQUE_DATA_LL 0x0000007C`
75	38	edn_walter	`// define TSU control values`
76	43	edn_walter	`#define TSU_SET_CTRL_0 0x00`
77			`#define TSU_GET_RXQUE 0x01`
78			`#define TSU_SET_RXRST 0x02`
79	44	edn_walter	`#define TSU_SET_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7`
80	43	edn_walter	`#define TSU_GET_TXQUE 0x01`
81			`#define TSU_SET_TXRST 0x02`
82	44	edn_walter	`#define TSU_SET_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7`
83	33	edn_walter
84	21	edn_walter	`int ptp_drv_bfm_c(double fw_delay)`
85			`{`
86	26	edn_walter	`unsigned int cpu_addr_i;`
87			`unsigned int cpu_data_i;`
88			`unsigned int cpu_data_o;`
89	21	edn_walter
90	38	edn_walter	`// LOAD RTC PERIOD`
91			`cpu_addr_i = RTC_PERIOD_H;`
92			`cpu_data_i = RTC_SET_PERIOD_H;`
93	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
94	37	edn_walter
95	38	edn_walter	`cpu_addr_i = RTC_PERIOD_L;`
96			`cpu_data_i = RTC_SET_PERIOD_L;`
97	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
98	37	edn_walter
99	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
100			`cpu_data_i = RTC_SET_CTRL_0;`
101	23	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
102	37	edn_walter
103	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
104			`cpu_data_i = RTC_SET_PERIOD;`
105	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
106	37	edn_walter
107			`// RESET RTC`
108	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
109			`cpu_data_i = RTC_SET_CTRL_0;`
110	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
111	37	edn_walter
112	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
113			`cpu_data_i = RTC_SET_RESET;`
114	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
115	37	edn_walter
116	26	edn_walter	`// READ RTC SEC AND NS`
117	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
118			`cpu_data_i = RTC_SET_CTRL_0;`
119	26	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
120	37	edn_walter
121	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
122			`cpu_data_i = RTC_GET_TIME;`
123	26	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
124	37	edn_walter
125	26	edn_walter	`do {`
126	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
127	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
128	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
129	33	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
130	37	edn_walter
131	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
132	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
133			`printf("\ntime: \n%08x\n", cpu_data_o);`
134	37	edn_walter
135	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
136	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
137			`printf("%08x\n", cpu_data_o);`
138	37	edn_walter
139	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
140	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
141			`printf("%08x\n", cpu_data_o);`
142	37	edn_walter
143	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
144	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
145			`printf("%08x\n", cpu_data_o);`
146	37	edn_walter
147	22	edn_walter	`// LOAD RTC SEC AND NS`
148	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
149	22	edn_walter	`cpu_data_i = 0x0;`
150			`cpu_wr(cpu_addr_i, cpu_data_i);`
151	37	edn_walter
152	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
153	22	edn_walter	`cpu_data_i = 0x1;`
154			`cpu_wr(cpu_addr_i, cpu_data_i);`
155	37	edn_walter
156	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
157	33	edn_walter	`cpu_data_i = RTC_ACCMOD_H - 0xA;`
158	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
159	37	edn_walter
160	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
161	22	edn_walter	`cpu_data_i = 0x0;`
162			`cpu_wr(cpu_addr_i, cpu_data_i);`
163	37	edn_walter
164	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
165			`cpu_data_i = RTC_SET_CTRL_0;`
166	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
167	37	edn_walter
168	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
169			`cpu_data_i = RTC_SET_TIME;`
170	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
171	37	edn_walter
172	22	edn_walter	`// LOAD RTC ADJ`
173	38	edn_walter	`cpu_addr_i = RTC_ADJNUM;`
174	22	edn_walter	`cpu_data_i = 0x100;`
175			`cpu_wr(cpu_addr_i, cpu_data_i);`
176	37	edn_walter
177	38	edn_walter	`cpu_addr_i = RTC_ADJPER_H;`
178	22	edn_walter	`cpu_data_i = 0x1;`
179			`cpu_wr(cpu_addr_i, cpu_data_i);`
180	37	edn_walter
181	38	edn_walter	`cpu_addr_i = RTC_ADJPER_L;`
182	22	edn_walter	`cpu_data_i = 0x20;`
183			`cpu_wr(cpu_addr_i, cpu_data_i);`
184	37	edn_walter
185	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
186			`cpu_data_i = RTC_SET_CTRL_0;`
187	23	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
188	37	edn_walter
189	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
190			`cpu_data_i = RTC_SET_ADJ;`
191	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
192	37	edn_walter
193	38	edn_walter	`do {`
194			`cpu_addr_i = RTC_CTRL;`
195			`cpu_rd(cpu_addr_i, &cpu_data_o);`
196			`//printf("%08x\n", cpu_data_o);`
197			`} while ((cpu_data_o & RTC_SET_ADJ) == 0x0);`
198
199	23	edn_walter	`// READ RTC SEC AND NS`
200	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
201			`cpu_data_i = RTC_SET_CTRL_0;`
202	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
203	37	edn_walter
204	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
205			`cpu_data_i = RTC_GET_TIME;`
206	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
207	37	edn_walter
208	24	edn_walter	`do {`
209	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
210	24	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
211	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
212	33	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
213	37	edn_walter
214	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
215	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
216	26	edn_walter	`printf("\ntime: \n%08x\n", cpu_data_o);`
217	37	edn_walter
218	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
219	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
220	26	edn_walter	`printf("%08x\n", cpu_data_o);`
221	37	edn_walter
222	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
223	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
224	26	edn_walter	`printf("%08x\n", cpu_data_o);`
225	37	edn_walter
226	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
227	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
228	26	edn_walter	`printf("%08x\n", cpu_data_o);`
229	22	edn_walter
230	24	edn_walter	`int i;`
231	33	edn_walter	`int rx_queue_num;`
232			`int tx_queue_num;`
233	37	edn_walter
234	43	edn_walter	`// CONFIG TSU`
235			`cpu_addr_i = TSU_RXQUE_STATUS;`
236			`cpu_data_i = TSU_SET_RXMSGID;`
237			`cpu_wr(cpu_addr_i, cpu_data_i);`
238
239			`cpu_addr_i = TSU_TXQUE_STATUS;`
240			`cpu_data_i = TSU_SET_TXMSGID;`
241			`cpu_wr(cpu_addr_i, cpu_data_i);`
242
243	37	edn_walter	`// RESET TSU`
244	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
245	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
246			`cpu_wr(cpu_addr_i, cpu_data_i);`
247
248	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
249			`cpu_data_i = TSU_SET_RXRST;`
250	37	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
251
252	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
253			`cpu_data_i = TSU_SET_CTRL_0;`
254			`cpu_wr(cpu_addr_i, cpu_data_i);`
255
256			`cpu_addr_i = TSU_TXCTRL;`
257			`cpu_data_i = TSU_SET_TXRST;`
258			`cpu_wr(cpu_addr_i, cpu_data_i);`
259
260	37	edn_walter	`// READ TSU`
261	33	edn_walter	`while (1) {`
262	37	edn_walter
263			`// POLL TSU RX STATUS`
264			`cpu_addr_i = TSU_RXQUE_STATUS;`
265			`cpu_rd(cpu_addr_i, &cpu_data_o);`
266	43	edn_walter	`rx_queue_num = cpu_data_o & 0x00FFFFFF;`
267	37	edn_walter	`//printf("%08x\n", rx_queue_num);`
268
269			`if (rx_queue_num > 0x0) {`
270			`for (i=rx_queue_num; i>0; i--) {`
271
272			`// READ TSU RX FIFO`
273	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
274	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
275			`cpu_wr(cpu_addr_i, cpu_data_i);`
276
277	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
278	37	edn_walter	`cpu_data_i = TSU_GET_RXQUE;`
279			`cpu_wr(cpu_addr_i, cpu_data_i);`
280
281			`do {`
282	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
283	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
284	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
285	37	edn_walter	`} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);`
286
287			`cpu_addr_i = TSU_RXQUE_DATA_HH;`
288	31	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
289	37	edn_walter	`printf("\nRx stamp: \n%08x\n", cpu_data_o);`
290
291			`cpu_addr_i = TSU_RXQUE_DATA_HL;`
292			`cpu_rd(cpu_addr_i, &cpu_data_o);`
293			`printf("%08x\n", cpu_data_o);`
294
295			`cpu_addr_i = TSU_RXQUE_DATA_LH;`
296			`cpu_rd(cpu_addr_i, &cpu_data_o);`
297			`printf("%08x\n", cpu_data_o);`
298
299			`cpu_addr_i = TSU_RXQUE_DATA_LL;`
300			`cpu_rd(cpu_addr_i, &cpu_data_o);`
301			`printf("%08x\n", cpu_data_o);`
302
303			`// READ RTC SEC AND NS`
304			`cpu_addr_i = RTC_CTRL;`
305			`cpu_data_i = RTC_SET_CTRL_0;`
306			`cpu_wr(cpu_addr_i, cpu_data_i);`
307
308			`cpu_addr_i = RTC_CTRL;`
309			`cpu_data_i = RTC_GET_TIME;`
310			`cpu_wr(cpu_addr_i, cpu_data_i);`
311
312			`do {`
313			`cpu_addr_i = RTC_CTRL;`
314			`cpu_rd(cpu_addr_i, &cpu_data_o);`
315	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
316	37	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
317
318	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
319	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
320			`printf("\ntime: \n%08x\n", cpu_data_o);`
321
322	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
323	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
324			`printf("%08x\n", cpu_data_o);`
325
326	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
327	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
328			`printf("%08x\n", cpu_data_o);`
329
330	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
331	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
332			`printf("%08x\n", cpu_data_o);`
333			`}`
334	33	edn_walter	`}`
335	37	edn_walter
336			`// POLL TSU TX STATUS`
337			`cpu_addr_i = TSU_TXQUE_STATUS;`
338			`cpu_rd(cpu_addr_i, &cpu_data_o);`
339	43	edn_walter	`tx_queue_num = cpu_data_o & 0x00FFFFFF;`
340	37	edn_walter	`//printf("%08x\n", tx_queue_num);`
341
342			`if (tx_queue_num > 0x0) {`
343			`for (i=tx_queue_num; i>0; i--) {`
344
345			`// READ TSU TX FIFO`
346	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
347	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
348			`cpu_wr(cpu_addr_i, cpu_data_i);`
349
350	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
351	37	edn_walter	`cpu_data_i = TSU_GET_TXQUE;`
352			`cpu_wr(cpu_addr_i, cpu_data_i);`
353
354			`do {`
355	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
356	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
357	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
358	37	edn_walter	`} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);`
359
360			`cpu_addr_i = TSU_TXQUE_DATA_HH;`
361	31	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
362	37	edn_walter	`printf("\nTx stamp: \n%08x\n", cpu_data_o);`
363
364			`cpu_addr_i = TSU_TXQUE_DATA_HL;`
365			`cpu_rd(cpu_addr_i, &cpu_data_o);`
366			`printf("%08x\n", cpu_data_o);`
367
368			`cpu_addr_i = TSU_TXQUE_DATA_LH;`
369			`cpu_rd(cpu_addr_i, &cpu_data_o);`
370			`printf("%08x\n", cpu_data_o);`
371
372			`cpu_addr_i = TSU_TXQUE_DATA_LL;`
373			`cpu_rd(cpu_addr_i, &cpu_data_o);`
374			`printf("%08x\n", cpu_data_o);`
375
376			`// READ RTC SEC AND NS`
377			`cpu_addr_i = RTC_CTRL;`
378			`cpu_data_i = RTC_SET_CTRL_0;`
379			`cpu_wr(cpu_addr_i, cpu_data_i);`
380
381			`cpu_addr_i = RTC_CTRL;`
382			`cpu_data_i = RTC_GET_TIME;`
383			`cpu_wr(cpu_addr_i, cpu_data_i);`
384
385			`do {`
386			`cpu_addr_i = RTC_CTRL;`
387			`cpu_rd(cpu_addr_i, &cpu_data_o);`
388	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
389	37	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
390
391	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
392	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
393			`printf("\ntime: \n%08x\n", cpu_data_o);`
394
395	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
396	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
397			`printf("%08x\n", cpu_data_o);`
398
399	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
400	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
401			`printf("%08x\n", cpu_data_o);`
402
403	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
404	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
405			`printf("%08x\n", cpu_data_o);`
406			`}`
407	33	edn_walter	`}`
408	24	edn_walter	`}`
409
410	22	edn_walter	`// READ BACK ALL REGISTERS`
411			`for (;;)`
412	21	edn_walter	`{`
413	22	edn_walter	`int t;`
414	37	edn_walter	`for (t=0; t<=0xff; t=t+4)`
415	22	edn_walter	`{`
416	24	edn_walter	`cpu_hd(10);`
417
418	22	edn_walter	`cpu_addr_i = t;`
419	21	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
420	22	edn_walter	`}`
421	21	edn_walter	`}`
422
423			`return(0); /* Return success (required by tasks) */`
424			`}`

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