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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 46

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/*
 * ptp_drv_bfm.c
 *
 * Copyright (c) 2012, BABY&HW. All rights reserved.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301  USA
 */
 
#include <stdio.h>
 
#include "svdpi.h"
#include "../dpiheader.h"
 
// define RTC address values
#define RTC_CTRL       0x00000000
#define RTC_NULL_0x04  0x00000004
#define RTC_NULL_0x08  0x00000008
#define RTC_NULL_0x0C  0x0000000C
#define RTC_TIME_SEC_H 0x00000010
#define RTC_TIME_SEC_L 0x00000014
#define RTC_TIME_NSC_H 0x00000018
#define RTC_TIME_NSC_L 0x0000001C
#define RTC_PERIOD_H   0x00000020
#define RTC_PERIOD_L   0x00000024
#define RTC_ADJPER_H   0x00000028
#define RTC_ADJPER_L   0x0000002C
#define RTC_ADJNUM     0x00000030
#define RTC_NULL_0x34  0x00000034
#define RTC_NULL_0x38  0x00000038
#define RTC_NULL_0x3C  0x0000003C
// define RTC control values
#define RTC_SET_CTRL_0 0x00
#define RTC_GET_TIME   0x01
#define RTC_SET_ADJ    0x02
#define RTC_SET_PERIOD 0x04
#define RTC_SET_TIME   0x08
#define RTC_SET_RESET  0x10
// define RTC data values
#define RTC_SET_PERIOD_H 0x8     // 8ns for 125MHz rtc_clk
#define RTC_SET_PERIOD_L 0x0
// define RTC constant
#define RTC_ACCMOD_H 0x3B9ACA00  // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0         // 256 for 8bit
 
// define TSU address values
#define TSU_RXCTRL        0x00000040
#define TSU_RXQUE_STATUS  0x00000044
#define TSU_NULL_0x48     0x00000048
#define TSU_NULL_0x4C     0x0000004C
#define TSU_RXQUE_DATA_HH 0x00000050
#define TSU_RXQUE_DATA_HL 0x00000054
#define TSU_RXQUE_DATA_LH 0x00000058
#define TSU_RXQUE_DATA_LL 0x0000005C
#define TSU_TXCTRL        0x00000060
#define TSU_TXQUE_STATUS  0x00000064
#define TSU_NULL_0x68     0x00000068
#define TSU_NULL_0x6C     0x0000006C
#define TSU_TXQUE_DATA_HH 0x00000070
#define TSU_TXQUE_DATA_HL 0x00000074
#define TSU_TXQUE_DATA_LH 0x00000078
#define TSU_TXQUE_DATA_LL 0x0000007C
// define TSU control values
#define TSU_SET_CTRL_0  0x00
#define TSU_GET_RXQUE   0x01
#define TSU_SET_RXRST   0x02
#define TSU_GET_TXQUE   0x01
#define TSU_SET_TXRST   0x02
// define TSU data values
#define TSU_MASK_RXMSGID 0xFF000000  // FF to enable 0x0 to 0x7
#define TSU_MASK_TXMSGID 0xFF000000  // FF to enable 0x0 to 0x7
 
int ptp_drv_bfm_c(double fw_delay)
{
  unsigned int cpu_addr_i;
  unsigned int cpu_data_i;
  unsigned int cpu_data_o;
 
  // LOAD RTC PERIOD
  cpu_addr_i = RTC_PERIOD_H;
  cpu_data_i = RTC_SET_PERIOD_H;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_PERIOD_L;
  cpu_data_i = RTC_SET_PERIOD_L;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_PERIOD;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // RESET RTC
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_RESET;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ RTC SEC AND NS
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_GET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("\ntime: \n%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  // LOAD RTC SEC AND NS
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_data_i = RTC_ACCMOD_H - 0xA;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_data_i = 0x0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // LOAD RTC ADJ
  cpu_addr_i = RTC_ADJNUM;
  cpu_data_i = 0x100;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_ADJPER_H;
  cpu_data_i = 0x1;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_ADJPER_L;
  cpu_data_i = 0x20;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_ADJ;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_SET_ADJ) == 0x0);
 
  // READ RTC SEC AND NS
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = RTC_CTRL;
  cpu_data_i = RTC_GET_TIME;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  do {
    cpu_addr_i = RTC_CTRL;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    //printf("%08x\n", cpu_data_o);
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
  cpu_addr_i = RTC_TIME_SEC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("\ntime: \n%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_SEC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_H;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  cpu_addr_i = RTC_TIME_NSC_L;
  cpu_rd(cpu_addr_i, &cpu_data_o);
  printf("%08x\n", cpu_data_o);
 
  int i;
  int rx_queue_num;
  int tx_queue_num;
 
  // CONFIG TSU
  cpu_addr_i = TSU_RXQUE_STATUS;
  cpu_data_i = TSU_MASK_RXMSGID;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_TXQUE_STATUS;
  cpu_data_i = TSU_MASK_TXMSGID;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // RESET TSU
  cpu_addr_i = TSU_RXCTRL;
  cpu_data_i = TSU_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_RXCTRL;
  cpu_data_i = TSU_SET_RXRST;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_TXCTRL;
  cpu_data_i = TSU_SET_CTRL_0;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = TSU_TXCTRL;
  cpu_data_i = TSU_SET_TXRST;
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ TSU
  while (1) {
 
    // POLL TSU RX STATUS
    cpu_addr_i = TSU_RXQUE_STATUS;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    rx_queue_num = cpu_data_o & 0x00FFFFFF;
    //printf("%08x\n", rx_queue_num);
 
    if (rx_queue_num > 0x0) {
      for (i=rx_queue_num; i>0; i--) {
 
        // READ TSU RX FIFO
        cpu_addr_i = TSU_RXCTRL;
        cpu_data_i = TSU_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = TSU_RXCTRL;
        cpu_data_i = TSU_GET_RXQUE;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = TSU_RXCTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
 
        cpu_addr_i = TSU_RXQUE_DATA_HH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\nRx stamp: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_HL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_LH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_RXQUE_DATA_LL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        // READ RTC SEC AND NS
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_GET_TIME;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = RTC_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
        cpu_addr_i = RTC_TIME_SEC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\ntime: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_SEC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
      }
    }
 
    // POLL TSU TX STATUS
    cpu_addr_i = TSU_TXQUE_STATUS;
    cpu_rd(cpu_addr_i, &cpu_data_o);
    tx_queue_num = cpu_data_o & 0x00FFFFFF;
    //printf("%08x\n", tx_queue_num);
 
    if (tx_queue_num > 0x0) {
      for (i=tx_queue_num; i>0; i--) {
 
        // READ TSU TX FIFO
        cpu_addr_i = TSU_TXCTRL;
        cpu_data_i = TSU_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = TSU_TXCTRL;
        cpu_data_i = TSU_GET_TXQUE;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = TSU_TXCTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
 
        cpu_addr_i = TSU_TXQUE_DATA_HH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\nTx stamp: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_TXQUE_DATA_HL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = TSU_TXQUE_DATA_LH;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
         cpu_addr_i = TSU_TXQUE_DATA_LL;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        // READ RTC SEC AND NS
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_SET_CTRL_0;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        cpu_addr_i = RTC_CTRL;
        cpu_data_i = RTC_GET_TIME;
        cpu_wr(cpu_addr_i, cpu_data_i);
 
        do {
          cpu_addr_i = RTC_CTRL;
          cpu_rd(cpu_addr_i, &cpu_data_o);
          //printf("%08x\n", cpu_data_o);
        } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
        cpu_addr_i = RTC_TIME_SEC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("\ntime: \n%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_SEC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_H;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
 
        cpu_addr_i = RTC_TIME_NSC_L;
        cpu_rd(cpu_addr_i, &cpu_data_o);
        printf("%08x\n", cpu_data_o);
      }
    }
  }
 
  // READ BACK ALL REGISTERS
  for (;;)
  {
    int t;
    for (t=0; t<=0xff; t=t+4)
    {
      cpu_hd(10);
 
      cpu_addr_i = t;
      cpu_rd(cpu_addr_i, &cpu_data_o);
    }
  }
 
  return(0); /* Return success (required by tasks) */
}

Line No.	Rev	Author	Line
1	34	edn_walter	`/*`
2	38	edn_walter	`* ptp_drv_bfm.c`
3	34	edn_walter	`*`
4	37	edn_walter	`* Copyright (c) 2012, BABY&HW. All rights reserved.`
5	34	edn_walter	`*`
6			`* This library is free software; you can redistribute it and/or`
7			`* modify it under the terms of the GNU Lesser General Public`
8			`* License as published by the Free Software Foundation; either`
9			`* version 2.1 of the License, or (at your option) any later version.`
10			`*`
11			`* This library is distributed in the hope that it will be useful,`
12			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`* Lesser General Public License for more details.`
15			`*`
16			`* You should have received a copy of the GNU Lesser General Public`
17			`* License along with this library; if not, write to the Free Software`
18			`* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,`
19			`* MA 02110-1301 USA`
20			`*/`
21
22	21	edn_walter	`#include <stdio.h>`
23
24			`#include "svdpi.h"`
25			`#include "../dpiheader.h"`
26	33	edn_walter
27			`// define RTC address values`
28	38	edn_walter	`#define RTC_CTRL 0x00000000`
29	39	edn_walter	`#define RTC_NULL_0x04 0x00000004`
30			`#define RTC_NULL_0x08 0x00000008`
31			`#define RTC_NULL_0x0C 0x0000000C`
32	38	edn_walter	`#define RTC_TIME_SEC_H 0x00000010`
33			`#define RTC_TIME_SEC_L 0x00000014`
34			`#define RTC_TIME_NSC_H 0x00000018`
35			`#define RTC_TIME_NSC_L 0x0000001C`
36			`#define RTC_PERIOD_H 0x00000020`
37			`#define RTC_PERIOD_L 0x00000024`
38			`#define RTC_ADJPER_H 0x00000028`
39			`#define RTC_ADJPER_L 0x0000002C`
40			`#define RTC_ADJNUM 0x00000030`
41			`#define RTC_NULL_0x34 0x00000034`
42			`#define RTC_NULL_0x38 0x00000038`
43			`#define RTC_NULL_0x3C 0x0000003C`
44			`// define RTC control values`
45	39	edn_walter	`#define RTC_SET_CTRL_0 0x00`
46			`#define RTC_GET_TIME 0x01`
47			`#define RTC_SET_ADJ 0x02`
48			`#define RTC_SET_PERIOD 0x04`
49			`#define RTC_SET_TIME 0x08`
50			`#define RTC_SET_RESET 0x10`
51	33	edn_walter	`// define RTC data values`
52	39	edn_walter	`#define RTC_SET_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk`
53	38	edn_walter	`#define RTC_SET_PERIOD_L 0x0`
54			`// define RTC constant`
55	39	edn_walter	`#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit`
56			`#define RTC_ACCMOD_L 0x0 // 256 for 8bit`
57	33	edn_walter
58			`// define TSU address values`
59	39	edn_walter	`#define TSU_RXCTRL 0x00000040`
60	38	edn_walter	`#define TSU_RXQUE_STATUS 0x00000044`
61	39	edn_walter	`#define TSU_NULL_0x48 0x00000048`
62	38	edn_walter	`#define TSU_NULL_0x4C 0x0000004C`
63	39	edn_walter	`#define TSU_RXQUE_DATA_HH 0x00000050`
64			`#define TSU_RXQUE_DATA_HL 0x00000054`
65			`#define TSU_RXQUE_DATA_LH 0x00000058`
66			`#define TSU_RXQUE_DATA_LL 0x0000005C`
67			`#define TSU_TXCTRL 0x00000060`
68			`#define TSU_TXQUE_STATUS 0x00000064`
69			`#define TSU_NULL_0x68 0x00000068`
70			`#define TSU_NULL_0x6C 0x0000006C`
71	37	edn_walter	`#define TSU_TXQUE_DATA_HH 0x00000070`
72			`#define TSU_TXQUE_DATA_HL 0x00000074`
73			`#define TSU_TXQUE_DATA_LH 0x00000078`
74			`#define TSU_TXQUE_DATA_LL 0x0000007C`
75	38	edn_walter	`// define TSU control values`
76	43	edn_walter	`#define TSU_SET_CTRL_0 0x00`
77			`#define TSU_GET_RXQUE 0x01`
78			`#define TSU_SET_RXRST 0x02`
79			`#define TSU_GET_TXQUE 0x01`
80			`#define TSU_SET_TXRST 0x02`
81	46	edn_walter	`// define TSU data values`
82			`#define TSU_MASK_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7`
83			`#define TSU_MASK_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7`
84	33	edn_walter
85	21	edn_walter	`int ptp_drv_bfm_c(double fw_delay)`
86			`{`
87	26	edn_walter	`unsigned int cpu_addr_i;`
88			`unsigned int cpu_data_i;`
89			`unsigned int cpu_data_o;`
90	21	edn_walter
91	38	edn_walter	`// LOAD RTC PERIOD`
92			`cpu_addr_i = RTC_PERIOD_H;`
93			`cpu_data_i = RTC_SET_PERIOD_H;`
94	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
95	37	edn_walter
96	38	edn_walter	`cpu_addr_i = RTC_PERIOD_L;`
97			`cpu_data_i = RTC_SET_PERIOD_L;`
98	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
99	37	edn_walter
100	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
101			`cpu_data_i = RTC_SET_CTRL_0;`
102	23	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
103	37	edn_walter
104	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
105			`cpu_data_i = RTC_SET_PERIOD;`
106	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
107	37	edn_walter
108			`// RESET RTC`
109	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
110			`cpu_data_i = RTC_SET_CTRL_0;`
111	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
112	37	edn_walter
113	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
114			`cpu_data_i = RTC_SET_RESET;`
115	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
116	37	edn_walter
117	26	edn_walter	`// READ RTC SEC AND NS`
118	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
119			`cpu_data_i = RTC_SET_CTRL_0;`
120	26	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
121	37	edn_walter
122	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
123			`cpu_data_i = RTC_GET_TIME;`
124	26	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
125	37	edn_walter
126	26	edn_walter	`do {`
127	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
128	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
129	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
130	33	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
131	37	edn_walter
132	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
133	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
134			`printf("\ntime: \n%08x\n", cpu_data_o);`
135	37	edn_walter
136	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
137	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
138			`printf("%08x\n", cpu_data_o);`
139	37	edn_walter
140	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
141	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
142			`printf("%08x\n", cpu_data_o);`
143	37	edn_walter
144	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
145	26	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
146			`printf("%08x\n", cpu_data_o);`
147	37	edn_walter
148	22	edn_walter	`// LOAD RTC SEC AND NS`
149	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
150	22	edn_walter	`cpu_data_i = 0x0;`
151			`cpu_wr(cpu_addr_i, cpu_data_i);`
152	37	edn_walter
153	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
154	22	edn_walter	`cpu_data_i = 0x1;`
155			`cpu_wr(cpu_addr_i, cpu_data_i);`
156	37	edn_walter
157	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
158	33	edn_walter	`cpu_data_i = RTC_ACCMOD_H - 0xA;`
159	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
160	37	edn_walter
161	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
162	22	edn_walter	`cpu_data_i = 0x0;`
163			`cpu_wr(cpu_addr_i, cpu_data_i);`
164	37	edn_walter
165	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
166			`cpu_data_i = RTC_SET_CTRL_0;`
167	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
168	37	edn_walter
169	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
170			`cpu_data_i = RTC_SET_TIME;`
171	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
172	37	edn_walter
173	22	edn_walter	`// LOAD RTC ADJ`
174	38	edn_walter	`cpu_addr_i = RTC_ADJNUM;`
175	22	edn_walter	`cpu_data_i = 0x100;`
176			`cpu_wr(cpu_addr_i, cpu_data_i);`
177	37	edn_walter
178	38	edn_walter	`cpu_addr_i = RTC_ADJPER_H;`
179	22	edn_walter	`cpu_data_i = 0x1;`
180			`cpu_wr(cpu_addr_i, cpu_data_i);`
181	37	edn_walter
182	38	edn_walter	`cpu_addr_i = RTC_ADJPER_L;`
183	22	edn_walter	`cpu_data_i = 0x20;`
184			`cpu_wr(cpu_addr_i, cpu_data_i);`
185	37	edn_walter
186	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
187			`cpu_data_i = RTC_SET_CTRL_0;`
188	23	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
189	37	edn_walter
190	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
191			`cpu_data_i = RTC_SET_ADJ;`
192	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
193	37	edn_walter
194	38	edn_walter	`do {`
195			`cpu_addr_i = RTC_CTRL;`
196			`cpu_rd(cpu_addr_i, &cpu_data_o);`
197			`//printf("%08x\n", cpu_data_o);`
198			`} while ((cpu_data_o & RTC_SET_ADJ) == 0x0);`
199
200	23	edn_walter	`// READ RTC SEC AND NS`
201	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
202			`cpu_data_i = RTC_SET_CTRL_0;`
203	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
204	37	edn_walter
205	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
206			`cpu_data_i = RTC_GET_TIME;`
207	22	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
208	37	edn_walter
209	24	edn_walter	`do {`
210	33	edn_walter	`cpu_addr_i = RTC_CTRL;`
211	24	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
212	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
213	33	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
214	37	edn_walter
215	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
216	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
217	26	edn_walter	`printf("\ntime: \n%08x\n", cpu_data_o);`
218	37	edn_walter
219	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
220	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
221	26	edn_walter	`printf("%08x\n", cpu_data_o);`
222	37	edn_walter
223	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
224	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
225	26	edn_walter	`printf("%08x\n", cpu_data_o);`
226	37	edn_walter
227	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
228	23	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
229	26	edn_walter	`printf("%08x\n", cpu_data_o);`
230	22	edn_walter
231	24	edn_walter	`int i;`
232	33	edn_walter	`int rx_queue_num;`
233			`int tx_queue_num;`
234	37	edn_walter
235	43	edn_walter	`// CONFIG TSU`
236			`cpu_addr_i = TSU_RXQUE_STATUS;`
237	46	edn_walter	`cpu_data_i = TSU_MASK_RXMSGID;`
238	43	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
239
240			`cpu_addr_i = TSU_TXQUE_STATUS;`
241	46	edn_walter	`cpu_data_i = TSU_MASK_TXMSGID;`
242	43	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
243
244	37	edn_walter	`// RESET TSU`
245	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
246	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
247			`cpu_wr(cpu_addr_i, cpu_data_i);`
248
249	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
250			`cpu_data_i = TSU_SET_RXRST;`
251	37	edn_walter	`cpu_wr(cpu_addr_i, cpu_data_i);`
252
253	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
254			`cpu_data_i = TSU_SET_CTRL_0;`
255			`cpu_wr(cpu_addr_i, cpu_data_i);`
256
257			`cpu_addr_i = TSU_TXCTRL;`
258			`cpu_data_i = TSU_SET_TXRST;`
259			`cpu_wr(cpu_addr_i, cpu_data_i);`
260
261	37	edn_walter	`// READ TSU`
262	33	edn_walter	`while (1) {`
263	37	edn_walter
264			`// POLL TSU RX STATUS`
265			`cpu_addr_i = TSU_RXQUE_STATUS;`
266			`cpu_rd(cpu_addr_i, &cpu_data_o);`
267	43	edn_walter	`rx_queue_num = cpu_data_o & 0x00FFFFFF;`
268	37	edn_walter	`//printf("%08x\n", rx_queue_num);`
269
270			`if (rx_queue_num > 0x0) {`
271			`for (i=rx_queue_num; i>0; i--) {`
272
273			`// READ TSU RX FIFO`
274	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
275	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
276			`cpu_wr(cpu_addr_i, cpu_data_i);`
277
278	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
279	37	edn_walter	`cpu_data_i = TSU_GET_RXQUE;`
280			`cpu_wr(cpu_addr_i, cpu_data_i);`
281
282			`do {`
283	39	edn_walter	`cpu_addr_i = TSU_RXCTRL;`
284	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
285	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
286	37	edn_walter	`} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);`
287
288			`cpu_addr_i = TSU_RXQUE_DATA_HH;`
289	31	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
290	37	edn_walter	`printf("\nRx stamp: \n%08x\n", cpu_data_o);`
291
292			`cpu_addr_i = TSU_RXQUE_DATA_HL;`
293			`cpu_rd(cpu_addr_i, &cpu_data_o);`
294			`printf("%08x\n", cpu_data_o);`
295
296			`cpu_addr_i = TSU_RXQUE_DATA_LH;`
297			`cpu_rd(cpu_addr_i, &cpu_data_o);`
298			`printf("%08x\n", cpu_data_o);`
299
300			`cpu_addr_i = TSU_RXQUE_DATA_LL;`
301			`cpu_rd(cpu_addr_i, &cpu_data_o);`
302			`printf("%08x\n", cpu_data_o);`
303
304			`// READ RTC SEC AND NS`
305			`cpu_addr_i = RTC_CTRL;`
306			`cpu_data_i = RTC_SET_CTRL_0;`
307			`cpu_wr(cpu_addr_i, cpu_data_i);`
308
309			`cpu_addr_i = RTC_CTRL;`
310			`cpu_data_i = RTC_GET_TIME;`
311			`cpu_wr(cpu_addr_i, cpu_data_i);`
312
313			`do {`
314			`cpu_addr_i = RTC_CTRL;`
315			`cpu_rd(cpu_addr_i, &cpu_data_o);`
316	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
317	37	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
318
319	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
320	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
321			`printf("\ntime: \n%08x\n", cpu_data_o);`
322
323	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
324	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
325			`printf("%08x\n", cpu_data_o);`
326
327	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
328	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
329			`printf("%08x\n", cpu_data_o);`
330
331	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
332	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
333			`printf("%08x\n", cpu_data_o);`
334			`}`
335	33	edn_walter	`}`
336	37	edn_walter
337			`// POLL TSU TX STATUS`
338			`cpu_addr_i = TSU_TXQUE_STATUS;`
339			`cpu_rd(cpu_addr_i, &cpu_data_o);`
340	43	edn_walter	`tx_queue_num = cpu_data_o & 0x00FFFFFF;`
341	37	edn_walter	`//printf("%08x\n", tx_queue_num);`
342
343			`if (tx_queue_num > 0x0) {`
344			`for (i=tx_queue_num; i>0; i--) {`
345
346			`// READ TSU TX FIFO`
347	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
348	37	edn_walter	`cpu_data_i = TSU_SET_CTRL_0;`
349			`cpu_wr(cpu_addr_i, cpu_data_i);`
350
351	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
352	37	edn_walter	`cpu_data_i = TSU_GET_TXQUE;`
353			`cpu_wr(cpu_addr_i, cpu_data_i);`
354
355			`do {`
356	39	edn_walter	`cpu_addr_i = TSU_TXCTRL;`
357	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
358	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
359	37	edn_walter	`} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);`
360
361			`cpu_addr_i = TSU_TXQUE_DATA_HH;`
362	31	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
363	37	edn_walter	`printf("\nTx stamp: \n%08x\n", cpu_data_o);`
364
365			`cpu_addr_i = TSU_TXQUE_DATA_HL;`
366			`cpu_rd(cpu_addr_i, &cpu_data_o);`
367			`printf("%08x\n", cpu_data_o);`
368
369			`cpu_addr_i = TSU_TXQUE_DATA_LH;`
370			`cpu_rd(cpu_addr_i, &cpu_data_o);`
371			`printf("%08x\n", cpu_data_o);`
372
373			`cpu_addr_i = TSU_TXQUE_DATA_LL;`
374			`cpu_rd(cpu_addr_i, &cpu_data_o);`
375			`printf("%08x\n", cpu_data_o);`
376
377			`// READ RTC SEC AND NS`
378			`cpu_addr_i = RTC_CTRL;`
379			`cpu_data_i = RTC_SET_CTRL_0;`
380			`cpu_wr(cpu_addr_i, cpu_data_i);`
381
382			`cpu_addr_i = RTC_CTRL;`
383			`cpu_data_i = RTC_GET_TIME;`
384			`cpu_wr(cpu_addr_i, cpu_data_i);`
385
386			`do {`
387			`cpu_addr_i = RTC_CTRL;`
388			`cpu_rd(cpu_addr_i, &cpu_data_o);`
389	38	edn_walter	`//printf("%08x\n", cpu_data_o);`
390	37	edn_walter	`} while ((cpu_data_o & RTC_GET_TIME) == 0x0);`
391
392	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_H;`
393	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
394			`printf("\ntime: \n%08x\n", cpu_data_o);`
395
396	38	edn_walter	`cpu_addr_i = RTC_TIME_SEC_L;`
397	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
398			`printf("%08x\n", cpu_data_o);`
399
400	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_H;`
401	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
402			`printf("%08x\n", cpu_data_o);`
403
404	38	edn_walter	`cpu_addr_i = RTC_TIME_NSC_L;`
405	37	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
406			`printf("%08x\n", cpu_data_o);`
407			`}`
408	33	edn_walter	`}`
409	24	edn_walter	`}`
410
411	22	edn_walter	`// READ BACK ALL REGISTERS`
412			`for (;;)`
413	21	edn_walter	`{`
414	22	edn_walter	`int t;`
415	37	edn_walter	`for (t=0; t<=0xff; t=t+4)`
416	22	edn_walter	`{`
417	24	edn_walter	`cpu_hd(10);`
418
419	22	edn_walter	`cpu_addr_i = t;`
420	21	edn_walter	`cpu_rd(cpu_addr_i, &cpu_data_o);`
421	22	edn_walter	`}`
422	21	edn_walter	`}`
423
424			`return(0); /* Return success (required by tasks) */`
425			`}`

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