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[/] [ha1588/] [trunk/] [sim/] [tsu/] [tsu_queue_tb.v] - Blame information for rev 34

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1 34 edn_walter
/*
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 * $tsu_queue_tb.v
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 *
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 * Copyright (c) 2012, BBY&HW. All rights reserved.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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 * MA 02110-1301  USA
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 */
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22 4 ash_riple
`timescale 1ns/1ns
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module tsu_queue_tb;
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26 5 ash_riple
reg         rst;
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wire        gmii_rxclk;
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wire        gmii_rxctrl;
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wire [ 7:0] gmii_rxdata;
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wire        gmii_txclk;
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wire        gmii_txctrl;
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wire [ 7:0] gmii_txdata;
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reg         rtc_timer_clk;
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reg  [79:0] rtc_timer_in;
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reg         q_rd_clk;
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reg         q_rd_en;
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wire [ 7:0] q_rd_stat;
38 32 edn_walter
wire [63:0] q_rd_data;
39 4 ash_riple
 
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initial begin
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  // emulate the hardware behavior when power-up
42 4 ash_riple
  DUT_RX.ts_ack = 1'b0;
43 13 edn_walter
  DUT_TX.ts_ack = 1'b0;
44 4 ash_riple
 
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      rst = 1'b0;
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  #10 rst = 1'b1;
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  #20 rst = 1'b0;
48 13 edn_walter
 
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  fork
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    @(posedge BFM_RX.eof_rx);
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    @(posedge BFM_TX.eof_tx);
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  join
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  #100 $stop;
54 4 ash_riple
end
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initial begin
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             q_rd_clk = 1'b0;
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  forever #5 q_rd_clk = !q_rd_clk;
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end
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initial begin
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             rtc_timer_clk = 1'b0;
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  forever #4 rtc_timer_clk = !rtc_timer_clk;
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end
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initial begin
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                                   rtc_timer_in = 80'd0;
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  forever @(posedge rtc_timer_clk) rtc_timer_in = rtc_timer_in +1;
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end
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71 15 edn_walter
tsu DUT_RX
72 4 ash_riple
  (
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    .rst(rst),
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    .gmii_clk(gmii_rxclk),
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    .gmii_ctrl(gmii_rxctrl),
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    .gmii_data(gmii_rxdata),
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    .rtc_timer_clk(rtc_timer_clk),
80 32 edn_walter
    .rtc_timer_in(rtc_timer_in),
81 5 ash_riple
 
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    .q_rst(rst),
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    .q_rd_clk(q_rd_clk),
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    .q_rd_en(q_rd_en),
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    .q_rd_stat(q_rd_stat),
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    .q_rd_data(q_rd_data)
87 4 ash_riple
  );
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gmii_rx_bfm BFM_RX
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  (
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    .gmii_rxclk(gmii_rxclk),
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    .gmii_rxctrl(gmii_rxctrl),
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    .gmii_rxdata(gmii_rxdata)
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  );
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96 13 edn_walter
 
97 15 edn_walter
tsu DUT_TX
98 4 ash_riple
  (
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    .rst(rst),
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    .gmii_clk(gmii_txclk),
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    .gmii_ctrl(gmii_txctrl),
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    .gmii_data(gmii_txdata),
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    .rtc_timer_clk(rtc_timer_clk),
106 32 edn_walter
    .rtc_timer_in(rtc_timer_in),
107 5 ash_riple
 
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    .q_rst(rst),
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    .q_rd_clk(q_rd_clk),
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    .q_rd_en(),
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    .q_rd_stat(),
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    .q_rd_data()
113 4 ash_riple
  );
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gmii_tx_bfm BFM_TX
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  (
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    .gmii_txclk(gmii_txclk),
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    .gmii_txctrl(gmii_txctrl),
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    .gmii_txdata(gmii_txdata)
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  );
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122 13 edn_walter
 
123 4 ash_riple
endmodule
124
 

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