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[/] [ha1588/] [trunk/] [sim/] [tsu/] [tsu_queue_tb.v] - Blame information for rev 8

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Line No. Rev Author Line
1 4 ash_riple
`timescale 1ns/1ns
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module tsu_queue_tb;
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5 5 ash_riple
reg         rst;
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wire        gmii_rxclk;
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wire        gmii_rxctrl;
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wire [ 7:0] gmii_rxdata;
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wire        gmii_txclk;
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wire        gmii_txctrl;
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wire [ 7:0] gmii_txdata;
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reg         rtc_timer_clk;
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reg  [79:0] rtc_timer_in;
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reg         q_rd_clk;
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reg         q_rd_en;
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wire [ 7:0] q_rd_stat;
17 7 edn_walter
wire [47:0] q_rd_data;
18 4 ash_riple
 
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initial begin
20 8 edn_walter
  // emulate the hardware behavior when power-up
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  DUT_RX.ts_ack = 1'b0;
22 8 edn_walter
  DUT_TX.ts_ack = 1'b0;
23 4 ash_riple
 
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      rst = 1'b0;
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  #10 rst = 1'b1;
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  #20 rst = 1'b0;
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end
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initial begin
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             q_rd_clk = 1'b0;
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  forever #5 q_rd_clk = !q_rd_clk;
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end
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initial begin
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             rtc_timer_clk = 1'b0;
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  forever #4 rtc_timer_clk = !rtc_timer_clk;
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end
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initial begin
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                                   rtc_timer_in = 80'd0;
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  forever @(posedge rtc_timer_clk) rtc_timer_in = rtc_timer_in +1;
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end
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tsu_queue DUT_RX
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  (
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    .rst(rst),
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    .gmii_clk(gmii_rxclk),
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    .gmii_ctrl(gmii_rxctrl),
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    .gmii_data(gmii_rxdata),
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    .rtc_timer_clk(rtc_timer_clk),
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    .rtc_timer_in(rtc_timer_in[29:0]),
54 5 ash_riple
 
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    .q_rst(rst),
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    .q_rd_clk(q_rd_clk),
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    .q_rd_en(q_rd_en),
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    .q_rd_stat(q_rd_stat),
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    .q_rd_data(q_rd_data)
60 4 ash_riple
  );
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gmii_rx_bfm BFM_RX
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  (
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    .gmii_rxclk(gmii_rxclk),
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    .gmii_rxctrl(gmii_rxctrl),
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    .gmii_rxdata(gmii_rxdata)
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  );
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tsu_queue DUT_TX
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  (
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    .rst(rst),
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    .gmii_clk(gmii_txclk),
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    .gmii_ctrl(gmii_txctrl),
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    .gmii_data(gmii_txdata),
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    .rtc_timer_clk(rtc_timer_clk),
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    .rtc_timer_in(rtc_timer_in[29:0]),
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    .q_rst(rst),
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    .q_rd_clk(q_rd_clk),
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    .q_rd_en(),
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    .q_rd_stat(),
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    .q_rd_data()
85 4 ash_riple
  );
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gmii_tx_bfm BFM_TX
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  (
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    .gmii_txclk(gmii_txclk),
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    .gmii_txctrl(gmii_txctrl),
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    .gmii_txdata(gmii_txdata)
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  );
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endmodule
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