URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sys/] [xilinx_xps/] [system.xmp] - Blame information for rev 74

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#Please do not modify this file by hand
XmpVersion: 14.3
VerMgmt: 14.3
IntStyle: default
Flow: ise
ModuleSearchPath: ../../rtl/bus/xps/pcores/ha1588_axi_v1_00_a/../../../
ModuleSearchPath: ../../
MHS File: system.mhs
Architecture: zynq
Device: xc7z020
Package: clg400
SpeedGrade: -2
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 1
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: Verilog
SimModel: BEHAVIORAL
ExternalMemSim: 0
UcfFile: data/system.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
BInfo:
LockAddr: ha1588_axi_0,C_S_AXI_REG_RNG00_BASEADDR

Line No.	Rev	Author	Line
1	73	ash_riple	`#Please do not modify this file by hand`
2			`XmpVersion: 14.3`
3			`VerMgmt: 14.3`
4			`IntStyle: default`
5			`Flow: ise`
6			`ModuleSearchPath: ../../rtl/bus/xps/pcores/ha1588_axi_v1_00_a/../../../`
7			`ModuleSearchPath: ../../`
8			`MHS File: system.mhs`
9			`Architecture: zynq`
10			`Device: xc7z020`
11			`Package: clg400`
12			`SpeedGrade: -2`
13			`UserCmd1:`
14			`UserCmd1Type: 0`
15			`UserCmd2:`
16			`UserCmd2Type: 0`
17			`GenSimTB: 0`
18			`SdkExportBmmBit: 1`
19			`SdkExportDir: SDK/SDK_Export`
20			`InsertNoPads: 0`
21			`WarnForEAArch: 1`
22			`HdlLang: Verilog`
23			`SimModel: BEHAVIORAL`
24			`ExternalMemSim: 0`
25			`UcfFile: data/system.ucf`
26			`EnableParTimingError: 1`
27			`ShowLicenseDialog: 1`
28			`BInfo:`
29			`LockAddr: ha1588_axi_0,C_S_AXI_REG_RNG00_BASEADDR`

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Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sys/] [xilinx_xps/] [system.xmp] - Blame information for rev 74