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-- Filename: lcd_driver_hd44780_module.vhd
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-- Filetype: VHDL Source Code
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-- Date: 26 oct 2012
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-- Update: -
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-- Description: VHDL Description for driving an HD44780 based LCD driver
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-- Author: J. op den Brouw
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-- State: Demo
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-- Error: -
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-- Version: 1.2alpha
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-- Copyright: (c)2012, De Haagse Hogeschool
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-- This file contains a VHDL description for driving an HD44780 based LCD
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-- driver, see for a standard information of such a display:
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-- https://decibel.ni.com/content/servlet/JiveServlet/download/2741-3-3217/hd44780.pdf
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--
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-- Currently, this driver uses the 8-bit databus mode. This is not a big problem
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-- for most FPGA's because of the numerous pins.
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--
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-- Please note that there are a lot of almost-the-same displays available, so
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-- it's not guaranteed to work with all displays available. Also, timing may differ.
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--
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-- This code is tested on a Terasic DE0-board with an optional
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-- LCD display. See the weblinks
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-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=364
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-- http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396
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-- for more info. The display used has only two lines.
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--
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jodb |
-- This VHDL description can both be simulated and synthesized.
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jodb |
--
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-- This driver has a User Side and a LCD Side. The user is to interface at the User Side
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-- and has a number of "routines" at her disposal. The User Side implements the following
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-- inputs/routines in order of priority:
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--
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-- Command inputs:
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-- init: a logic 1 initializes the display
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-- cls: a logic 1 clears the display (and goes to home)
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-- home: a logic 1 sets the cursor to row 0, column 0
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-- goto10: a logic 1 sets the cursor to row 1, column 0
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-- goto20: a logic 1 sets the cursor to row 2, column 0
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-- goto30: a logic 1 sets the cursor to row 3, column 0
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-- wr: a logic 1 writes a character to the display
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--
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-- Data inputs:
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--
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-- data: an 8-bit data to be written to the display
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--
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-- The user has one observable output:
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--
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-- busy: a logic 1 indicates that the driver is currently
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-- busy driving the display, a logic 0 indicates that
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-- the driver waits for the next command.
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--
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-- The user can supply the next generics, which are processed at
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-- instantiation of the module:
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--
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-- freq: the clock frequency at which the hardware has to run.
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-- this frequency is mandatory because of internal delays
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-- calculated, defaults to 50 MHz.
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-- areset_pol:
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-- the polarity of the reset signal, defaults to High (1)
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-- time_init1:
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-- the time to wait after Vcc > 4.5 V
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-- time_init2:
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-- the time to wait after first "contact"
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-- time_init3:
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-- the time to wait after the second contact
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-- time_tas:
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-- the RW and RS signal setup time with respect to the positive
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-- edge of the E pulse
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-- time_cycle_e:
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-- the complete cycle time
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-- time_pweh:
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-- the E pulse width high time
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-- time_no_bf:
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-- time to wait before command completion if no Busy Flag reading is done,
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-- some designs connect RW to logic 0, so reading from the LCD is not
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-- possible, saves a pin.
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-- cursor_on:
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-- true to set the cursor on at the display, false for no cursor
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-- blink_on:
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-- true to let the cursor blink, false for no blink (just a underscore)
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-- use_bf: true if Busy Flag reading is to be used, false for no BF reading
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--
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-- Note: it's not possible to write command codes to the display.
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--
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-- Changes to v1.0: LCD_E is renamed to LCD_EN
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-- LCD_DB is renamed to LCD_DATA
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-- busy is now registered
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-- removed hardware simulation architecture
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--
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-- Changes to v1.1: added timing generics for better steering of the E pulse cycle
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-- implemented cursor on/off/blink with generic parameters
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--
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-- Changes to v1.2: added Busy Flag reading mode, selectable at instantiation time
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-- LCD_EN changes back to LCD_E
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-- LCD_DATA changed back to LCD_DB
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--
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-- To do: use 4-bit mode or 8-bit mode at instantiation time
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--
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-- The libraries to use.
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library ieee;
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use ieee.std_logic_1164.all;
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-- The entity of the LCD Driver Module.
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entity lcd_driver_hd44780_module is
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generic (freq : integer := 50000000;
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areset_pol : std_logic := '1';
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time_init1 : time := 40 ms;
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time_init2 : time := 4100 us;
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time_init3 : time := 100 us;
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time_tas : time := 60 ns;
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time_cycle_e : time := 1000 ns;
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time_pweh : time := 500 ns;
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time_no_bf : time := 2 ms;
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cursor_on : boolean := false;
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blink_on : boolean := false;
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use_bf : boolean := true
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);
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port (clk : in std_logic;
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areset : in std_logic;
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-- User site
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init : in std_logic;
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data : in std_logic_vector(7 downto 0);
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wr : in std_logic;
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cls : in std_logic;
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home : in std_logic;
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goto10 : in std_logic;
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goto20 : in std_logic;
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goto30 : in std_logic;
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busy : out std_logic;
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-- LCD side
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LCD_E : out std_logic;
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LCD_RS : out std_logic;
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LCD_RW : out std_logic;
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LCD_DB : inout std_logic_vector(7 downto 0)
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);
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end entity lcd_driver_hd44780_module;
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-- This architecture drives the LCD.
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architecture hardware_driver of lcd_driver_hd44780_module is
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-- Delays... Please note that if the frequency is (too) low,
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-- some of the delays will 0. The code will take care of that.
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-- Converting time to integer is problematic. Please note the use of
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-- the simulator time step in the calculations.
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-- The simulator timestep
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constant simulator_timestep : time := 1 ns;
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-- Number of simulator timesteps per second.
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constant sim_steps_per_sec : real := real(1 sec/simulator_timestep);
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constant delay_init1 : integer := integer( real(freq) * real(time_init1/simulator_timestep) / sim_steps_per_sec);
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constant delay_init2 : integer := integer( real(freq) * real(time_init2/simulator_timestep) / sim_steps_per_sec);
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constant delay_init3 : integer := integer( real(freq) * real(time_init3/simulator_timestep) / sim_steps_per_sec);
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constant delay_tas : integer := integer( real(freq) * real(time_tas/simulator_timestep) / sim_steps_per_sec);
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constant delay_cycle_e : integer := integer( real(freq) * real(time_cycle_e/simulator_timestep) / sim_steps_per_sec);
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constant delay_pweh : integer := integer( real(freq) * real(time_pweh/simulator_timestep) / sim_steps_per_sec);
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constant delay_no_bf : integer := integer( real(freq) * real(time_no_bf/simulator_timestep) / sim_steps_per_sec);
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-- The next statements do work in Quartus but not in (32 bit) ModelSim...
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--constant delay_init1 : integer := integer(real(freq)*real(time'pos(time_init1)) / real(time'pos(1 sec)));
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--constant delay_init2 : integer := integer(real(freq)*real(time'pos(time_init2)) / real(time'pos(1 sec)));
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--constant delay_init3 : integer := integer(real(freq)*real(time'pos(time_init3)) / real(time'pos(1 sec)));
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--constant delay_tas : integer := integer(real(freq)*real(time'pos(time_tas)) / real(time'pos(1 sec)));
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--constant delay_cycle_e : integer := integer(real(freq)*real(time'pos(time_cycle_e)) / real(time'pos(1 sec)));
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--constant delay_pweh : integer := integer(real(freq)*real(time'pos(time_pweh)) / real(time'pos(1 sec)));
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--constant delay_no_bf : integer := integer(real(freq)*real(time'pos(time_no_bf)) / real(time'pos(1 sec)));
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-- Time the E signal must be low following E high
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constant delay_pwel : integer := delay_cycle_e-delay_pweh;
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-- Counter for the delays. Timer would be a better choice.
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-- Range should be to the longest delay.
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signal delay_counter : integer range 0 to delay_init1;
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-- Should we use Busy Flag reading?
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signal use_bf_int : std_logic;
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-- The states of the state machine.
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type state_type is (reset, command_init, command_init_1, command_init_2, command_init_3,
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command_init_4, command_init_5, command_init_6, command_init_7, command_init_8,
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command_init_9, command_init_10, command_init_11, command_init12,
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wait_for_command,
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command_cls, command_home,
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command_goto10, command_goto20, command_goto30, command_wr,
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pulse_e, pulse_e_1, pulse_e_2, pulse_e_3, pulse_e_4,
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pulse_busy_flag, pulse_busy_flag_1, pulse_busy_flag_2, pulse_busy_flag_3,
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pulse_busy_flag_4, pulse_busy_flag_5);
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-- The current state and one for the return state (to facilitate return to the caller).
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signal current_state, return_state : state_type;
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begin
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-- The state machine ;-)
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nsl_state: process (clk, areset) is
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-- Function to translate a boolean to std_logic
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function bool_to_stdlogic(l: boolean) return std_logic is
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begin
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if l then
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return('1');
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else
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return('0');
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end if;
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end function bool_to_stdlogic;
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begin
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if (areset = '1' and areset_pol = '1') or (areset = '0' and areset_pol = '0') then
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current_state <= reset;
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delay_counter <= 0;
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busy <= '1';
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LCD_DB <= (others => 'Z');
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LCD_E <= '0';
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LCD_RS <= '0';
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LCD_RW <= '0';
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use_bf_int <= '0';
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elsif rising_edge(clk) then
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-- Default is busy
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busy <= '1';
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-- Default values of the LCD side
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LCD_E <= '0';
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LCD_RW <= '0';
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case current_state is
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when reset|command_init =>
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-- The logic is reset. Start initialization routine.
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LCD_DB <= (others => 'Z');
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LCD_RS <= '0';
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use_bf_int <= '0';
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delay_counter <= delay_init1;
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current_state <= command_init_1;
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when command_init_1 =>
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-- Wait until Vcc > 4.5 V...
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LCD_DB <= (others => 'Z');
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LCD_RS <= '0';
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use_bf_int <= '0';
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-- If done write 0x30 to the LCD
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if delay_counter = 0 or delay_counter = 1 then
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LCD_DB <= "00110000"; -- 0x30
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current_state <= pulse_e;
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return_state <= command_init_2;
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else
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delay_counter <= delay_counter-1;
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end if;
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when command_init_2 =>
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-- Next, set up wait for 4.1 ms
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LCD_DB <= (others => 'Z');
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LCD_RS <= '0';
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use_bf_int <= '0';
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delay_counter <= delay_init2;
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current_state <= command_init_3;
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when command_init_3 =>
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-- Wait...
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LCD_DB <= (others => 'Z');
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LCD_RS <= '0';
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use_bf_int <= '0';
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-- If done write 0x30 to the LCD
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if delay_counter = 0 or delay_counter = 1 then
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LCD_DB <= "00110000"; -- 0x30
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current_state <= pulse_e;
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return_state <= command_init_4;
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else
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delay_counter <= delay_counter-1;
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end if;
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when command_init_4 =>
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-- Next, set up wait for 100 us
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LCD_DB <= (others => 'Z');
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LCD_RS <= '0';
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use_bf_int <= '0';
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delay_counter <= delay_init3;
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current_state <= command_init_5;
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when command_init_5 =>
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-- Wait...
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LCD_DB <= (others => 'Z');
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LCD_RS <= '0';
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use_bf_int <= '0';
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-- If done write 0x30 to the LCD
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if delay_counter = 0 or delay_counter = 1 then
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LCD_DB <= "00110000"; -- 0x30
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current_state <= pulse_e;
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return_state <= command_init_6;
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else
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delay_counter <= delay_counter-1;
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end if;
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when command_init_6 =>
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-- Power up is now done, so let's enter some reasonable values...
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LCD_DB <= "00110000";
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LCD_RS <= '0';
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use_bf_int <= bool_to_stdlogic(use_bf);
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current_state <= pulse_e;
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return_state <= command_init_7;
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when command_init_7 =>
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-- 8-bit bus, 2(?) lines, 5x7 characters
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LCD_DB <= "00111100"; -- 0x3C
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LCD_RS <= '0';
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current_state <= pulse_e;
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return_state <= command_init_8;
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when command_init_8 =>
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-- Display off
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LCD_DB <= "00001000"; -- 0x08
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LCD_RS <= '0';
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current_state <= pulse_e;
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return_state <= command_init_9;
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when command_init_9 =>
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-- Display clear
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LCD_DB <= "00000001"; -- 0x01
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LCD_RS <= '0';
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current_state <= pulse_e;
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return_state <= command_init_10;
|
| 308 |
|
|
when command_init_10 =>
|
| 309 |
|
|
-- Display on, cursor and blink...
|
| 310 |
|
|
LCD_DB <= "000011" & bool_to_stdlogic(cursor_on) & bool_to_stdlogic(blink_on); -- 0x0C + ...
|
| 311 |
|
|
LCD_RS <= '0';
|
| 312 |
|
|
current_state <= pulse_e;
|
| 313 |
|
|
return_state <= command_init_11;
|
| 314 |
|
|
when command_init_11 =>
|
| 315 |
|
|
-- Mode set, increment cursor address, cursor shift
|
| 316 |
|
|
LCD_DB <= "00000110"; -- 0x06
|
| 317 |
|
|
LCD_RS <= '0';
|
| 318 |
|
|
current_state <= pulse_e;
|
| 319 |
|
|
return_state <= wait_for_command;
|
| 320 |
|
|
|
| 321 |
|
|
-- The command dispatcher! This state waits for one of
|
| 322 |
|
|
-- the command inputs to be logic '1' and 'starts' the
|
| 323 |
|
|
-- accompanying routine. Note the priority encoding!
|
| 324 |
|
|
when wait_for_command =>
|
| 325 |
|
|
LCD_DB <= (others => 'Z');
|
| 326 |
|
|
LCD_RS <= '0';
|
| 327 |
|
|
busy <= '0';
|
| 328 |
|
|
if init = '1' then
|
| 329 |
|
|
busy <= '1';
|
| 330 |
|
|
current_state <= command_init;
|
| 331 |
|
|
elsif cls = '1' then
|
| 332 |
|
|
busy <= '1';
|
| 333 |
|
|
current_state <= command_cls;
|
| 334 |
|
|
elsif home = '1' then
|
| 335 |
|
|
busy <= '1';
|
| 336 |
|
|
current_state <= command_home;
|
| 337 |
|
|
elsif goto10 = '1' then
|
| 338 |
|
|
busy <= '1';
|
| 339 |
|
|
current_state <= command_goto10;
|
| 340 |
|
|
elsif goto20 = '1' then
|
| 341 |
|
|
busy <= '1';
|
| 342 |
|
|
current_state <= command_goto20;
|
| 343 |
|
|
elsif goto30 = '1' then
|
| 344 |
|
|
busy <= '1';
|
| 345 |
|
|
current_state <= command_goto30;
|
| 346 |
|
|
elsif wr = '1' then
|
| 347 |
|
|
-- Read in data! Do NOT forget that here!
|
| 348 |
|
|
LCD_DB <= data;
|
| 349 |
|
|
busy <= '1';
|
| 350 |
|
|
current_state <= command_wr;
|
| 351 |
|
|
end if;
|
| 352 |
|
|
|
| 353 |
|
|
when command_cls =>
|
| 354 |
|
|
-- Display clear
|
| 355 |
|
|
LCD_DB <= "00000001";
|
| 356 |
|
|
LCD_RS <= '0';
|
| 357 |
|
|
current_state <= pulse_e;
|
| 358 |
|
|
return_state <= wait_for_command;
|
| 359 |
|
|
|
| 360 |
|
|
when command_home =>
|
| 361 |
|
|
-- Cursor home
|
| 362 |
|
|
LCD_DB <= "00000010";
|
| 363 |
|
|
LCD_RS <= '0';
|
| 364 |
|
|
current_state <= pulse_e;
|
| 365 |
|
|
return_state <= wait_for_command;
|
| 366 |
|
|
|
| 367 |
|
|
when command_goto10 =>
|
| 368 |
|
|
-- Cursor to beginning of line 2nd line...
|
| 369 |
|
|
LCD_DB <= "11000000"; --0x80+0x40;
|
| 370 |
|
|
LCD_RS <= '0';
|
| 371 |
|
|
current_state <= pulse_e;
|
| 372 |
|
|
return_state <= wait_for_command;
|
| 373 |
|
|
|
| 374 |
|
|
when command_goto20 =>
|
| 375 |
|
|
-- Cursor to beginning of line 3rd line...
|
| 376 |
|
|
LCD_DB <= "10010000"; --0x80+0x10;
|
| 377 |
|
|
LCD_RS <= '0';
|
| 378 |
|
|
current_state <= pulse_e;
|
| 379 |
|
|
return_state <= wait_for_command;
|
| 380 |
|
|
|
| 381 |
|
|
when command_goto30 =>
|
| 382 |
|
|
-- Cursor to beginning of line 4th line...
|
| 383 |
|
|
LCD_DB <= "11010000"; --0x80+0x50;
|
| 384 |
|
|
LCD_RS <= '0';
|
| 385 |
|
|
current_state <= pulse_e;
|
| 386 |
|
|
return_state <= wait_for_command;
|
| 387 |
|
|
|
| 388 |
|
|
when command_wr =>
|
| 389 |
|
|
-- Start character write cycle
|
| 390 |
|
|
-- Do NOT set data here!
|
| 391 |
|
|
LCD_RS <= '1';
|
| 392 |
|
|
current_state <= pulse_e;
|
| 393 |
|
|
return_state <= wait_for_command;
|
| 394 |
|
|
|
| 395 |
|
|
-- --
|
| 396 |
|
|
-- Provide E strobing for data transfer.
|
| 397 |
|
|
-- Writes data byte to the LCD.
|
| 398 |
|
|
-- Please note, DATA and RS are set by the caller!
|
| 399 |
|
|
when pulse_e =>
|
| 400 |
|
|
-- wait 60 ns before E -> 1 (tAS)
|
| 401 |
|
|
delay_counter <= delay_tas;
|
| 402 |
|
|
current_state <= pulse_e_1;
|
| 403 |
|
|
when pulse_e_1 =>
|
| 404 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 405 |
|
|
-- timer set: E = 1 for 500 ns (PWeh)
|
| 406 |
|
|
delay_counter <= delay_pweh;
|
| 407 |
|
|
current_state <= pulse_e_2;
|
| 408 |
|
|
else
|
| 409 |
|
|
delay_counter <= delay_counter-1;
|
| 410 |
|
|
end if;
|
| 411 |
|
|
when pulse_e_2 =>
|
| 412 |
|
|
LCD_E <= '1';
|
| 413 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 414 |
|
|
-- timer set: E = 0 for 500 ns (tCycleE-PWeh)
|
| 415 |
|
|
delay_counter <= delay_pwel;
|
| 416 |
|
|
current_state <= pulse_e_3;
|
| 417 |
|
|
else
|
| 418 |
|
|
delay_counter <= delay_counter-1;
|
| 419 |
|
|
end if;
|
| 420 |
|
|
when pulse_e_3 =>
|
| 421 |
|
|
LCD_E <= '0';
|
| 422 |
|
|
-- Command completion, check for use busy flag
|
| 423 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 424 |
|
|
-- If no busy flag used, wait for a amount of time.
|
| 425 |
|
|
if use_bf_int = '0' then
|
| 426 |
|
|
delay_counter <= delay_no_bf;
|
| 427 |
|
|
current_state <= pulse_e_4;
|
| 428 |
|
|
else -- BF used
|
| 429 |
|
|
current_state <= pulse_busy_flag;
|
| 430 |
|
|
end if;
|
| 431 |
|
|
else
|
| 432 |
|
|
delay_counter <= delay_counter-1;
|
| 433 |
|
|
end if;
|
| 434 |
|
|
when pulse_e_4 =>
|
| 435 |
|
|
-- Wait for the delay to finsh and then return to the caller.
|
| 436 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 437 |
|
|
current_state <= return_state;
|
| 438 |
|
|
else
|
| 439 |
|
|
delay_counter <= delay_counter-1;
|
| 440 |
|
|
end if;
|
| 441 |
|
|
|
| 442 |
|
|
-- Let's read the busy flag, see if the module is busy...
|
| 443 |
|
|
when pulse_busy_flag =>
|
| 444 |
|
|
LCD_DB <= (others => 'Z');
|
| 445 |
|
|
LCD_RW <= '1';
|
| 446 |
|
|
LCD_RS <= '0';
|
| 447 |
|
|
-- wait 60 ns before E -> 1 (tAS)
|
| 448 |
|
|
delay_counter <= delay_tas;
|
| 449 |
|
|
current_state <= pulse_busy_flag_1;
|
| 450 |
|
|
when pulse_busy_flag_1 =>
|
| 451 |
|
|
LCD_RW <= '1';
|
| 452 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 453 |
|
|
-- timer set: E = 1 for 500 ns (tPWeh)
|
| 454 |
|
|
delay_counter <= delay_pweh;
|
| 455 |
|
|
current_state <= pulse_busy_flag_2;
|
| 456 |
|
|
else
|
| 457 |
|
|
delay_counter <= delay_counter-1;
|
| 458 |
|
|
end if;
|
| 459 |
|
|
when pulse_busy_flag_2 =>
|
| 460 |
|
|
LCD_E <= '1';
|
| 461 |
|
|
LCD_RW <= '1';
|
| 462 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 463 |
|
|
-- timer set: E = 0 for 500 ns (tPWel)
|
| 464 |
|
|
delay_counter <= delay_pwel;
|
| 465 |
|
|
current_state <= pulse_busy_flag_3;
|
| 466 |
|
|
else
|
| 467 |
|
|
delay_counter <= delay_counter-1;
|
| 468 |
|
|
end if;
|
| 469 |
|
|
when pulse_busy_flag_3 =>
|
| 470 |
|
|
LCD_E <= '0';
|
| 471 |
|
|
LCD_RW <= '1';
|
| 472 |
|
|
if LCD_DB(7) = '0' then
|
| 473 |
|
|
-- operation ended
|
| 474 |
|
|
current_state <= pulse_busy_flag_4;
|
| 475 |
|
|
else
|
| 476 |
|
|
-- operation in progress
|
| 477 |
|
|
current_state <= pulse_busy_flag_5;
|
| 478 |
|
|
end if;
|
| 479 |
|
|
when pulse_busy_flag_4 =>
|
| 480 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 481 |
|
|
-- Operation ended, return caller
|
| 482 |
|
|
current_state <= return_state;
|
| 483 |
|
|
else
|
| 484 |
|
|
delay_counter <= delay_counter-1;
|
| 485 |
|
|
end if;
|
| 486 |
|
|
when pulse_busy_flag_5 =>
|
| 487 |
|
|
if delay_counter = 0 or delay_counter = 1 then
|
| 488 |
|
|
-- Operation in progress, read BF again
|
| 489 |
|
|
current_state <= pulse_busy_flag;
|
| 490 |
|
|
else
|
| 491 |
|
|
delay_counter <= delay_counter-1;
|
| 492 |
|
|
end if;
|
| 493 |
|
|
|
| 494 |
|
|
when others => null;
|
| 495 |
|
|
end case;
|
| 496 |
|
|
end if;
|
| 497 |
|
|
|
| 498 |
|
|
end process;
|
| 499 |
|
|
|
| 500 |
|
|
end architecture hardware_driver;
|
