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[/] [hd44780_driver/] [trunk/] [tb_lcd_driver_hd44780_module.vhd] - Blame information for rev 6

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-- Filename:     tb_lcd_driver_hd44780_module.do
-- Filetype:     VHDL Testbench
-- Date:         26 oct 2012
-- Update:       -
-- Description:  VHDL Testbench for simulation
-- Author:       J. op den Brouw
-- State:        Demo
-- Error:        -
-- Version:      1.1alpha
-- Copyright:    (c)2012, De Haagse Hogeschool
 
-- This file contains a very simple VHDL testbench for a HD44780 LCD
-- display, see more specs at
-- 
-- This VHDL code implements a simple testbench for testing
-- the LCD Module Driver. More scripting should be done here.
 
-- The libraries et al.
library ieee;
use ieee.std_logic_1164.all;
 
-- Empty entity
entity tb_lcd_driver_hd44780_module is
end entity tb_lcd_driver_hd44780_module;
 
-- The testbench
architecture sim of tb_lcd_driver_hd44780_module is
-- The LCD driver
component lcd_driver_hd44780_module is
        generic (freq         : integer := 50000000;
                                areset_pol   : std_logic := '1';
                                time_init1   : time := 40 ms;
                                time_init2   : time := 4100 us;
                                time_init3   : time := 100 us;
                                time_tas     : time := 60 ns;
                                time_cycle_e : time := 1000 ns;
                                time_pweh    : time := 500 ns;
                                time_no_bf   : time := 2 ms;
                                cursor_on    : boolean := false;
                                blink_on     : boolean := false;
                                use_bf       : boolean := true
                          );
        port      (clk      : in std_logic;
                           areset   : in std_logic;
                           -- User site
                           init     : in std_logic;
                           data     : in std_logic_vector(7 downto 0);
                           wr       : in std_logic;
                           cls      : in std_logic;
                           home     : in std_logic;
                           goto10   : in std_logic;
                           goto20   : in std_logic;
                           goto30   : in std_logic;
                           busy     : out std_logic;
                           -- LCD side
                           LCD_E    : out std_logic;
                           LCD_RS   : out std_logic;
                           LCD_RW   : out std_logic;
                           LCD_DB   : inout std_logic_vector(7 downto 0)
                          );
end component lcd_driver_hd44780_module;
 
-- Glue signals
signal clk     : std_logic;
signal areset  : std_logic;
-- User site
signal init    : std_logic;
signal data    : std_logic_vector(7 downto 0);
signal wr      : std_logic;
signal cls     : std_logic;
signal home    : std_logic;
signal goto10  : std_logic;
signal goto20  : std_logic;
signal goto30  : std_logic;
signal busy    : std_logic;
-- LCD side
signal LCD_DB  : std_logic_vector(7 downto 0);
signal LCD_E   : std_logic;
signal LCD_RW  : std_logic;
signal LCD_RS  : std_logic;
 
--constant freq_in : integer := 10000; -- 10 kHz
constant freq_in : integer := 50000000; -- 50 MHz
constant clock_period : time := (1.0/real(freq_in)) * (1 sec);
 
-- Internal tracer
signal trace : integer;
 
-- Now let's begin...
begin
 
        -- Instantiation of the LCD Driver, some generics are used
        lcdm : lcd_driver_hd44780_module
        generic map (freq => freq_in, areset_pol => '1', time_cycle_e => 2000 ns, time_pweh => 500 ns,
                                         cursor_on => true, blink_on => true, use_bf => false)
        port map (clk => clk, areset => areset, init => init, data => data, wr => wr, cls => cls,
                                 home => home, goto10 => goto10, goto20 => goto20, goto30 => goto30, busy => busy,
                                 LCD_DB => LCD_DB, LCD_E => LCD_E, LCD_RW => LCD_RW, LCD_RS => LCD_RS);
 
        -- The clock signal generation process
        clockgen: process is
        begin
                -- give time for reset
                clk <= '0';
                areset <= '1';
                wait for 15 ns;
                areset <= '0';
                wait for 5 ns;
                -- forever: generate clock cycle for 20 ns and 50% d.c.
                loop
                        clk <= '1';
                        wait for clock_period/2;
                        clk <= '0';
                        wait for clock_period/2;
                end loop;
        end process;
 
        -- Simulating the user side of the driver
        user_side: process is
        begin
                -- All at zero
                init <= '0';
                cls <= '0';
                home <= '0';
                goto10 <= '0';
                goto20 <= '0';
                goto30 <= '0';
                wr <= '0';
                data <= (others => '0');
                wait until clk = '1';
 
                -- wait for initialization to complete
                wait until busy = '0';
 
                -- Write data to LCD
                wait until clk = '1';
                data <= "01000011";
                wr <= '1';
                wait until clk = '1';
                wr <= '0';
                wait until busy = '0';
                wait until clk = '1';
                -- Write data to LCD
                data <= "01000011";
                wr <= '1';
                wait until clk = '1';
                wr <= '0';
                wait until busy = '0';
                wait until clk = '1';
 
                -- Clear the screen
                wait until clk = '1';
                cls <= '1';
                wait until clk = '1';
                cls <= '0';
                wait until busy = '0';
 
                -- Home the screen
                wait until clk = '1';
                home <= '1';
                wait until clk = '1';
                home <= '0';
                wait until busy = '0';
 
                -- Goto line
                wait until clk = '1';
                goto10 <= '1';
                wait until clk = '1';
                goto10 <= '0';
                wait until busy = '0';
                wait until clk = '1';
                goto20 <= '1';
                wait until clk = '1';
                goto20 <= '0';
                wait until busy = '0';
                wait until clk = '1';
                goto30 <= '1';
                wait until clk = '1';
                goto30 <= '0';
                wait until busy = '0';
 
                -- Write data to LCD
                wait until clk = '1';
                wr <= '1';
                wait until clk = '1';
                wr <= '0';
                wait until busy = '0';
                wait until clk = '1';
 
                -- Initialize the LCD
                wait until clk = '1';
                init <= '1';
                wait until clk = '1';
                init <= '0';
                wait until busy = '0';
                wait until clk = '1';
 
                wait;
        end process;
 
        -- Simple simulation description of the LCD itself...
        -- (probably too simple)
        lcd_module_sim: process is
        begin
                trace <= 0;
                LCD_DB <= (others => 'Z');
                -- Wait for reset clear
                wait until areset = '0';
                trace <= 1;
                -- Three writes to the LCD, no busy flag testing possible
                wait until LCD_E = '1';
                wait until LCD_E = '1';
                wait until LCD_E = '1';
                trace <= 2;
 
                loop
                        -- command/data written to
                        trace <= 3;
                        wait until LCD_E = '1';
                        trace <= 4;
                        wait until LCD_E = '0';
 
                        -- busy flag reading
                        trace <= 5;
                        wait until LCD_E = '1';
                        trace <= 6;
                        if LCD_RW = '1' then
                                trace <= 61;
                                -- Signal LCD is busy
                                LCD_DB <= "1ZZZZZZZ";
                                -- Internal delay of the LCD for some commands
                                wait for 40 us;
                                -- Signal LCD is ready
                                LCD_DB <= "0ZZZZZZZ";
                        end if;
                        wait until LCD_E = '0';
                        trace <= 7;
                        if LCD_RW = '1' then
                                trace <= 1;
                                LCD_DB <= "ZZZZZZZZ";
                        end if;
 
                end loop;
                wait;
        end process;
 
end architecture;

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Subversion Repositories hd44780_driver

[/] [hd44780_driver/] [trunk/] [tb_lcd_driver_hd44780_module.vhd] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	jodb	`-- Filename: tb_lcd_driver_hd44780_module.do`
2			`-- Filetype: VHDL Testbench`
3			`-- Date: 26 oct 2012`
4			`-- Update: -`
5			`-- Description: VHDL Testbench for simulation`
6			`-- Author: J. op den Brouw`
7			`-- State: Demo`
8			`-- Error: -`
9			`-- Version: 1.1alpha`
10			`-- Copyright: (c)2012, De Haagse Hogeschool`
11
12			`-- This file contains a very simple VHDL testbench for a HD44780 LCD`
13			`-- display, see more specs at`
14			`--`
15			`-- This VHDL code implements a simple testbench for testing`
16			`-- the LCD Module Driver. More scripting should be done here.`
17
18			`-- The libraries et al.`
19			`library ieee;`
20			`use ieee.std_logic_1164.all;`
21
22			`-- Empty entity`
23			`entity tb_lcd_driver_hd44780_module is`
24			`end entity tb_lcd_driver_hd44780_module;`
25
26			`-- The testbench`
27			`architecture sim of tb_lcd_driver_hd44780_module is`
28			`-- The LCD driver`
29			`component lcd_driver_hd44780_module is`
30			`generic (freq : integer := 50000000;`
31			`areset_pol : std_logic := '1';`
32			`time_init1 : time := 40 ms;`
33			`time_init2 : time := 4100 us;`
34			`time_init3 : time := 100 us;`
35			`time_tas : time := 60 ns;`
36			`time_cycle_e : time := 1000 ns;`
37			`time_pweh : time := 500 ns;`
38			`time_no_bf : time := 2 ms;`
39			`cursor_on : boolean := false;`
40			`blink_on : boolean := false;`
41			`use_bf : boolean := true`
42			`);`
43			`port (clk : in std_logic;`
44			`areset : in std_logic;`
45			`-- User site`
46			`init : in std_logic;`
47			`data : in std_logic_vector(7 downto 0);`
48			`wr : in std_logic;`
49			`cls : in std_logic;`
50			`home : in std_logic;`
51			`goto10 : in std_logic;`
52			`goto20 : in std_logic;`
53			`goto30 : in std_logic;`
54			`busy : out std_logic;`
55			`-- LCD side`
56			`LCD_E : out std_logic;`
57			`LCD_RS : out std_logic;`
58			`LCD_RW : out std_logic;`
59			`LCD_DB : inout std_logic_vector(7 downto 0)`
60			`);`
61			`end component lcd_driver_hd44780_module;`
62
63			`-- Glue signals`
64			`signal clk : std_logic;`
65			`signal areset : std_logic;`
66			`-- User site`
67			`signal init : std_logic;`
68			`signal data : std_logic_vector(7 downto 0);`
69			`signal wr : std_logic;`
70			`signal cls : std_logic;`
71			`signal home : std_logic;`
72			`signal goto10 : std_logic;`
73			`signal goto20 : std_logic;`
74			`signal goto30 : std_logic;`
75			`signal busy : std_logic;`
76			`-- LCD side`
77			`signal LCD_DB : std_logic_vector(7 downto 0);`
78			`signal LCD_E : std_logic;`
79			`signal LCD_RW : std_logic;`
80			`signal LCD_RS : std_logic;`
81
82			`--constant freq_in : integer := 10000; -- 10 kHz`
83			`constant freq_in : integer := 50000000; -- 50 MHz`
84			`constant clock_period : time := (1.0/real(freq_in)) * (1 sec);`
85
86			`-- Internal tracer`
87			`signal trace : integer;`
88
89			`-- Now let's begin...`
90			`begin`
91
92			`-- Instantiation of the LCD Driver, some generics are used`
93			`lcdm : lcd_driver_hd44780_module`
94			`generic map (freq => freq_in, areset_pol => '1', time_cycle_e => 2000 ns, time_pweh => 500 ns,`
95			`cursor_on => true, blink_on => true, use_bf => false)`
96			`port map (clk => clk, areset => areset, init => init, data => data, wr => wr, cls => cls,`
97			`home => home, goto10 => goto10, goto20 => goto20, goto30 => goto30, busy => busy,`
98			`LCD_DB => LCD_DB, LCD_E => LCD_E, LCD_RW => LCD_RW, LCD_RS => LCD_RS);`
99
100			`-- The clock signal generation process`
101			`clockgen: process is`
102			`begin`
103			`-- give time for reset`
104			`clk <= '0';`
105			`areset <= '1';`
106			`wait for 15 ns;`
107			`areset <= '0';`
108			`wait for 5 ns;`
109			`-- forever: generate clock cycle for 20 ns and 50% d.c.`
110			`loop`
111			`clk <= '1';`
112			`wait for clock_period/2;`
113			`clk <= '0';`
114			`wait for clock_period/2;`
115			`end loop;`
116			`end process;`
117
118			`-- Simulating the user side of the driver`
119			`user_side: process is`
120			`begin`
121			`-- All at zero`
122			`init <= '0';`
123			`cls <= '0';`
124			`home <= '0';`
125			`goto10 <= '0';`
126			`goto20 <= '0';`
127			`goto30 <= '0';`
128			`wr <= '0';`
129			`data <= (others => '0');`
130			`wait until clk = '1';`
131
132			`-- wait for initialization to complete`
133			`wait until busy = '0';`
134
135			`-- Write data to LCD`
136			`wait until clk = '1';`
137			`data <= "01000011";`
138			`wr <= '1';`
139			`wait until clk = '1';`
140			`wr <= '0';`
141			`wait until busy = '0';`
142			`wait until clk = '1';`
143			`-- Write data to LCD`
144			`data <= "01000011";`
145			`wr <= '1';`
146			`wait until clk = '1';`
147			`wr <= '0';`
148			`wait until busy = '0';`
149			`wait until clk = '1';`
150
151			`-- Clear the screen`
152			`wait until clk = '1';`
153			`cls <= '1';`
154			`wait until clk = '1';`
155			`cls <= '0';`
156			`wait until busy = '0';`
157
158			`-- Home the screen`
159			`wait until clk = '1';`
160			`home <= '1';`
161			`wait until clk = '1';`
162			`home <= '0';`
163			`wait until busy = '0';`
164
165			`-- Goto line`
166			`wait until clk = '1';`
167			`goto10 <= '1';`
168			`wait until clk = '1';`
169			`goto10 <= '0';`
170			`wait until busy = '0';`
171			`wait until clk = '1';`
172			`goto20 <= '1';`
173			`wait until clk = '1';`
174			`goto20 <= '0';`
175			`wait until busy = '0';`
176			`wait until clk = '1';`
177			`goto30 <= '1';`
178			`wait until clk = '1';`
179			`goto30 <= '0';`
180			`wait until busy = '0';`
181
182			`-- Write data to LCD`
183			`wait until clk = '1';`
184			`wr <= '1';`
185			`wait until clk = '1';`
186			`wr <= '0';`
187			`wait until busy = '0';`
188			`wait until clk = '1';`
189
190			`-- Initialize the LCD`
191			`wait until clk = '1';`
192			`init <= '1';`
193			`wait until clk = '1';`
194			`init <= '0';`
195			`wait until busy = '0';`
196			`wait until clk = '1';`
197
198			`wait;`
199			`end process;`
200
201			`-- Simple simulation description of the LCD itself...`
202			`-- (probably too simple)`
203			`lcd_module_sim: process is`
204			`begin`
205			`trace <= 0;`
206			`LCD_DB <= (others => 'Z');`
207			`-- Wait for reset clear`
208			`wait until areset = '0';`
209			`trace <= 1;`
210			`-- Three writes to the LCD, no busy flag testing possible`
211			`wait until LCD_E = '1';`
212			`wait until LCD_E = '1';`
213			`wait until LCD_E = '1';`
214			`trace <= 2;`
215
216			`loop`
217			`-- command/data written to`
218			`trace <= 3;`
219			`wait until LCD_E = '1';`
220			`trace <= 4;`
221			`wait until LCD_E = '0';`
222
223			`-- busy flag reading`
224			`trace <= 5;`
225			`wait until LCD_E = '1';`
226			`trace <= 6;`
227			`if LCD_RW = '1' then`
228			`trace <= 61;`
229			`-- Signal LCD is busy`
230			`LCD_DB <= "1ZZZZZZZ";`
231			`-- Internal delay of the LCD for some commands`
232			`wait for 40 us;`
233			`-- Signal LCD is ready`
234			`LCD_DB <= "0ZZZZZZZ";`
235			`end if;`
236			`wait until LCD_E = '0';`
237			`trace <= 7;`
238			`if LCD_RW = '1' then`
239			`trace <= 1;`
240			`LCD_DB <= "ZZZZZZZZ";`
241			`end if;`
242
243			`end loop;`
244			`wait;`
245			`end process;`
246
247			`end architecture;`